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CD4013BC

CD4013BC

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 © 2002 Fairchild Semiconductor CorporationDS005946www.fairchildsemi.comOctober 1987Revised March 2002
 C  0  3  C   u al   y p el  i   pl   o p
CD4013BCDual D-Type Flip-Flop
General Description
The CD4013B dual D-type flip-flop is a monolithic comple-mentary MOS (CMOS) integrated circuit constructed withN- and P-channel enhancement mode transistors. Eachflip-flop has independent data, set, reset, and clock inputsand “Q” and “Q” outputs. These devices can be used forshift register applications, and by connecting “Q” output tothe data input, for counter and toggle applications. Thelogic level present at the “D” input is transferred to the Qoutput during the positive-going transition of the clockpulse. Setting or resetting is independent of the clock andis accomplished by a high level on the set or reset linerespectively.
Features
s
Wide supply voltage range: 3.0V to 15V
s
High noise immunity:0.45 V
DD
(typ.)
s
Low power TTL:fan out of 2 driving 74Lcompatibility:or 1 driving 74LS
Applications
AutomotiveData terminalsInstrumentationMedical electronicsAlarm systemIndustrial electronicsRemote meteringComputers 
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter
X
to the ordering code.
Connection Diagram
Top View
Truth Table
No Changex
=
Don't Care Case
Note 1:
Level Change
Order NumberPackage NumberPackage Description
CD4013BCMM14A14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" NarrowCD4013BCSJM14D14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WideCD4013BCNN14A14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CL(Note 1)DRSQQ
 
00001
 
10010
 
x00QQxx1001xx0110xx1111
 
www.fairchildsemi.com2
      C      D      4      0      1      3      B      C
Schematic Diagrams
 
Logic Diagram
 
3www.fairchildsemi.com
 C  0  3  C 
Absolute Maximum Ratings
(Note 2)(Note 3)
Recommended OperatingConditions
(Note 3)
Note 2:
Absolute Maximum Ratings
are those values beyond which thesafety of the device cannot be guaranteed, they are not meant to imply thatthe devices should be operated at these limits. The tables of
Recom-mended Operating Conditions
and
Electrical Characteristics
provide con-ditions for actual device operation.
Note 3:
V
SS
 
=
0V unless otherwise specified.
DC Electrical Characteristics
(Note 3)
Note 4:
I
OH
and I
OL
are measured one output at a time.
DC Supply Voltage (V
DD
)
0.5 V
DC
to
+
18 V
DC
Input Voltage (V
IN
)
0.5 V
DC
to V
DD
 
+
0.5 V
DC
Storage Temperature Range (T
S
)
65
°
C to
+
150
°
CPower Dissipation (P
D
)Dual-In-Line700 mWSmall Outline500 mWLead Temperature (T
L
)(Soldering, 10 seconds)260
°
CDC Supply Voltage (V
DD
)
+
3 V
DC
to
+
15 V
DC
Input Voltage (V
IN
)0 V
DC
to V
DD
V
DC
Operating Temperature Range (T
A
)
55
°
C to
+
125
°
C
SymbolParameterConditions
55
°
C
+
25
°
C
+
125
°
CUnitsMinMaxMinTypMaxMinMax
I
DD
Quiescent DeviceV
DD
 
=
5V, V
IN
 
=
V
DD
or V
SS
1.01.030
µ
ACurrentV
DD
 
=
10V, V
IN
 
=
V
DD
or V
SS
2.02.060V
DD
 
=
15V, V
IN
 
=
V
DD
or V
SS
4.04.0120V
OL
LOW Level|I
O
|
<
1.0
µ
AVOutput VoltageV
DD
 
=
5V0.050.050.05V
DD
 
=
10V0.050.050.05V
DD
 
=
15V0.050.050.05V
OH
HIGH Level|I
O
|
<
1.0
µ
AVOutput VoltageV
DD
 
=
5V4.954.954.95V
DD
 
=
10V9.959.959.95V
DD
 
=
15V14.9514.9514.95V
IL
LOW Level|I
O
|
<
1.0
µ
AVInput VoltageV
DD
 
=
5V, V
O
 
=
0.5V or 4.5V1.51.51.5V
DD
 
=
10V, V
O
 
=
1.0V or 9.0V3.03.03.0V
DD
 
=
15V, V
O
 
=
1.5V or 13.5V4.04.04.0V
IH
HIGH Level|I
O
|
<
1.0
µ
AVInput VoltageV
DD
 
=
5V, V
O
 
=
0.5V or 4.5V3.53.53.5V
DD
 
=
10V, V
O
 
=
1.0V or 9.0V7.07.07.0V
DD
 
=
15V, V
O
 
=
1.5V or 13.5V11.011.011.0I
OL
LOW Level OutputV
DD
 
=
5V, V
O
 
=
0.4V0.640.510.880.36mACurrent (Note 4)V
DD
 
=
10V, V
O
 
=
0.5V1.61.32.250.9V
DD
 
=
15V, V
O
 
=
1.5V4.23.48.82.4I
OH
HIGH Level OutputV
DD
 
=
5V, V
O
 
=
4.6V
0.64
0.51
0.88
0.36mACurrent (Note 4)V
DD
 
=
10V, V
O
 
=
9.5V
1.6
1.3
2.25
0.9V
DD
 
=
15V, V
O
 
=
13.5V
4.2
3.4
8.8
2.4I
IN
Input CurrentV
DD
 
=
15V, V
IN
 
=
0V
0.1
10
5
0.1
1.0
µ
AV
DD
 
=
15V, V
IN
 
=
15V0.110
5
0.11.0

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