Professional Documents
Culture Documents
Beeman Strong
Intel® Core™ microarchitecture
(Nehalem) Architect
Intel Corporation
Agenda
• Intel® Core™ Microarchitecture (Nehalem) Design
Overview
• Enhanced Processor Core
• Performance Features
• Intel® Hyper-Threading Technology
• New Platform
• New Cache Hierarchy
• New Platform Architecture
• Performance Acceleration
• Virtualization
• New Instructions
• Power Management Overview
• Minimizing Idle Power Consumption
• Performance when it counts
2
Scalable Cores
Same core for Common software Common feature set
all segments optimization
Intel® Core™
Microarchitecture Servers/Workstations
(Nehalem)
Energy Efficiency,
45nm Performance, Virtualization,
Reliability, Capacity,
Scalability
Desktop
Performance, Graphics,
Energy Efficiency, Idle
Power, Security
Mobile
Battery Life, Performance,
Energy Efficiency, Graphics,
Security
4
Agenda
• Intel® Core™ Microarchitecture (Nehalem) Design
Overview
• Enhanced Processor Core
• Performance Features
• Intel® Hyper-Threading Technology
• New Platform
• New Cache Hierarchy
• New Platform Architecture
• Performance Acceleration
• Virtualization
• New Instructions
• Power Management Overview
• Minimizing Idle Power Consumption
• Performance when it counts
5
Intel® Core™ Microarchitecture Recap
6
Designed for Performance
New SSE4.2 Improved Additional Caching
Instructions Lock Hierarchy
Support
7
Macrofusion
• Introduced in Intel® Core™2 microarchitecture
• TEST/CMP instruction followed by a conditional branch treated
as a single instruction
– Decode/execute/retire as one instruction
• Higher performance & improved power efficiency
– Improves throughput/Reduces execution latency
– Less processing required to accomplish the same work
• Support all the cases in Intel Core 2 microarchitecture PLUS
– CMP+Jcc macrofusion added for the following branch conditions
– JL/JNGE
– JGE/JNL
– JLE/JNG
– JG/JNLE
– Intel® Core™ microarchitecture (Nehalem) supports macrofusion
in both 32-bit and 64-bit modes
– Intel Core2 microarchitecture only supports macrofusion in 32-bit
mode
8
Intel® Core™ Microarchitecture
(Nehalem) Loop Stream Detector
• Loop Stream Detector identifies software loops
– Stream from Loop Stream Detector instead of normal path
– Disable unneeded blocks of logic for power savings
– Higher performance by removing instruction fetch limitations
• Higher performance: Expand the size of the loops detected (vs Core 2)
• Improved power efficiency: Disable even more logic (vs Core 2)
Branch Loop
Fetch Decode Stream
Prediction Detector
28
Micro-Ops
9
Branch Prediction Improvements
• Focus on improving branch prediction accuracy
each CPU generation
– Higher performance & lower power through more
accurate prediction
• Example Intel® Core™ microarchitecture (Nehalem)
improvements
– L2 Branch Predictor
– Improve accuracy for applications with large code size (ex.
database applications)
– Advanced Renamed Return Stack Buffer (RSB)
– Remove branch mispredicts on x86 RET instruction (function
returns) in the common case
10
Execution Unit Overview
Execute 6 operations/cycle
Unified Reservation Station
• 3 Memory Operations
• Schedules operations to Execution units
• 1 Load
• Single Scheduler for all Execution Units
• 1 Store Address
• Can be used by all integer, all FP, etc.
• 1 Store Data
• 3 “Computational” Operations
Port 4
Port 2
Port 1
Port 3
Port 5
Integer ALU & Integer ALU & Store Store Integer ALU &
Shift LEA Load Address Data Shift
11
Increased Parallelism
1
Concurrent uOps Possible
12
Enhanced Memory Subsystem
• Responsible for:
– Handling of memory operations (loads/stores)
• Key Intel® Core™2 Features
– Memory Disambiguation
– Hardware Prefetchers
– Advanced Smart Cache
• New Intel® Core™ Microarchitecture (Nehalem)
Features
– New TLB Hierarchy (new, low latency 2nd level unified TLB)
– Fast 16-Byte unaligned accesses
– Faster Synchronization Primitives
13
Intel® Hyper-Threading Technology
• Also known as Simultaneous Multi-
Threading (SMT) w/o SMT SMT
– Run 2 threads at the same time per core
• Take advantage of 4-wide execution engine
– Keep it fed with multiple threads
14
SMT Performance Chart
40%
Performance Gain SMT enabledvs disabled
34%
35%
29%
30%
25%
20%
16%
15% 13%
10%
10% 7%
5%
0%
FloatingPoint 3dsMax* Integer Cinebench* 10POV-Ray* 3.7 3DMark*
beta25 Vantage* CPU
Intel®Core™i7
SPEC, SPECint, SPECfp, and SPECrate are trademarks of the Standard Performance Evaluation Corporation.
For more information on SPEC benchmarks, see: http://www.spec.org
Source: Intel. Configuration: pre-production Intel® Core™ i7 processor with 3 channel DDR3 memory. Performance tests and ratings are measured
using specific computer systems and / or components and reflect the approximate performance of Intel products as measured by those tests. Any
difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information
to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the
performance of Intel products, visit http://www.intel.com/performance/
15
Agenda
• Intel® Core™ Microarchitecture (Nehalem) Design
Overview
• Enhanced Processor Core
• Performance Features
• Intel® Hyper-Threading Technology
• New Platform
• New Cache Hierarchy
• New Platform Architecture
• Performance Acceleration
• Virtualization
• New Instructions
• Power Management Overview
• Minimizing Idle Power Consumption
• Performance when it counts
16
Designed For Modularity
C C C
O O O Core
R R R
E E E
…
L3 Cache
DRAM
Uncore
Power
Intel Intel
… IM ® … ® &
C QPI QPI Clock
Intel QPI
…
Intel® QPI: Intel®
Differentiation in the QuickPath Interconnect
“Uncore”: (Intel® QPI)
18
Why Inclusive?
19
Intel® Core™ Microarchitecture
(Nehalem-EP) Platform Architecture
• Integrated Memory Controller
– 3 DDR3 channels per socket Nehalem Nehalem
– Massive memory bandwidth EP EP
– Memory Bandwidth scales with # of
processors
– Very low memory latency
Tylersburg
• Intel® QuickPath Interconnect EP
(Intel® QPI)
– New point-to-point interconnect
– Socket to socket connections
– Socket to chipset connections
IOH
– Build scalable solutions CPU CPU
memory memory
– Up to 6.4 GT/sec (12.8 GB/sec)
– Bidirectional (=> 25.6 GB/sec)
20
Non-Uniform Memory Access (NUMA)
• FSB architecture
– All memory in one location Nehalem Nehalem
• Starting with Intel Core™ ® EP EP
microarchitecture (Nehalem)
– Memory located in multiple
Tylersburg
places EP
• Latency to memory dependent
on location
• Local memory has highest Relative Memory Latency Comparison
0.60
0.40
0.00
optimized for best performance Harpertown (FSB 1600) Nehalem (DDR3-1067) Nehalem (DDR3-1067)
Local Remote
21
Memory Bandwidth – Initial Intel® Core™
Microarchitecture (Nehalem) Products
1
HTN: Intel® Xeon® processor 5400 Series (Harpertown)
NHM: Intel® Core™ microarchitecture (Nehalem)
22
Agenda
• Intel® Core™ Microarchitecture (Nehalem) Design
Overview
• Enhanced Processor Core
• Performance Features
• Intel® Hyper-Threading Technology
• New Platform
• New Cache Hierarchy
• New Platform Architecture
• Performance Acceleration
• Virtualization
• New Instructions
• Power Management Overview
• Minimizing Idle Power Consumption
• Performance when it counts
23
Virtualization
• To get best virtualized
performance
Round Trip Virtualization
– Have best native performance
1
Latency
– Reduce transitions to/from
virtual machine 100%
– Reduce latency of transitions 80%
Relative Latency
• Intel® Core™ microprocessor 60%
(Nehalem) virtualization
40%
features
– Reduced latency for transitions 20%
– Virtual Processor ID (VPID) to 0%
reduce effective cost of Merom Penryn Nehalem
transitions
– Extended Page Table (EPT) to
reduce # of transitions
24
EPT Solution
EPT
CR3 Base Pointer
25
Extending Performance and Energy Efficiency
- Intel® SSE4.2 Instruction Set Architecture (ISA) Leadership in 2008
ATA
STTNI ATA
Hardware based CRC (Application
e.g. XML
e.g. XML Targeted
instruction acceleration Accelerators)
New Communications Accelerated Network
Capabilities attached storage
Improved power efficiency
for Software I-SCSI, RDMA, POPCNT CRC32
and SCTP e.g. Genome e.g. iSCSI
Mining Application
26
Agenda
• Intel® Core™ Microarchitecture (Nehalem) Design
Overview
• Enhanced Processor Core
• Performance Features
• Intel® Hyper-Threading Technology
• New Platform
• New Cache Hierarchy
• New Platform Architecture
• Performance Acceleration
• Virtualization
• New Instructions
• Power Management Overview
• Minimizing Idle Power Consumption
• Performance when it counts
27
Intel® Core™ Microarchitecture (Nehalem)
Design Goals
World class performance combined with superior energy efficiency –
Optimized for:
Dynamically
scaled
performance
Single when
Thread
Existing
Multi- Apps
threads Emerging Apps
All Usages needed to
maximize energy
efficiency
A single, scalable, foundation optimized across each segment and power
envelope
Core
PLL
Vcc
Integrated proprietary
Freq.
Freq. PLL
Sensors
microcontroller
Core
Shifts control from
hardware to embedded
Vcc
firmware
Freq.
Freq. PLL
Sensors Real time sensors for
temperature, current,
Core
PCU power
Vcc
Freq.
Freq. PLL
Flexibility enables
Sensors sophisticated
algorithms, tuned for
Core
Uncore,
Uncore,
current operating
Vcc
LLC conditions
Freq.
Freq. PLL
Sensors
29
Minimizing Idle Power Consumption
30
C6 on Intel® Core™ Microarchitecture
(Nehalem)
31
C6 on Intel® Core™ Microarchitecture
(Nehalem)
Core Power
Cores 0, 1, 2,
and 3 running Core 3
applications.
0
Core 2
0
Core 1
0
Core 0
0
Time
32
C6 on Intel® Core™ Microarchitecture
(Nehalem)
Core Power Task completes. No
work waiting. OS
executes MWAIT(C6)
instruction. Core 3
0
Core 2
0
Core 1
0
Core 0
0
Time
33
C6 on Intel® Core™ Microarchitecture
(Nehalem)
Core Power Execution stops. Core
architectural state
saved. Core clocks
stopped. Cores 0, 1, Core 3
and 3 continue
0 execution undisturbed.
Core 2
0
Core 1
0
Core 0
0
Time
34
C6 on Intel® Core™ Microarchitecture
(Nehalem)
Core Power
Core power gate turned
off. Core voltage goes
to 0. Cores 0, 1, and 3
continue execution
Core 3
0 undisturbed.
Core 2
0
Core 1
0
Core 0
0
Time
35
C6 on Intel® Core™ Microarchitecture
(Nehalem)
Core Power
Core 3
0
Core 2
0 Task completes. No work
waiting. OS executes
MWAIT(C6) instruction. Core Core 1
0 enters C6. Cores 1 and 3
0 continue execution
undisturbed. Core 0
0
Time
36
C6 on Intel® Core™ Microarchitecture
(Nehalem)
Interrupt for Core 2 arrives.
Core Power Core 2 returns to C0,
execution resumes at
instruction following
MWAIT(C6). Cores 1 and 3 Core 3
continue execution
0 undisturbed.
Core 2
0
Core 1
0
Core 0
0
Time
37
C6 on Intel® Core™ Microarchitecture
(Nehalem)
Core Power
Core 3
0
Interrupt for Core 0 arrives. Core 2
Power gate turns on, core
0 clock turns on, core state
restored, core resumes
execution at instruction Core 1
following MWAIT(C6). Cores 1,
0 2, and 3 continue execution
undisturbed. Core 0
0
Time
Core independent C6 on Intel Core
microarchitecture (Nehalem) extends benefits
38
Intel® Core™ Microarchitecture (Nehalem)-
based Processor
Memory Controller
M M Total CPU Power
i i Consumption
s s
c c Core
Core Core Q Core Core Clocks
Cores (x N)
I u I
O e O and Logic
u
Q e Q
P P Core Clock
I I Distribution
Shared L3 Cache
0 1
Core
Leakage
Uncore Logic
• Significant logic outside core
– Integrated memory controller I/O
– Large shared cache Uncore Clock
Distribution
– High speed interconnect Uncore
– Arbitration logic Leakage
QPI = Intel® QuickPath Interconnect (Intel® QPI)
39
Intel® Core™ Microarchitecture
(Nehalem) Package C-State Support
Active CPU Power
• All cores in C6 state: Core
– Core power to ~0 Clocks
and Logic
Cores (x N)
Core Clock
Distribution
Core
Leakage
Uncore Logic
I/O
Uncore Clock
Distribution
Uncore
Leakage
40
Intel® Core™ Microarchitecture
(Nehalem) Package C-State Support
Active CPU Power
• All cores in C6 state:
– Core power to ~0
• Package to C6 state:
– Uncore logic stops toggling
Uncore Logic
I/O
Uncore Clock
Distribution
Uncore
Leakage
41
Intel® Core™ Microarchitecture
(Nehalem) Package C-State Support
Active CPU Power
• All cores in C6 state:
– Core power to ~0
• Package to C6 state:
– Uncore logic stops toggling
– I/O to lower power state
I/O
Uncore Clock
Distribution
Uncore
Leakage
42
Intel® Core™ Microarchitecture
(Nehalem) Package C-State Support
Active CPU Power
• All cores in C6 state:
– Core power to ~0
• Package to C6 state:
– Uncore logic stops toggling
– I/O to lower power state
– Uncore clock grids stopped
I/O
Uncore Clock
Distribution
Uncore
Leakage
Substantial reduction in
idle CPU power
43
Managing Active Power
• Operating system changes frequency as needed to
meet performance needs, minimize power
– Enhanced Intel SpeedStep® Technology
– Referred to as processor P-States
• PCU tunes voltage for given frequency, operating
conditions, and silicon characteristics
44
Turbo Mode: Key to Scalability Goal
45
Turbo Mode Enabling
46
Summary
47
Q&A
48
Legal Disclaimer
• INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO
LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL
PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS
AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,
AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE
OF INTEL® PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR
OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN
MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.
• Intel may make changes to specifications and product descriptions at any time, without notice.
• All products, dates, and figures specified are preliminary based on current expectations, and
are subject to change without notice.
• Intel, processors, chipsets, and desktop boards may contain design defects or errors known as
errata, which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
• Merom, Penryn, Hapertown, Nehalem, Dothan, Westmere, Sandy Bridge, and other code names
featured are used internally within Intel to identify products that are in development and not
yet publicly announced for release. Customers, licensees and other third parties are not
authorized by Intel to use code names in advertising, promotion or marketing of any product or
services and any such use of Intel's internal code names is at the sole risk of the user
• Performance tests and ratings are measured using specific computer systems and/or
components and reflect the approximate performance of Intel products as measured by those
tests. Any difference in system hardware or software design or configuration may affect actual
performance.
• Intel, Intel Inside, Intel Core, Pentium, Intel SpeedStep Technology, and the Intel logo are
trademarks of Intel Corporation in the United States and other countries.
• *Other names and brands may be claimed as the property of others.
• Copyright © 2008 Intel Corporation.
49
Risk Factors
This presentation contains forward-looking statements that involve a number of risks and uncertainties. These
statements do not reflect the potential impact of any mergers, acquisitions, divestitures, investments or other
similar transactions that may be completed in the future. The information presented is accurate only as of
today’s date and will not be updated. In addition to any factors discussed in the presentation, the important
factors that could cause actual results to differ materially include the following: Demand could be different
from Intel's expectations due to factors including changes in business and economic conditions, including
conditions in the credit market that could affect consumer confidence; customer acceptance of Intel’s and
competitors’ products; changes in customer order patterns, including order cancellations; and changes in the
level of inventory at customers. Intel’s results could be affected by the timing of closing of acquisitions and
divestitures. Intel operates in intensely competitive industries that are characterized by a high percentage of
costs that are fixed or difficult to reduce in the short term and product demand that is highly variable and
difficult to forecast. Revenue and the gross margin percentage are affected by the timing of new Intel product
introductions and the demand for and market acceptance of Intel's products; actions taken by Intel's
competitors, including product offerings and introductions, marketing programs and pricing pressures and
Intel’s response to such actions; Intel’s ability to respond quickly to technological developments and to
incorporate new features into its products; and the availability of sufficient supply of components from
suppliers to meet demand. The gross margin percentage could vary significantly from expectations based on
changes in revenue levels; product mix and pricing; capacity utilization; variations in inventory valuation,
including variations related to the timing of qualifying products for sale; excess or obsolete inventory;
manufacturing yields; changes in unit costs; impairments of long-lived assets, including manufacturing,
assembly/test and intangible assets; and the timing and execution of the manufacturing ramp and associated
costs, including start-up costs. Expenses, particularly certain marketing and compensation expenses, vary
depending on the level of demand for Intel's products, the level of revenue and profits, and impairments of
long-lived assets. Intel is in the midst of a structure and efficiency program that is resulting in several actions
that could have an impact on expected expense levels and gross margin. Intel's results could be impacted by
adverse economic, social, political and physical/infrastructure conditions in the countries in which Intel, its
customers or its suppliers operate, including military conflict and other security risks, natural disasters,
infrastructure disruptions, health concerns and fluctuations in currency exchange rates. Intel's results could be
affected by adverse effects associated with product defects and errata (deviations from published
specifications), and by litigation or regulatory matters involving intellectual property, stockholder, consumer,
antitrust and other issues, such as the litigation and regulatory matters described in Intel's SEC reports. A
detailed discussion of these and other factors that could affect Intel’s results is included in Intel’s SEC filings,
including the report on Form 10-Q for the quarter ended 50 June 28, 2008.
Backup Slides
51
Intel® Core™ Microarchitecture (Nehalem)
Design Goals
World class performance combined with superior energy efficiency –
Optimized for:
Dynamically
scaled
performance
Single when
Thread
Existing
Multi- Apps
threads Emerging Apps
All Usages needed to
maximize energy
efficiency
A single, scalable, foundation optimized across each segment and power
envelope
Sandy
Merom1 Penryn Nehalem Westmere
Bridge
NEW NEW NEW NEW NEW
Microarchitecture Process Microarchitecture Process Microarchitecture
65nm 45nm 45nm 32nm 32nm
Forecast
1
Intel® Core™ microarchitecture (formerly Merom)
45nm next generation Intel® Core™ microarchitecture (Penryn) All dates, product descriptions, availability and plans are forecasts and
Intel® Core™ Microarchitecture (Nehalem) subject to change without notice.
Intel® Microarchitecture (Westmere)
53
Intel® Microarchitecture (Sandy Bridge) 53
Enhanced Processor Core
Instruction Fetch and
ITLB
32kB Front End
Pre Decode Instruction Cache
Execution
Instruction Queue Engine
Memory
Decode
Reservation Station
6
Execution Units
DTLB
32kB
Data Cache
54
Front-end
Instruction Queue
Decode
55
Loop Stream Detector Reminder
• Loops are very common in most software
• Take advantage of knowledge of loops in HW
– Decoding the same instructions over and over
– Making the same branch predictions over and over
• Loop Stream Detector identifies software loops
– Stream from Loop Stream Detector instead of normal path
– Disable unneeded blocks of logic for power savings
– Higher performance by removing instruction fetch limitations
Loop
Branch
Fetch Stream Decode
Prediction Detector
18
Instructions
56
Branch Prediction Reminder
• Goal: Keep powerful compute engine fed
• Options:
– Stall pipeline while determining branch direction/target
– Predict branch direction/target and correct if wrong
• Minimize amount of time wasted correcting from
incorrect branch predictions
– Performance:
– Through higher branch prediction accuracy
– Through faster correction when prediction is wrong
– Power efficiency: Minimize number of
speculative/incorrect micro-ops that are executed
57
L2 Branch Predictor
58
Advanced Renamed Return Stack Buffer (RSB)
• Instruction Reminder
– CALL: Entry into functions
– RET: Return from functions
• Classical Solution
– Return Stack Buffer (RSB) used to predict RET
– RSB can be corrupted by speculative path
• The Renamed RSB
– No RET mispredicts in the common case
59
Execution Engine
• Responsible for:
– Scheduling operations
– Executing operations
• Powerful Intel® Core™2 microarchitecture execution
engine
– Dynamic 4-wide Execution
– Intel® Advanced Digital Media Boost
– 128-bit wide SSE
– Super Shuffler (45nm next generation Intel® Core™
microarchitecture (Penryn))
60
Intel® Smart Cache – Core Caches
• New 3-level Cache Hierarchy
• 1st level caches
– 32kB Instruction cache
– 32kB, 8-way Data Cache Core
32kB L1 32kB L1
– Support more L1 misses in parallel than Data Cache Inst. Cache
Intel® Core™2 microarchitecture
• 2nd level Cache
– New cache introduced in Intel® Core™
microarchitecture (Nehalem)
– Unified (holds code and data)
– 256 kB per core (8-way) 256kB
L2 Cache
– Performance: Very low latency
– 10 cycle load-to-use
– Scalability: As core count increases,
reduce pressure on shared cache
61
New TLB Hierarchy
# of Entries
1st Level Instruction TLBs
Small Page (4k) 128
Large Page (2M/4M) 7 per thread
1st Level Data TLBs
Small Page (4k) 64
Large Page (2M/4M) 32
New 2nd Level Unified TLB
Small Page Only 512
62
Fast Unaligned Cache Accesses
• Two flavors of 16-byte SSE loads/stores exist
– Aligned (MOVAPS/D, MOVDQA) -- Must be aligned on a 16-byte boundary
– Unaligned (MOVUPS/D, MOVDQU) -- No alignment requirement
• Prior to Intel® Core™ microarchitecture (Nehalem)
– Optimized for Aligned instructions
– Unaligned instructions slower, lower throughput -- Even for aligned accesses!
– Required multiple uops (not energy efficient)
– Compilers would largely avoid unaligned load
– 2-instruction sequence (MOVSD+MOVHPD) was faster
• Intel Core microarchitecture (Nehalem) optimizes Unaligned instructions
– Same speed/throughput as Aligned instructions on aligned accesses
– Optimizations for making accesses that cross 64-byte boundaries fast
– Lower latency/higher throughput than Core 2
– Aligned instructions remain fast
• No reason to use aligned instructions on Intel Core microarchitecture (Nehalem)!
• Benefits:
– Compiler can now use unaligned instructions without fear
– Higher performance on key media algorithms
– More energy efficient than prior implementations
63
Faster Synchronization Primitives
LOCK CMPXCHG Perform ance 1
• Multi-threaded software 1
becoming more prevalent 0.9
0.8
• Scalability of multi-thread 0.7
Relative Latency
applications can be limited by 0.6
0.5
synchronization 0.4
1
Intel® Pentium® 4 processor
Intel® Core™2 Duo processor
Intel® Core™ microarchitecture (Nehalem)-based processor
64
Intel® Core™ Microarchitecture (Nehalem) SMT
Implementation Details
Policy Description Intel® Core™
Microarchitecture
(Nehalem) Examples
Replicated Duplicate logic per thread Register State
Renamed RSB
Large Page ITLB
66
Inclusive vs. Exclusive Caches –
Cache Miss
Exclusive Inclusive
L3 Cache L3 Cache
67
Inclusive vs. Exclusive Caches –
Cache Miss
Exclusive Inclusive
L3 Cache L3 Cache
MISS! MISS!
68
Inclusive vs. Exclusive Caches –
Cache Miss
Exclusive Inclusive
L3 Cache L3 Cache
MISS! MISS!
69
Inclusive vs. Exclusive Caches –
Cache Hit
Exclusive Inclusive
L3 Cache L3 Cache
HIT! HIT!
70
Inclusive vs. Exclusive Caches –
Cache Hit
Inclusive
• Maintain a set of “core
valid” bits per cache line
in the L3 cache
• Each bit represents a core L3 Cache
• If the L1/L2 of a core may HIT! 0 0 0 0
contain the cache line,
then core valid bit is set to
“1”
• No snoops of cores are Core Core Core Core
needed if no bits are set
0 1 2 3
• If more than 1 bit is set,
line cannot be in Modified
state in any core
Core valid bits limit
unnecessary snoops
71
Inclusive vs. Exclusive Caches –
Read from other core
Exclusive Inclusive
L3 Cache L3 Cache
MISS! HIT! 0 0 1 0
Must check all other cores Only need to check the core
whose core valid bit is set
72
Local Memory Access
• CPU0 requests cache line X, not present in any CPU0 cache
– CPU0 requests data from its DRAM
– CPU0 snoops CPU1 to check if data is present
• Step 2:
– DRAM returns data
– CPU1 returns snoop response
• Local memory latency is the maximum latency of the two responses
• Intel® Core™ microarchitecture (Nehalem) optimized to keep key latencies
close to each other
Intel®
QPI
DRAM CPU0 CPU1 DRAM
73
Remote Memory Access
• CPU0 requests cache line X, not present in any CPU0 cache
– CPU0 requests data from CPU1
– Request sent over Intel® QuickPath Interconnect (Intel® QPI) to
CPU1
– CPU1’s IMC makes request to its DRAM
– CPU1 snoops internal caches
– Data returned to CPU0 over Intel QPI
• Remote memory latency a function of having a low latency
interconnect
Intel®
QPI DRAM
DRAM CPU0 CPU1
74
Hardware Prefetching (HWP)
75
Today’s Platform Architecture
CPU memory
CPU memory
CPU memory
76
Intel® QuickPath Interconnect
• Intel® Core™ microarchitecture
(Nehalem) introduces new Nehalem Nehalem
EP EP
Intel® QuickPath Interconnect
(Intel® QPI)
• High bandwidth, low latency
point to point interconnect
• Up to 6.4 GT/sec initially
– 6.4 GT/sec -> 12.8 GB/sec
– Bi-directional link -> 25.6 IOH
CPU CPU
GB/sec per link memory memory
77
Integrated Memory Controller (IMC)
• Memory controller optimized per
market segment
• Initial Intel® Core™
microarchitecture (Nehalem)
products
– Native DDR3 IMC
– Up to 3 channels per socket
– Nehalem
Massive memory bandwidth DDR3 Nehalem DDR3
EP EP
– Designed for low latency
– Support RDIMM and UDIMM
– RAS Features
• Future products Tylersburg
EP
– Scalability
– Vary # of memory channels
– Increase memory speeds
– Buffered and Non-Buffered solutions
– Market specific needs
– Higher memory capacity
– Integrated graphics
78
Memory Latency Comparison
• Low memory latency critical to high performance
• Design integrated memory controller for low latency
• Need to optimize both local and remote memory latency
• Intel® Core™ microarchitecture (Nehalem) delivers
– Huge reduction in local memory latency
– Even remote memory latency is fast
• Effective memory latency depends per application/OS
– Percentage of local vs. remote accesses
– Intel Core microarchitecture (Nehalem) has lower latency regardless of mix
Relative M emory Latency Comparison 1
1.00
Relative Memory Latency
0.80
0.60
0.40
0.20
0.00
Harpertow n (FSB 1600) Nehalem (DDR3-1067) Local Nehalem (DDR3-1067) Remote
1
Next generation Quad-Core Intel® Xeon® processor (Harpertown)
Intel® CoreTM microarchitecture (Nehalem)
79
Latency of Virtualization Transitions
• Microarchitectural
Round Trip Virtualization
– Huge latency reduction
1
Latency
generation over generation
100%
– Nehalem continues the
trend 80%
Relative Latency
• Architectural 60%
1
Intel® Core™ microarchitecture (formerly Merom)
45nm next generation Intel® Core™ microarchitecture (Penryn)
Intel® Core™ microarchitecture (Nehalem)
80
Extended Page Tables (EPT) Motivation
VM1 • A VMM needs to protect
Guest OS physical memory
• Multiple Guest OSs share
CR3 the same physical memory
Guest Page Table • Protections are
implemented through
Guest page table changes page-table virtualization
cause exits into the VMM
• Page table virtualization
VMM accounts for a
significant portion of
CR3 virtualization overheads
Active Page Table
• VM Exits / Entries
• The goal of EPT is to
VMM maintains the active
page table, which is used reduce these overheads
by the CPU
81
STTNI - STring & Text New Instructions
Operates on strings of bytes or words (16b)
Equal Each Instruction
True for each character in Src2 if
same position in Src1 is equal STTNI MODEL
Src1: Test\tday
Src2: tad tseT Source2 (XMM / M128) Bit 0
Mask: 01101111
Bit 0
t ad t s eT Check
each bit
in the
T xxxx xxxT diagonal
Source1 (XMM)
True if a character in Src2 is in
any character in Src1 matches
Src1: Example\n
at least one of up to 8 ranges in
Src1 t xxxxTxxx
Src2:
Mask:
atad tsT
10100000
Src1: AZ’0’9zzz \t xxxFxxxx
Src2:
Mask:
taD tseT
00100001 d xxTx xxxx
a xTxx xxxx
Equal Ordered Instruction y Fxxxxxxx
IntRes1
Finds the start of a substring (Src1)
within another string (Src2)
01101111
Src1: ABCA0XYZ
Src2: S0BACBAB
Mask: 00000010
Source1 (XMM)
Source1 (XMM)
a T FTF F F F F s xxxxxTxx
m F FFF F F F F t xxxxTxxx
p F FFF F F F F \t xxxFxxxx
l F FFF F F F F d xxTxxxxx
e F FFF F F F F a xTxxxxxx
\n F FFF F F F F y Fxxxxxxx
10100000 IntRes1 01101111 IntRes1
Source1 (XMM)
Source1 (XMM)
Source1 (XMM)
‘0’ T T T F T T T T does LE C fF fF F F T F x x
9 FFFTFFFF •AND GE/LE pairs of results A fF fF F T F x x x
z FFFFFFFF 0 fTfTfTfT x x x x
z TTTTTTTT •OR those results
X fTfTfT x x x x x
z FFFFFFFF Y fTfT x x x x x x
z TTTTTTTT Z fT x x x x x x x
00100001 IntRes1 00000010 IntRes1
83
ATA - Application Targeted Accelerators
CRC32 POPCNT
Accumulates a CRC32 value using the iSCSI polynomial POPCNT determines the number of nonzero
bits in the source.
63 32 31 0 63 10 Bit
0 1 0 ... 0 0 1 1 RAX
DST X Old CRC
0x3 RBX
63 32 31 0
DST 0 New CRC
=? 0 0 ZF
84
Tools Support of New Instructions
• Intel® Compiler 10.x supports the new instructions
– Nehalem specific compiler optimizations
– SSE4.2 supported via vectorization and intrinsics
– Inline assembly supported on both IA-32 and Intel® 64 architecture targets
– Necessary to include required header files in order to access intrinsics
• GCC* 4.3.1
– Support Intel Core microarchitecture (Merom), 45nm next generation Intel Core microarchitecture (Penryn), Intel Core
microarchitecture (Nehalem)
– via –mtune=generic.
– Support SSE4.1 and SSE4.2 through vectorizer and intrinsics
86
Example Code For strlen()
string equ [esp + 4]
STTNI Version
mov ecx,string ; ecx -> string int sttni_strlen(const char * src)
test ecx,3 je
; test if string is aligned short byte_2
on 32 bits
test eax,0ff000000h {
je short main_loop
str_misaligned: ; is it byte 3
je short byte_3 char eom_vals[32] = {1, 255, 0};
; simple byte loop until string is aligned
mov al,byte ptr [ecx] jmp short main_loop
; taken if bits 24-30 are clear and bit __asm{
add ecx,1
test al,al ; 31 is set
byte_3: mov eax, src
je short byte_3
test ecx,3 lea eax,[ecx - 1]
mov ecx,string movdqu xmm2, eom_vals
jne short str_misaligned
add eax,dword ptr 0 ; 5 byte nop tosub eax,ecx
align label below xor ecx, ecx
align 16 ; should be redundant ret
main_loop: byte_2:
topofloop:
mov eax,dword ptr [ecx] ; read 4 byteslea eax,[ecx - 2]
mov edx,7efefeffh mov ecx,string
sub eax,ecx add eax, ecx
add edx,eax
xor eax,-1 ret
byte_1: movdqu xmm1, OWORD PTR[eax]
xor eax,edx
add ecx,4 lea eax,[ecx - 3]
mov ecx,string pcmpistri xmm2, xmm1, imm8
test eax,81010100h
je short main_loop sub eax,ecx
ret jnz topofloop
; found zero byte in the loop
mov eax,[ecx - 4] byte_0:
lea eax,[ecx - 4] endofstring:
test al,al ; is it byte 0
je short byte_0 mov ecx,string
sub eax,ecx add eax, ecx
test ah,ah ; is it byte 1
je short byte_1 ret
strlen endp sub eax, src
test eax,00ff0000h ; is it byte 2 ret
end
}
Current Code: Minimum of 11 instructions; Inner loop processes 4 bytes with 8 instructions
}
STTNI Code: Minimum of 10 instructions; A single inner loop processes 16 bytes with only 4
instructions
87
CRC32 Preliminary Performance
CRC32 optimized Code
Preliminary tests involved Kernel code implementing
crc32c_sse42_optimized_version(uint32 crc, unsigned CRC algorithms commonly used by iSCSI drivers.
char const *p, size_t len)
32-bit and 64-bit versions of the Kernel under test
{ // Assuming len is a multiple of 0x10
asm("pusha"); 32-bit version processes 4 bytes of data using
asm("mov %0, %%eax" :: "m" (crc)); 1 CRC32 instruction
asm("mov %0, %%ebx" :: "m" (p)); 64-bit version processes 8 bytes of data using
asm("mov %0, %%ecx" :: "m" (len)); 1 CRC32 instruction
asm("1:");
Input strings of sizes 48 bytes and 4KB used for the
// Processing four byte at a time: Unrolled four times:
test
asm("crc32 %eax, 0x0(%ebx)");
asm("crc32 %eax, 0x4(%ebx)");
asm("crc32 %eax, 0x8(%ebx)"); 32 - bit 64 - bit
asm("crc32 %eax, 0xc(%ebx)");
Input 6.53 X 9.85 X
asm("add $0x10, %ebx")2;
Data
asm("sub $0x10, %ecx");
Size =
asm("jecxz 2f");
48 bytes
asm("jmp 1b");
asm("2:");
Input 9.3 X 18.63 X
Data
asm("mov %%eax, %0" : "=m" (crc));
Size = 4
asm("popa");
KB
return crc;
}}
89
CPU Core Power Consumption
90
CPU Core Power Consumption
91
CPU Core Power Consumption
Total Core Power
Consumption
92
C-State Support Before Intel® Core™
Microarchitecture (Nehalem)
Active Core Power
• C0: CPU active state
Local
Clocks
and Logic
Clock
Distribution
Leakage
93
C-State Support Before Intel® Core™
Microarchitecture (Nehalem)
Active Core Power
• C0: CPU active state
• C1, C2 states (early 1990s):
• Stop core pipeline Local
• Stop most core clocks Clocks
and Logic
Clock
Distribution
Leakage
94
C-State Support Before Intel® Core™
Microarchitecture (Nehalem)
Active Core Power
• C0: CPU active state
• C1, C2 states (early 1990s):
• Stop core pipeline
• Stop most core clocks
• C3 state (mid 1990s):
• Stop remaining core clocks
Clock
Distribution
Leakage
95
C-State Support Before Intel® Core™
Microarchitecture (Nehalem)
Active Core Power
• C0: CPU active state
• C1, C2 states (early 1990s):
• Stop core pipeline
• Stop most core clocks
• C3 state (mid 1990s):
• Stop remaining core clocks
• C4, C5, C6 states (mid 2000s):
• Drop core voltage, reducing leakage
Leakage
• Voltage reduction via shared VR
96
C-State Support Before Intel® Core™
Microarchitecture (Nehalem)
• Cores share a single voltage plane
– All cores must be idle before voltage reduced
– Independent VR’s per core prohibitive from cost and form
factor perspective
• Deepest C-states have relatively long exit latencies
– System / VR handshake, ramp voltage, restore state,
restart pipeline, etc.
97
Intel® Core™ Microarchitecture
(Nehalem) Core C-State Support
Active Core Power
• C0: CPU active state
Local
Clocks
and Logic
Clock
Distribution
Leakage
98
Intel® Core™ Microarchitecture
(Nehalem) Core C-State Support
Active Core Power
• C0: CPU active state
• C1 state:
• Stop core pipeline Local
Clocks
• Stop most core clocks and Logic
Clock
Distribution
Leakage
99
Intel® Core™ Microarchitecture
(Nehalem) Core C-State Support
Active Core Power
• C0: CPU active state
• C1 state:
• Stop core pipeline
• Stop most core clocks
• C3 state:
• Stop remaining core clocks
Clock
Distribution
Leakage
100
Intel® Core™ Microarchitecture
(Nehalem) Core C-State Support
Active Core Power
• C0: CPU active state
• C1 state:
• Stop core pipeline
• Stop most core clocks
• C3 state:
• Stop remaining core clocks
• C6 state:
• Processor saves architectural state
Leakage
• Turn off power gate, eliminating
leakage
101
C6 Support on Intel® Core™2 Duo Mobile
Processor (Penryn)
102
C6 Support on Intel® Core™2 Duo Mobile
Processor (Penryn)
Core 1
0
Core 0
0
Time
103
C6 Support on Intel® Core™2 Duo Mobile
Processor (Penryn)
Task completes. No
work waiting. OS
Core Power executes MWAIT(C6)
instruction.
Core 1
0
Core 0
0
Time
104
C6 Support on Intel® Core™2 Duo Mobile
Processor (Penryn)
Execution stops. Core
architectural state
Core Power saved. Core clocks
stopped. Core 0
continues execution
undisturbed.
Core 1
0
Core 0
0
Time
105
C6 Support on Intel® Core™2 Duo Mobile
Processor (Penryn)
Core Power
Core 1
0 Task completes. No
work waiting. OS
executes MWAIT(C6)
instruction. Core
enters C6.
Core 0
0
Time
106
C6 Support on Intel® Core™2 Duo Mobile
Processor (Penryn)
Core Power
Core 1
0
VR voltage
reduced.
Power drops.
Core 0
0
Time
107
C6 Support on Intel® Core™2 Duo Mobile
Processor (Penryn)
Interrupt for Core 1 arrives.
VR voltage increased. Core 1
Core Power clocks turn on, core state
restored, and core resumes
execution at instruction
following MWAIT(C6). Cores 0
remains idle. Core 1
0
Core 0
0
Time
108
C6 Support on Intel® Core™2 Duo Mobile
Processor (Penryn)
Core Power
Core 1
Interrupt for Core 0 arrives. Core
0 0 returns to C0 and resumes
execution at instruction following
MWAIT(C6). Core 1 continues
execution undisturbed.
Core 0
0
C6 significantly reducesTime
idle power consumption
109
Reducing Platform Idle Power
• Dramatic improvements in CPU idle power increase
importance of platform improvements
• Memory power:
– Memory clocks stopped between requests at low utilization
– Memory to self refresh in package C3, C6
• Link power:
– Intel® QuickPath Interconnect links to lower power states
as CPU becomes less active
– PCI Express* links on chipset have similar behavior
• Hint to VR to reduce phases during periods of low
current demand
111 111
Agenda
• Intel® Core™ microarchitecture (Nehalem)
power management overview
• Minimizing idle power consumption
• Performance when you need it
112
Turbo Mode Before Intel® Core™
Microarchitecture (Nehalem)
Clock Stopped
Power reduction in
inactive cores
No Turbo
Frequency (F)
Frequency (F)
Core 0
Core 0
Core 1
Core 1
Workload Lightly Threaded
113 113
Turbo Mode Before Intel® Core™
Microarchitecture (Nehalem)
Frequency (F)
Frequency (F)
Core 0
Core 0
Core 1
114 114
Intel® Core™ Microarchitecture
(Nehalem) Turbo Mode
Power Gating
Zero power for
inactive cores
No Turbo
Frequency (F)
Core 1
Core 0
Core 2
Core 3
Frequency (F)
Core 1
Core 2
Core 3
Core 0
115 115
Intel® Core™ Microarchitecture
(Nehalem) Turbo Mode
Frequency (F)
Core 1
Core 0
Frequency (F)
Core 1
Core 2
Core 3
Core 0
116 116
Intel® Core™ Microarchitecture
(Nehalem) Turbo Mode
Frequency (F)
Core 1
Core 0
Frequency (F)
Core 1
Core 2
Core 3
Core 0
117 117
Intel® Core™ Microarchitecture
(Nehalem) Turbo Mode
No Turbo
Frequency (F)
Core 1
Core 0
Core 2
Core 3
Frequency (F)
Core 1
Core 2
Core 3
Core 0
118 118
Intel® Core™ Microarchitecture
(Nehalem) Turbo Mode
Frequency (F)
Core 1
Core 2
Core 3
Core 0
Frequency (F)
Core 1
Core 2
Core 3
Core 0
119 119
Intel® Core™ Microarchitecture
(Nehalem) Turbo Mode
Frequency (F)
Core 1
Core 0
Core 2
Core 3
Frequency (F)
Core 0
Core 1
Core 2
Core 3
120 120
Additional Sources of
Information on This Topic:
• Other Sessions / Chalk Talks / Labs:
– TCHS001: Next Generation Intel® Core™ Microarchitecture (Nehalem) Family of
Processors: Screaming Performance, Efficient Power (8/19, 3:00 – 3:50)
– DPTS001: High End Desktop Platform Design Overview for the Next Generation
Intel® Microarchitecture (Nehalem) Processor (8/20, 2:40 – 3:30)
– NGMS001: Next Generation Intel® Microarchitecture (Nehalem) Family:
Architectural Insights and Power Management (8/19, 4:00 – 5:50)
– NGMC001: Chalk Talk: Next Generation Intel® Microarchitecture (Nehalem)
Family (8/19, 5:50 – 6:30)
– NGMS002: Tuning Your Software for the Next Generation Intel®
Microarchitecture (Nehalem) Family (8/20, 11:10 – 12:00)
– PWRS003: Power Managing the Virtual Data Center with Windows Server* 2008
/ Hyper-V and Next Generation Processor-based Intel® Servers Featuring Intel®
Dynamic Power Technology (8/19, 3:00 – 3:50)
– PWRS005: Platform Power Management Options for Intel® Next Generation
Server Processor Technology (Tylersburg-EP) (8/21, 1:40 – 2:30)
– SVRS002: Overview of the Intel® QuickPath Interconnect (8/21, 11:10 –
12:00)
121
Session Presentations - PDFs
https://intel.wingateweb.com/US08/scheduler/public.jsp
122
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