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In this section we will find that either of two gates, the NAND gate or the NOR gate can be used to implement arbitrary logic functions. We use the Positive Logic Convention (where all signals are active high) and a small circle to on a symbol to represent NOT or invert.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 2-Part 7 2
NAND Gates
S The basic positive logic NAND gate is denoted
F( X , Y , Z ) = X Y Z
function with a NOT applied. We call this symbol for a NAND gate an AND-Invert. The small circle represents the invert function. S If we apply DeMorgan's Law we get:
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
XYZ = X + Y + Z
Chapter 2-Part 7 3
F( X , Y , Z ) = X + Y + Z
OR since all inputs are inverted, followed by the OR function. S Both symbols represent the NAND gate - it is sometimes more logically descriptive to use one form over the other. S A NAND gate with one input degenerates to an inverter.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 2-Part 7 4
G( A, B, C, D ) = A B + C D
Invert. The second level is one 2-input NAND gate using Invert-OR. Using the NAND relationship, we have: G( A , B, C, D ) = AB CD = AB + CD = A B + CD Logic and Computer Design Fundamentals Chapter 2-Part 7
2001 Prentice Hall, Inc
Chapter 2-Part 7 6
S A sum-of-products (SOP) form results S To implement an equation like: F(A,B,C) = A + BC, the
Chapter 2-Part 7 7
Chapter 2-Part 7 8
NAND-NAND Example
S Implement:y F( w , x , y , z ) = y z + w x + x y + yw z
1 1 1 w 1
0 4 12 8
1 0 0 1
1 5 13 9
1 0 0 0
3 7 15 11
1 1 0 0
2 6 14 10
1 1 x w
0 4
1 0
1 5
1 0
3 7
1 1
2 6
1 12 1
8
0 13 1
9
0 15 0 11
0 14 0 10
z F(w,x,y,z)
z F (w,x,y,z)
Chapter 2-Part 7 9
and F S Select SOP form with smallest literal count S Convert selected form to NAND circuit using AND-invert (inverters for single literal AND terms) and invert-OR symbols S If SOP form for F used, add inverter to circuit output.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 2-Part 7 10
NOR Gates
The basic positive logic NOR gate (Not-OR) is denoted by the following symbol:
OR-Invert (NOR)
X Y Z
F(X, Y, Z) = X +Y+Z
This is called the OR-Invert, since it is logically an OR function followed by an invert. By DeMorgan's Law we have the following Invert-AND symbol for a NOR gate:
Invert-AND
X Y Z
Chapter 2-Part 7 11
NOR Gates
S The basic positive logic NOR gate is denoted by
F(X, Y, Z) = X +Y+Z
function with a NOT applied. We call this symbol for a NOR gate an OR-Invert. The small circle represents the invert function. S If we apply DeMorgan's Law we get:
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
X +Y +Z = X Y Z
Chapter 2-Part 7 12
F( X , Y , Z ) = X Y Z
AND since all inputs are inverted, followed by the AND function. S Both symbols represent the NOR gate - it is sometimes more logically descriptive to use one form over the other. S A NOR gate with one input degenerates to an inverter.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 2-Part 7 13
G( A, B, C, D) = (A + B) (C + D )
Invert. The second level is one 2-input NOR gate using Invert-AND. S Using the NOR relationship, we have: G( A , B, C, D) =(A+B)+(C+D) = (A+B) (C+D) = (A+B) (C+ D) Logic and Computer Design Fundamentals
2001 Prentice Hall, Inc
Chapter 2-Part 7 14
Useful Transformations
From Involution (i.e. (A')' = A) and DeMorgan's Law, we get the following useful equivalences: (AB) = ((AB)')' (A+B) = ((A+B)')' (AB)' (A'+B')' (A'B')' (A'+B')
(A+B)' (A'B') These simple transformations can be used to manipulate a two level network.
Chapter 2-Part 7 15
Graphical Transformations
The relations from the previous slide lead to the following transformations:
(A B ) = ((A B )')' (A '+ B ')' (A ' B ')' (A '+ B ') (A ' B ')
Recall that two bubbles in series can be removed from the circuit
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 2-Part 7 16
Complemented output functions (i.e. AND-NOR or ORNAND) can be handled by complementing the function. Given a function F expressed as a Karnaugh Map, we can use the same general procedures we have used before to minimize the function and express it in SOP or POS form.
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 2-Part 7 17
Chapter 2-Part 7 18
Implementation Example 1
B
1
A
1 1
C
0 0
We can remove the "Inverter" and replace it with the complement of the input variable
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 2-Part 7 19
Implementation Example 2
B
1
A
1 1
0 0
Chapter 2-Part 7 20
10
implementation into the cost picture S Attempt to combine inverters to reduce the term count S Attempt to reduce literal + term count by factoring expression into POSOP or SOPOS
Chapter 2-Part 7 21
= A A + A B + A C + B A + B B + B C = A (A + B + C) + B (A + B + C)
7 inputs and 4 gates A B C * Counting inverters (NOTS) as 1 input and 1 gate
Logic and Computer Design Fundamentals 2001 Prentice Hall, Inc
Chapter 2-Part 7 22
11
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12