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Shxrtl Vcs Single

Shxrtl Vcs Single

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Published by Ashok A
Shxrtl Vcs Single
Shxrtl Vcs Single

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Published by: Ashok A on Aug 17, 2013
Copyright:Attribution Non-commercial

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08/17/2013

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#!/bin/csh -f# VCS mixed lang simulator setenv LD_LIBRARY_PATHsetenv MG_MODEL_PATH /renesas/ba_rme/pd/ASIC_DB/APE6/toRMI_20120628_pwrnet/mobileAPE6/VNET1/release/120621_eco12/simmodel/custommodelsetenv DIR_armBST /renesas/ba_rme/pd/ASIC_DB/APE6/toRMI_20120628_pwrnet/mobileAPE6/VNET1/release/120621_eco12/simmodel/custommodel/armBST_64 setenv PROJ_SIMM_TB /renesas/ba_rme/pd/ASIC_DB/APE6/toRMI_20120628_pwrnet/mobileAPE6/VNET1/release/120621_eco12/sim/testbench setenv MG_LIB /renesas/ba_rme/pd/ASIC_DB/APE6/toRMI_20120628_pwrnet/mobileAPE6/VNET1/release/120621_eco12/simmodel/custommodel/armBST_64/ModelManager/Linux_64/MMsetenv LD_LIBRARY_PATH /renesas/ba_rme/pd/ASIC_DB/EOS2_ES2/RTL/RENESAS_PLI/TCHK/vcsmx/linux64:$LD_LIBRARY_PATHsetenv LD_LIBRARY_PATH ${MG_LIB}/synopsys_vcs_verilog:$LD_LIBRARY_PATH rm -rf worklibmkdir worklib vlogan \-work worklib \+v2k \-f ./vlgfile.list \-f ./libfile.list \+incdir+/renesas/ba_rme/pd/ASIC_DB/APE6/toRMI_20120628_pwrnet/mobileAPE6/VNET1/release/120621_eco12/sim/testbench/include \+incdir+/renesas/ba_rme/pd/ASIC_DB/APE6/toRMI_20120628_pwrnet/mobileAPE6/VNET1/release/120621_eco12/inc_board \+incdir+/renesas/apps/synthesis/2007.12-SP2/dw/sim_ver \+incdir+/renesas/ba_rme/pd/ASIC_DB/APE6/toRMI_20120628_pwrnet/mobileAPE6/VNET1/release/120621_eco12/pwr \+incdir+/renesas/ba_rme/pd/ASIC_DB/APE6/DOWNLOADS/To_Bangalore/19Jul12/0x11D0001B_0x21D0001B_APE6_eco12_PwrInsNet/inc_force \+incdir+/renesas/ba_rme/pd/ASIC_DB/APE6/toRMI_20120628_pwrnet/mobileAPE6/VNET1/release/120621_eco12/inc_force \+incdir+/renesas/ba_rme/pd/ASIC_DB/APE6/toRMI_20120628_pwrnet/Cell_Library/custom/AT28MUS20000_120525/verilog/pg \+define+romcodedir=\"/renesas/ba_rme/pd/ASIC_DB/APE6/toRMI_20120628_pwrnet/mobileAPE6/VNET1/release/120621_eco12/rom_code\" \+delay_mode_distributed \+define+freq_check_off \+notimingcheck \-timescale=1ns/1ps \-debug_all \+define+VCS_SIM \+define+CPGM_DELAY=1000 \+define+EMEM_DISABLE_ERRMES \+define+EXTAL_WIDTH=38.462 \+define+EXTAL2_WIDTH=19.2 \+define+CLOCKHALFCYC=14.44 \-full64 \-sverilog \+define+GATE +define+FORCE \-l vlogan.log rm -rf simv* csrcvcs worklib.shxsim \

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