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Table Of Contents

Revision History
Design Strategies
Large FPGA Devices
SSI Technology
Routing Utilization
Design Performance
Power Consumption
Project Costs
Stacked Silicon Interconnect (SSI)
SSI Components
•Super Logic Region (SLR)
Super Logic Region (SLR)
SLR Components
•xc7v2000t Devices
•xc7vx1140t and Virtex-7 HT Device Family
xc7v2000t Devices
xc7vx1140t and Virtex-7 HT Device Family
Silicon Interposer
Super Long Line (SLL) Routes
Master Super Logic Region (SLR)
Clocking
•Regional Clocking
Global Clocking (BUFG)
Management of Design Placement in SLR Components
Automatic SLR Assignment
Placement Strategies
Manual SLR Assignment
SSI Configuration
•Pinout Selection
Pinout Selection
•Consequences of Pinout Selection
Consequences of Pinout Selection
Using Xilinx Tools in Pinout Selection
General Pinout Selection Recommendations
Specific Pinout Selection Recommendations
Interface Control Signals
Very High Fanout, Design-Wide Control Signals
Xilinx IP Containing I/O Interfaces
CCIO and CMT Usage
Components Located in a Particular SLR (SSI)
Device Migration
Control Sets
•About Control Sets
About Control Sets
Resets
About Resets
When and Where to Use Resets
Defining an Initial State on Inferred Synchronous Elements
Synchronous and Asynchronous Resets
Active-High and Active-Low Resets
HDL Coding Styles
•Register the Outputs of Data Paths
•Place Clocking Elements Toward the Top Level
•Infer I/O Components
Register the Outputs of Data Paths
Place Clocking Elements Toward the Top Level
Infer I/O Components
•Use BUFG and BUFH
•Manage Replication in the Tools
Reduce Loads
Use BUFG and BUFH
Manage Replication in the Tools
Manage replication in the tools
Selecting Clocking Resources
Global Clocking
BUFGCE
BUFGMUX
BUFGCTRL
IP and Synthesis
Regional Clocking
•Horizontal Clock Region Buffers (BUFH, BUFHCE)
Horizontal Clock Region Buffers (BUFH, BUFHCE)
Horizontal clock region buffers (BUFH, BUFHCE) can be used:
Regional Clock Buffers (BUFR)
I/O Clock Buffers (BUFIO)
Multi-Regional Clock Buffers (BUFMR)
Clocking for SSI Devices
Clock Skew in SSI Devices
Inference
Synthesis Attributes
Intellectual Property (IP)
•Clocking Wizard and I/O Wizard
Clocking Wizard and I/O Wizard
Complex IP
Instantiation
•Benefits of Instantiation
•Instantiating Clocking Resources at the Top
•Dangers of Redundant Clocking Resources
Benefits of Instantiation
Instantiating Clocking Resources at the Top
Dangers of Redundant Clocking Resources
Controlling Clock Phase, Frequency, Duty Cycle, and Jitter
•Using Clock Modifying Blocks
Using Clock Modifying Blocks
Using IDELAY to Control Phase
Using Gated Clocks
Reducing Dynamic Power
Output Clocks
Clock Domain Crossings
Using Clock Buffers for Non-Clock Nets
•Design Performance
•Using More Than Two BUFG Components or BUFH Components for Non-Clock
Signals
Using More Than Two BUFG Components or BUFH Components for Non-Clock Signals
Using BUFG Components for Mixed Polarity Signals
Using Enables Effectively
Buffer Selection
Specifying Buffer Placement
Clock Resource Selection Summary
•BUFGMUX and BUFGCTRL
BUFG
BUFGMUX and BUFGCTRL
BUFH
BUFHCE
BUFR
BUFIO
BUFMR
BUFMRCE
MMCM
IDELAY and IODELAY
ODDR
AppendixA
Additional Resources
Xilinx Resources
Hardware Documentation
ISE Documentation
Partial Reconfiguration Documentation
PlanAhead Documentation
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Published by Sorabh Dung
Xilinx FPGA
Xilinx FPGA

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Published by: Sorabh Dung on Aug 21, 2013
Copyright:Attribution Non-commercial

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