Report on the workshop High Performance Signal Processing Organised by European Commission DG INFSO Unit E5: Peripherals, Sub-systems

and Microsystems

Date: Venue:

15 May 2000 European Commission, Avenue de Beaulieu 5 room B

Rapporteur: Cornelis Bruin

Workshop High Performance Signal Processing 15 May 2000

Table of contents

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1.1 1.2 1.3

INTRODUCTION
Introduction to ISTAG Profile of the workshop participants and presenters Topics covered by the Workshop

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3 3 4

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2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11

PRESENTATIONS BY THE PARTICIPANTS

Mr. Benedetto Altieri, Director of Industrial Alliances for Advanced Products, ATMEL Mr. Tim Caspell, Collaborative Projects Consultant, ARM Mr. Pavel Karmazin, Definition Line Card Controllers, Infineon Technologies Guido Magazzu, INFN, Italian nuclear physics institute. Mr. Pier Stanislao Paolucci, Nergal Roma Professor Francis Castanie, Director, ENSEEIHT-TSA Dr. Conor Heneghan, College Lecturer, University College Dublin Prof. Ivars Bilinskis, Professor, Institute of Electronics - University of Latvia

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5 5 6 6 6 7 7 7

Mr. Bernard Candaele, Manager Custom IC Competence Centre, Thomson-CSF Communications 8 Prof. Joos Vandewalle, Katholieke Universiteit van Leuven Mr. Bjrn Olav Bakka, Research Manager, Sintef Electronics and Cybernetics 8 9

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3.1

DISCUSSION COMMENTS
Conclusions

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11

LIST OF PARTICIPANTS

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Workshop High Performance Signal Processing 15 May 2000

Introduction

Unit E5 organised a workshop on the 15th of May 2000 with the aim of taking stock of the current thinking within Europe about High Performance Signal Processing and to identify the challenges within the medium term. The outcome of the workshop will be used as a strategic vision for further developments in the Signal Processing domain. The outcome of the workshop will be aligned with the vision of the IST Advisory Group (ISTAG) and will be used as input to the yearly process of aligning the IST workprogramme with the technological developments and the market evolution. The European Commission is using a yearly process of workshops with active industry participation as an input mechanism to the work of the ISTAG and the IST Committee (ISTC) who determine together with the European Commission the evolving workprogramme during Framework V. 1.1 Introduction to ISTAG

The role of the IST Advisory Group (ISTAG) is to provide the Commission with independent advice concerning the content and direction of research work to be carried out under the IST Programme. This involves proposing guidelines for the detailed work programmes, including the timetable of calls for proposals, the criteria to be used for evaluating project proposals, and verifiable objectives for achieving the aims of the key actions. The groups will also comment on the strategic nature and exploitation of the work to be carried out and on the analysis of results, with a view to a possible revision or reorientation of the work programmes. The vision statement agreed by ISTAG members is to . "Start creating an ambient intelligence landscape for seamless delivery of services and applications in Europe (relying also upon testbeds and open source software), develop user-friendliness, and develop and converge the networking infrastructure in Europe to world-class" The vision for Ambient Intelligence arises from the convergence of three key technologies: "Ubiquitous Computing", "Ubiquitous Communication", and "Intelligent user-friendly Interfaces". It proposes a laid-back mode of dialogue with an integrated service infrastructure in which one s everyday surroundings become the Interface. This vision builds on European strengths in mobile communication, digital broadcasting, rich content and network infrastructures to provide a new impetus for rapid and complete convergence of fixed and mobile applications as well as synergies between broadcast and on-line services. It necessitates the resolution of many formidable technical and standardisation problems, relying on a continuing, rapid advance in key technologies and their aggregation and materialisation as competitive products and services. This should catalyse an expanse of business opportunities that capitalise on the growing appetite for added-value services packaged in ever more user-friendly formats. 1.2 Profile of the workshop participants and presenters

21 persons of whom 11 persons gave a presentation during the workshop attended the workshop. As can be seen in the list of attendees at page 13 the participants and presenters were representative for a large cross-section of industry and the scientific community. They were from large enterprises, SMEs, IP providers, semiconductor manufacturing, systems integration, universities, research institutes and industrial associations.

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Workshop High Performance Signal Processing 15 May 2000 1.3 Topics covered by the Workshop

The scope of high performance signal processing is very large and the workshop topics were focused by the ISTAG vision, current Workprogramme 2000 activities and the Key Actions therein. The workshop covered real-time and quasi-real-time signal processing applications. Quasi real-time here means applications with a response within a few seconds, as opposed to offline or batch processing. There are many synergies between technological areas covered in the key actions and actions lines that would benefit from the added value of a focused signal processing initiative. The application areas under consideration would include medical imaging, multimedia applications such as music, images and video, speech analysis and synthesis, mobile & wireless communications and landbased and satellite-based navigation applications. The workshop focused on Algorithms, Devices, Tools & Methodologies and Software. A number of industry representatives outlined in presentations how they perceived the status and the challenges in the High Performance Signal Processing domain and how they felt that this initiative could benefit the European industry. The workshop was attended by several well regarded experts in this technology domain as can be seen in the list of attendees on page 13 of this report. Mr Javid Khan is the scientific officer from unit E5 who organised the workshop and opened the meeting by outlining the objectives, the agenda and strategy. After a short introduction to the IST workprogramme 2000 and the process of alignment of the workprogramme for the coming years, the industry participants were given the opportunity to explain their viewpoints.

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Workshop High Performance Signal Processing 15 May 2000

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2.1

Presentations by the participants

Mr. Benedetto Altieri, Director of Industrial Alliances for Advanced Products, ATMEL

Atmel a company of 7000 employees with over 50 % of its employees in Europe has been a producer of microelectronics solutions for several years and has been involved in many of the technologies that are important to signal processing. Mr. Altieri explained the trend of Global Markets, Global Organisations and Global Solutions (3G) demanding new and versatile solutions to application challenges. He outlined the "Computer Architecture for Signal Processing" (CASP), a modular technology of tools that are configurable to support different hardware and application environments. The markets addressed are G3 UMTS, modelling of musical instruments and sound generation, biomedical and ultrasound applications, echography and "Digital Radio Mondiale (DRM). From work that took place in the ESPRIT project Magic-FPU it was determined that FPU cores and SIMD engines are mandatory for high performance multimedia applications. Technologies such as C-simulators, co-design with transfer of C-blocks to VHDL and Verilog, high performance chips at low power utilisation, increasing parallelism and VLIW approaches, cycle accurate simulation, multi-MAC and multiport register files are urgent requirements. Megaoperations (MOPS) per watt are an increasingly important factor. The speaker also pleaded for the opening up of IP blocks in making it available as IP cores as well as making algorithms more openly available ("whitebox" versus "blackbox" approach). 2.2 Mr. Tim Caspell, Collaborative Projects Consultant, ARM

Advanced Risc Machines (ARM) is a leading European IP supplier of processor cores and has established a pre-eminent position within embedded applications. Companies such as Toshiba, Nokia, Alcatel, Ericsson, Samsung and many others have licensed IP cores for design into their products. The DSP is gaining momentum with a worldwide shipment volume of DSP components reaching 5 billion $ in 2001. We are increasingly living in a DSP world through signal-processing-based applications that are ubiquitous through mobile and fixed communication and different kinds of multimedia applications. This has resulted in a multitude of standards (MPEG 2 and 4, MP3, H.261, H263 ..), de-facto standards ( .wav, .bmp, .. ) and proprietary standards (RealAudio, Sony audio format ..). Each of these is evolving over time and new ones are being added regularly. This leads to a requirement for DSP products to be either highly adaptable or increasingly software-based to be able to adapt to the evolving environment. ARM has moved its products to integrated development environments including microprocessor and DSP instruction sets. Mr. Caspell suggested that we should research compiler techniques such as executable specifications, total systems construction from high level language and techniques from the supercomputer world to meet the increasingly DSP/CPU performance demands. VLIW, Multi-CPU, SIMD and superscalar architectures are increasingly becoming part of the computing landscape.

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Workshop High Performance Signal Processing 15 May 2000 2.3 Mr. Pavel Karmazin, Definition Line Card Controllers, Infineon Technologies

Infineon Technologies is one of the leading European Semiconductor producers and was founded when Siemens spun of its Siemens Semiconductor division in April of 1999. Last year's revenue amounted to 4.3 billion Euro at a growth rate of 33 %. Infineon is the world's 8th largest semiconductor manufacturer with 10 manufacturing sites and 16 R&D sites world-wide. Mr. Karmazin represented the Communications Division within Infineon that concentrating on the production of communication line cards, XDSL, PCM, ATM etc. In this market segment there is a strong requirement for RISC / DSP processing at high performance levels that can handle highspeed conversion between PCM, XDSL and ATM with high numbers of communication lines. G711 compression and "Voice over IP" (VoIP) are promising upcoming applications. Infineon has developed the CARMEL family of open DSP cores featuring multi-core debugging, on-chip emulation and superscalar processing using two 24-bit instructions in parallel. Up to 6 instructions are executed per cycle with the "Dynamicaly Configurable Long Instruction Word" (CLIW), a technology that uses memory more efficiently than VLIW. Carmel is based on 0.13 micron technology. Mr. Karmazin believes that future telecom applications should be based upon open DSP architectures. 2.4 Guido Magazzu, INFN, Italian nuclear physics institute.

Mr. Magazzu represents the Italian Nuclear physics institute (INFN) that has been involved in a number of high performance computing initiatives such as APE, AP100, APEmille and APENext. All of those initiatives were aimed at massive parallel computing in order to achieve the compute performance that is required to process the high volumes of data as they are collected in nuclear physics experiments. The APENext initiative is expected to reach, as it goes from 0.25 to 0.18 micron technology, a performance level of 3.2 Gflops at 200 MHz. The design approach in the initiative is focused on HDL modelling, standard cells and HDL blocks turned into IP cores. Multiport register files are central to the high performance DSP architecture. Mr. Magazzu pleaded for continued attention to high performance computing initiatives and emphasised the synergy/technology transfer with DSP. 2.5 Mr. Pier Stanislao Paolucci, Nergal Roma

Nergal Roma is a small company that was founded as a spin-off from INFN, the Italian nuclear physics institute. Mr. Paolucci explained that in his opinion the DSP technology for "Systems on a Chip" (SOC) would require VLIW cores and that the competition for VLIW - SIMD based product is growing rapidly. The successful development of this technology will require advanced co-design methodology that has made much progress but still has a long way to go. Within the context of the project MAGIC-FPU the consortium of IRIS-Bontempi, Thomson-CSF, Nergal and Atmel created the MAGIC Core (a general-purpose architecture description language) and MADE (a modular VLIW architecture description environment). The project developed methodologies for the creation of modular VLIW cores for the implementation of DSP technology. Applications that will benefit from this technology are beam forming antennas, music and sound

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Workshop High Performance Signal Processing 15 May 2000 synthesis based on physical modelling such as singing from MIDI scores and game sound synchronisation, digital AM chip sets, sonar and seismic and UMTS base stations and terminals. 2.6 Professor Francis Castanie, Director, ENSEEIHT-TSA

TSA concentrates on telecommunications for Space and Aeronautics and Professor Castanie explained the work being done in Neural Network technologies. The main problems being faced in satellite communications is the time-varying and non-linear distortion taking place at the same time. Many equalisation and optimisation techniques are being used but many problems still remain. The presentation showed how Neural Networks could be used to try to solve those problems by putting those networks in the satellite and model the environment to get as close as possible to the situation of the signal at the ground. The Neural Networks would have a learning ability to adapt to other satellites automatically. In order to be successful the solution would have to reach a high performance level in order to cope with satellite communication that is not possible today but could be brought in reach through technological developments. The state of art of conventional DSP technology provides a 100 kb/s performance, with FPGA 400 kb/s is possible and the hybrid digital / analogue technology discussed would bring 40 to 100 Mb/s within reach. As the Neural Network technology offers opportunity for an adaptive solution with a simple architecture, a better fit to experimental data, a unified architecture and a parallel implementation it should receive attention of the RTD programmes. 2.7 Dr. Conor Heneghan, College Lecturer, University College Dublin

The DSP research group of the University College of Dublin consists of 16 researchers and does mostly algorithmic work. Its funding is derived for 50 % from private industry and for 50 % from national and European initiatives. The group is involved with DSP components for software radio, multi-channel and multi-user crosstalk limited communications, low power DSP, pattern recognition, signal adaptive compression and quasi real-time image analysis. The group does research in adaptive wavelet compression and even thought the theory of adaptive wavelet compression is not complete it promises through the lifting scheme an interesting technological path. Themes for the future addressed by Dr. Heneghan were the following: more emphasis on core engineering, IPR and soft hardware concepts provide many opportunities to European industry, commercial success needs to be as much in tools as in chips. Europe needs to provide the correct legal and financial framework for IP reuse. European research programmes should encourage schemes for researchers to spend time in private industry. Specific suggestions made for future focus were the following: better power optimisation tools, better pre-processors and improved tools for architecture trade-offs. 2.8 Prof. Ivars Bilinskis, Professor, Institute of Electronics - University of Latvia

Mr. Bilinskis explained the technology of alias-free signal processing to cope the acquisition of signals where the line frequency is so high that the performance of current solutions is not sufficient for the fixed rate sampling algorithms popular today. Because of equidistant sampling today, various signal-frequencies can be represented by the same samples and pre-knowledge of the signals to be sampled is desired by the designers.

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Workshop High Performance Signal Processing 15 May 2000 With non-uniform sampling much higher signal frequencies can be handled as fewer samples can lead to accurate reconstruction of the original signal. A draw back of the approach is that classical approaches such as FFT and filtering do not work anymore, special algorithms and more computing are required and more storage per sample is required. Research work on this technology of Alias-free processing is done at the University of Latvia and Mr. Bilinskis believes that the technology deserves wider initiatives. An application such as GSM demodulation with the possibility of direct conversion from the RF to the digital domain might benefit enormously from a breakthrough of this technology. 2.9 Mr. Bernard Candaele, Manager Custom IC Competence Centre, Thomson-CSF Communications

Mr. Candaele presented several aspects of signal processing for the telecommunication industry. Significant applications where Thomson-CSF Communications is active are Cryptography, JPEG encoding, software radio, wireless high rate modem, voice over IP (VOIP) and PABX. The trends in cryptography show that the public keys in RSA and DSA are moving from 2048 to 4096 bits, while ECDSA is moving from 200 to 512 and later to 1024 bits. Europe needs to keep its know-how in security and performance in the devices. The NIST initiative is developing the "advanced encryption standards" (AES) as a follow-on to "digital encryption standard" (DES). European standards are promoted in the project NESSIE. In terms of devices, methodologies of formal proof of security and common criteria for qualification of devices for security are required. Real time encryption in smart cards for high datarate video and configurable algorithms with smart cards devices are needed. In conclusion Mr. Candaele stressed security requirements for IT applications as well as the fact that multimedia applications for increasingly mobile applications will require new DSP algorithms, new tools and new devices. 2.10 Prof. Joos Vandewalle, Katholieke Universiteit van Leuven The University of Leuven has a large group of about 80 researchers involved with signal processing. Mr. Vandewalle indicated that the group focuses its attention on linear algebra, multilinear algebra, high order statistics, adaptive filtering and coding theory as well as cryptography. Mr. Vandewalle gave an overview of the "European Association for speech and image processing" (EURASIP). This association was founded in 1978 and promotes technology development and uptake. The work of this association takes place in the form of journals, conferences, newsletters, training courses and participation in several committees. The association co-operates as well actively with the "European Speech Communication Association" (ESCA). A better dissemination of the digital signal processing methods and more intense contacts with the scientific community on signal processing in Europe and its organisation EURASIP could be beneficial. Mr. Vandewalle suggested that emphasis should be given to the development of advanced algorithms that are a number of years ahead of the IC technology in order to have the algorithms available when the IC technology is ready. Critical issues in ICT algorithms are speed, capacity, accuracy, quality, security, large data sets, user-friendliness, reliability and robustness. Critical cryptographic algorithms are needed for high-speed communication as well as biomedical algorithms for images, sounds, and measurement. The push for pragmatic work and demonstrators should not distract the attention from the real algorithmic high performance signal processing work. -8-

Workshop High Performance Signal Processing 15 May 2000 A breakthrough at the algorithmic level would have more strategic impact than technology demonstrators. 2.11 Mr. Bjrn Olav Bakka, Research Manager, Sintef Electronics and Cybernetics Mr. Bakka presented the large opportunities that are created by mobile and wireless applications and its requirements for intelligent and flexible devices. The technologies that are needed in those domains are sensors and actuators, embedded hardware and software, implementation of communications standards such as bluetooth, application software and new signal processing technologies.

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Workshop High Performance Signal Processing 15 May 2000

Discussion comments

The environment of standards, de-facto standards and proprietary standards requires soft or highly adaptive solutions and not final hardware implementations. An important issue is the challenge of how to mix MCU and DSP technology in devices as in applications some elements are better served with DSP processing, others with RISC or CISC processing. The industry needs simple architectures to facilitate the adaptation to applications. A VLIW architecture is emerging for the U.S.A (TRANSMETTA) that might not cater as well for low power and low footprint devices as suggested. Alternative architectures are needed. The group suggested energy to be put in reconfigurable tools to be able to adapt to different application environments. There is currently a multitude of memory and computing islands in implementations. The VLIW architectures are nice but provide only instruction level parallelism. The parallelism needs to go much further and include data flow and inter processor flow. Compile approaches need to be developed in line with those system features. Because of the many standards, applications need to go to sophisticated software solutions. Encode once and decode everywhere approaches have potentially wide applicability as in for example JPEG and MPEG. Co-design needs a high level of attention. Most solutions seem today to focus on C and C++. Those languages give the level of abstraction to decide later where to go in hardware and where to go in software. Several current implementations being worked on such as the one by the University of Leuven show that one can go automatically from C or C++ to VHDL or Verilog. Power optimisation should receive much attention with R&D in compiler technology that optimises for minimising overall power use and peak power within tight constraints. An object oriented approach should be encouraged in the design tools and the design practices to maximise the design reuse potential. It seems that the issue of floating versus integer is losing weight as much of the applications can now be done in saturated integer arithmetic. Research work in ADC and DAC technologies is important as signal-processing applications interact most of the time with the real world through those technologies. Technologies for tools aimed at mixed designs are still lacking. Integration between analogue and digital designs is often a management issue as the skills of the designers are very distinct. The surge in mobile communication and the analogue requirements in signal processing make this a very important issue. Speech coding and "Voice over IP" (VoIP) came up in the presentations, however, limited attention was given in the presentations to the requirements audio, although music generation and speech compression for communications were discussed. It was emphasised that the area of music and sound analysis and synthesis are quite important and should receive wide attention. DSP knowledge is still thinly spread and initiatives could help to put attention to the importance of this knowledge. DSP coding is still mostly assembly level coding and tools, technology and methodology for higher level coding approaches are desirable.

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Workshop High Performance Signal Processing 15 May 2000 Signal processing is not a niche anymore; it is becoming part of a larger percentage of embedded as well as desktop applications. Open approaches were mentioned a few times and the opening up of IP by making VHDL blocks available as IP cores as well as the opening of algorithms ("whitebox" versus "blackbox" approach) were deemed desirable. The interchange of knowledge between DSP centres such as the initiative of "DSP Valley" in Belgium is felt important and could be complemented by co-ordination from a European level. 3.1 Conclusions

Application focus is important as it goes hand in hand with the signal processing technology. The applications mentioned were:
q q q q q q q q

biomedical imaging (ultrasound echography, pattern recognition and image analysis) Digital Radio Mondiale (DRM), UMTS base stations, software radio Alternative direct frequency conversion from RF signals satellite transmission signal processing (based on Neural Networks) conversion between PCM, XDSL and ATM for telecommunications within central switches Voice over IP (VoIP) multimedia sound analysis and synthesis including physical modelling security and cryptography

New open algorithms in areas like codec design, RF to digital signal conversion and video, audio or still image compression could be important stimulants to many of the applications mentioned. Devices that cater for parallel processing at low power levels were mentioned several times. As can be seen in the presentations VLIW and CLIW techniques are indicated and the requirements for tighter integration with the development tools. VHDL blocks and IP cores play an increasingly important role in chip design and both the issue of VHDL block to IP core conversion as well as technical and legal infrastructure issues with design and reuse were raised. This is an area where initiatives could play an important role. Tools technology and availability was raised as an important issue. Object orientation, reuse, design for low power, configurable tools and open IP were mentioned as keywords. In terms of compile technology it was suggested that many of the techniques common in supercomputing should enter this area as much of the technology is heavily compute centred. RTOS developments that are clearly focused on the unique nature of signal processing design are necessary for efficient application design. This area could benefit from further initiatives. Different people often perform analogue and digital design, as the skills of the designers are very distinct. The surge in mobile communication and the analog requirements in signal processing make the integration between the two areas more pressing. It was pinpointed in the discussions that signal processing is a knowledge that is not well spread and initiatives that provide training, sharing of know-how and co-operation between institutes and enterprises could be extremely beneficial to the technology. The DSP-Valley initiative in Belgium is a good example. Other long-term initiatives such as a (virtual) European institute for signal processing may be considered.

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Workshop High Performance Signal Processing 15 May 2000 The issue of standards, de-facto standards, proprietary standards and its evolving nature was discussed several times. A common theme seems to be the fact that initiatives for open software solutions connected to standards that have a high degree of adaptability are desirable.

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Workshop High Performance Signal Processing 15 May 2000

List of Participants
Cornelis Bruin Managing Director Bruin Consulting Tel: +32-2-4608165 Fax: +32-2-4608165 cornelis.bruin@ping.be Bernard Candaele Thomson-CSF Communications, France Manager Custom IC Competence Centre Tel: +33-1-46132650 Fax: +33-1-46132766 bernard.candaele@tcc.thomson-csf.com Tim Caspell ARM, United Kingdom Collaborative Projects Consultant Tel: +44-1223-400761 Fax: +44-7092-265686 tim.caspell@arm.com Francis Castani ENSEEIHT - TSA, France Director Tel: +33-5-61588296 Fax: +33-5-61588296 francis.castanie@tesa.prd.fr Johan David Philips, Belgium Senior Project Engineer Tel: +32-16-390742 Fax: +32-16-390600 belvjda@beccmail.snads.philips.nl Ralph Dum European Commission Scientific Officer Tel: +32-2-2996434 ralph.dum@cec.eu.int

Benedetto Altieri Atmel, Italy Director of Industrial Alliances Tel: +39-02-38008275 Fax: +39-02-38037234 baltieri@es2.fr Michael Arentoft European Commission Scientific Officer Tel: +32-2-2963886 Fax: +32-2-2961692 michael.arentoft@cec.eu.int Bjrn Olav Bakka Sintef Electronics and Cybernetics, Norway Research Manager Tel: +47-22-067300 Fax: +47-22-067350 bjornOlav.bakka@ecy.sintef.no Dirk Beernaert European Commission Head of Unit Tel: +32-2-2968020 Fax: +32-2-2968389 dirk.beernaert@cec.eu.int Ivar Bilinskis Institute of Electronics and Computer Science University of Riga, Latvia Tel: +371-7554500 Fax: +371-7555337 bilinsk@edi.lv Ivo Bolsens imec, Belgium Vice President VLSI Systems and Design Methods Tel: +32-16-281244 Fax: +32-16-281515 bolsens@imec.be David Broster European Commission Cross Programme Themes Tel: +32-2-2968021 david.broster@cec.eu.int

Conor Heneghan University College Dublin, Ireland College Lecturer Tel: +353-1-7061925 Fax: +353-1-2830921 conor.heneghan@ucd.ie - 13 -

Workshop High Performance Signal Processing 15 May 2000 Francisco J.Ibaez European Commission Scientific Officer Tel: +32-2-2968659 Fax: +32-2-2968389 francisco.ibanez@cec.eu.int Pavel Karmazin Infineon Technologies, Germany Definition Line Card Controllers Tel: +49-89-23423877 Fax: +49-89-23422020 pavel.karmazin@infineon.com Javid Khan European Commission Scientific Officer Tel: +32-2-2995799 Fax: +32-2-2968387 javid.khan@cec.eu.int Alkis Konstantellos European Commission Scientific Officer Tel: +32-2-2957153 alkis.konstantellos@cec.eu.in

Guido Magazzu INFN-Sezione Di Pisa, Italy Tel: +39-050-880325 Fax: +39-050-880317 guido.magazzu@pi.infn.it

Pier Stanislao Paolucci Nergal, Italy Tel: +39-06-40801173 Fax: +39-06-40801283 paolucci@nergal.it

Joos Vandewalle Katholieke Universiteit Leuven, Belgium Professor, Representative EURASIP Tel: +32-16-321130 joos.vandewalle@esat.kuleuven.ac.be

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