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Table Of Contents

Verilog HDL -History
How Verilog Is Used
Levels of Abstraction
Levels of Abstraction (Cont..)
Design Methodologies
Modules (Contd..)
Design Hierarchy
Structure of module
Structure of module (Contd..)
Lexical Conventions
Verilog Comments
Verilog Number Specifications
Verilog Numbers: Example
Data Types
Logical Operators
Logical Operation Example
Bitwise Operators
Reduction operators Reduction operators
Reduction operation Reduction operation
Shift operators
Conditional Operator
Concatenation Operator
Relational & EqualityOperators
Operator precedence
Arrays (Contd..)
Port assignments
Module Instantiations
Hierarchical Naming (Contd..)
Gate Level Modeling
Gate Level Modeling (Contd..)
Gate Delays
Gate Level Modeling Examples
Gate Level Modeling Examples (Contd..)
Dataflow Modeling
Dataflow Modeling (Cont..)
Dataflow Modeling Examples
Dataflow Modeling Examples (Contd..)
Behavioral Modeling
Procedural Blocks
Procedural Assignment
Blocking Assignments
Blocking Assignments (Contd..)
Blocking Assignments Example
Non-blocking Assignments
Non-blocking Assignments (Contd..)
Non-blocking Looks Like Latches
Looping Flow Control
Task and Function
Difference between task and function
System Tasks
Compiler Directives
System Tasks & Compiler Directives Example
Synchronization -Event
Synchronization (Contd..)
Synchronization –fork and join
Synchronization –disable
Forever Statement
Generate Statements
Generate Statements (Contd..)
Race conditions in Verilog
Race Conditions & their Solutions
Flip-Flop Race Condition
User Defined Primitives
User Defined Primitives (Contd..)
Rules to Define UDP
Sequential UDP -Examples
FSM Classification
FSM Classification FSM Classification
FSM encoding
Modeling Mealy FSM Modeling Mealy FSM
Modeling Moore FSM Modeling Moore FSM
RTL Synthesis
Why is RTL synthesis important?
Synthesis Process
Technology Library
Only Put Latches If Necessary
Procedural synthesis
Latch Inference
CDFG format
Gate Level Optimization
After gate level optimization
Verilog "stratified event queue"
Signal Types
Signal Types(cont)
Signals (cont)
Signal Strength (cont)
Verilog Syntax for Strength
Support for transmission gate
Timing Delay in ASIC library
Timing Delay in Gate
Timing Delay Calculation
Timing Delay -SDF Back-Annotation
Macro Cont
Conditional Compilation
Good Naming Convention
File Output
Test bench
Test bench –timing control
Waveform Probing using VCD
Interactive Debugging
Simulation Tips 1
Simulation Tips 2
Simulation Tips 3
Where PLI is Used
Simulation Flow Using PLI routines
Generations of Verilog PLI
Uses Of PLI
Uses Of PLI (Contd..)
Linking and Invocation of PLI Tasks
Verilog Strengths and Weaknesses
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Published by: Ujjwal Kant on Sep 03, 2013
Copyright:Attribution Non-commercial


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