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Overview of MIPS ISA

Overview of MIPS ISA

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Published by BravoYusuf
MIPS is an acronym for Microprocessor without Interlock Pipeline Stages.
You can view Instruction Formats of MIPS in this article.

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MIPS is an acronym for Microprocessor without Interlock Pipeline Stages.
You can view Instruction Formats of MIPS in this article.

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Thank you.

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Published by: BravoYusuf on Jun 17, 2009
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12/23/2012

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CS-421 Parallel Processing BE (CIS) Batch 2004-05Handout_4
Page - 1 - of 3
Overview of MIPS ISA
MIPS is acronym for 
M
icroprocessor without
I
nterlock 
P
ipeline
S
tages. MIPS is very popular microprocessor inembedded devices. Salient features of its ISA are described below:
 
All instructions are 32-bit wide (fixed-length instructions)
o
 
Fixed-length instructions are easy to decode (simple decoding logic and hence fast decoding) asopposed to variable-length instructions
o
 
With fixed-length instructions, it’s easy to generate address of next instruction to be fetched. (addressof next instruction = PC + instruction-length)
o
 
The downside of fixed-length is poor storage economy as opposed to variable-length instructions thatuse as much storage as required.
 
MIPS is a
byte-addressable
machine that means every byte has a unique address.
 
Address are 32-byte wide
 
There are 32 general-purpose registers each of size 32-bit
 
These features are examples of a design principle:
simplicity favors regularity
. Simple designs are usuallyfast and easy to debug and improve.
Instruction Formats
An instruction format is a breakup of instruction into different fields, each field being reserved for a specific purpose. MIPS has
three instruction formats
(
the lesser the number of instruction formats, the simpler the ISAwill be
)
1.
R (Register) Format
This divides the instruction into six fields as follows:6 5 5 5 5 6
op rs rt rd shamt funct
Where,
op
= opcode
rs
= first source register 
rt
= second source register 
rd
= destination register 
shamt
= shift amount indicating how many times a register must be shifted left or right (onlyused in shift instructions)
funct
= distinguishes among R-type instructions as all R-type instructions have op = 0.
 Example
:
add $1, $2, $3
The machine encoding of this instruction will be as follows:
0 2 3 1 0 32
 
CS-421 Parallel Processing BE (CIS) Batch 2004-05Handout_4
Page - 2 - of 3
 
All arithmetic/logic instructions in MIPS are 3-address instructions i.e. they need to specify three operands.Hence, MIPS is a 3-address machine. No arithmetic/logic instruction is allowed to have a memory location asone of the operands i.e. only registers or in some instructions one immediate operand is allowed. Hence,MIPS is a
register-register
architecture.
2.
I (Immediate) Format
This divides the instruction into four fields as follows:6 5 5 16op rs rt Immediate/offsetThis instruction format is used by following instruction types:
 Example 1
:
addi $1, $2, 25
This instruction adds 25 to the contents of register $2 and stores the result in $1. The machine encoding of this instruction will be as follows:op 2 1 25
 Example 2
:
 Data Transfer (Memory Reference Instructions)
lw $1, 40($2)
This instruction loads a word (1 word = 32 bits i.e. 4 bytes) from memory at the
address
given by
$2 + 40
into register $1. The register $2 contains the base register and thus regarded as base register. . That is, inregister transfer language (RTL), the working of above instruction can be described as follows:
$1
Mem [$2 + 40]
The machine encoding of this instruction will be as follows:35 2 1 40Please note that here
rt
is interpreted as a destination register rather than a source register.
sw $1, 40($2)
This instruction does the reverse of 
lw
. Specifically, it stores a word from a CPU register ($1 in this example)into memory at the
address
given by
$2 + 40
The RTL description of the instruction follows:
 Mem [$2 + 40]
$1
The machine encoding of this instruction will be as follows:43 2 1 40
 
In MIPS only load/store instructions are allowed to access memory. No other instruction can access memory.Such an architecture is called a
load-store architecture
. You must appreciate that
load-store architecture =register-register
architecture.
 
All RISC (Reduced Instruction Set Computers) use load-store architecture. What’s reduced in a RISC?Instruction formats, addressing modes, number of instructions, virtually everything except a large set of 

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