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Flip Flop

# Flip Flop

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07/23/2013

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P517/617 Lec10, P1Review from last week:Flip-Flops:Basic counting unit in computercountersshift registersmemoryExample: RS flip-flop or Reset-Set flip-flopFlip-flops, like logic gates are defined by their truth table. Flip-flops are controlled by anexternal clock pulse.
R S Q0 0 Q1 0 00 1 11 1 undefined
n+1n
RSCQQ
Q
n
is the present state of the FF and Q
n+1
will be the output after the clock enables the FF tolook at its inputs (R and S).Many FF’s change state (Q
n
Æ
Q
n+1
) on the trailing edge of the clock.Note:
The state with
R = S =1
is undefined. The output is not predictable!
Example: D flip-flop (Like RS but only one input)
DQQ0 0 00 101011 1 1
next
DQQClock
Example: JK flip-flopJKFF is like the RSFF except that both inputs (J and K) can be high (1).
J K Q0 0 Q1 0 10 1 01 1 Q
n+1n
JKCQQ
n
Most JKFF's have a connection for forcing Q = 0 (reset) or forcing Q = 1 (set).

P517/617 Lec10, P2Example: T (
Toggle
) flip-flopT flip-flop is like the JKFF with both inputs (J and K) tied to each other.
TQQ0 0 00 1 11 0 11 1 0
next
TQQClock

A few words about clocking the flip-flops and timing of inputs.Setup time:For each type of flip-flop there is a minimum specified time relative to the clock pulseduring which time the input(s) to the FF must be stable (i.e. not change logic levels).Hold time:For each type of flip-flop there is a minimum specified time after Q changes state thatthe input(s) to the FF must be stable (i.e. not change logic levels).Example: 74LS112 JK flip-flop (the one we use in lab)This FF changes state (Q) relative to the trailing edge of the clock.The setup time is 20 nsec (2x10
-8
sec) while the hold time is
ª
0 nsec.The maximum clock speed of this FF is 30 MHz.
Clock5 V0 V
hold
setup
Thus the data on J and K must be stable for at least
setup
+
hold
.

Sometimes circuits with flip-flops are classified according to how the clock is distributed to theFF's.There are two clocking schemes:Synchronous:All FF's are clocked at the same time. The easiest way to do this is to use oneclock and distribute it to all the FF's.Asynchronous: FF's are clocked at different times, usually by different clocks. Last week'sexample was an example of this type of circuit. The first FF was clocked bya "clock", while the second FF was clocked by the output (Q) of the first FF.

P517/617 Lec10, P3Example: Divide by 10 ripple down counter (counts from 9 to zero)Asynchronous counter
JCKSRQQJCKSRQQJCKSRQQ+5 VJCKSRQQclock+5 V+5 V+5 VQ
ABCD
QQQ
J
A
=
1 J
B
=
Q
C
Q
D
=
Q
C
+
Q
D
J
C
=
1 J
D
=
Q
B
+
Q
C
=
Q
B
Q
C
K
A
=
1 K
B
=
1 K
C
=
1 K
D
=
1
clockQQ = clock for BQQ = clock for CQQ = clock for DQhighlowhighlowhighlowhighlow98765432100count

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