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DFT Strategies

DFT Strategies

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Published by Ashok A
DFT methods, analog, mixed-signal DFT.

DESIGN-FOR-TEST STRATEGIES FOR ANALOGUE AND MIXED-SIGNAL
INTEGRATED CIRCUITS

BILBO

Support for External Test
DFT methods, analog, mixed-signal DFT.

DESIGN-FOR-TEST STRATEGIES FOR ANALOGUE AND MIXED-SIGNAL
INTEGRATED CIRCUITS

BILBO

Support for External Test

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Published by: Ashok A on Sep 09, 2013
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DESIGN-FOR-TEST STRATEGIES FOR ANALOGUE AND MIXED-SIGNALINTEGRATED CIRCUITS
Andrew Richardson
(1)
, Thomas Olbrich
(1)
, Valentino Liberali
(2)
, & Franco Maloberti
(2)
(1) Microelectronics Research GroupLancaster UniversityLancaster LA1 4YR, UKE-mail: a.richardson@lancaster.ac.uk,t.olbrich@lancaster.ac.uk (2) Dipartimento di ElettronicaUniversità di PaviaVia Abbiategrasso, 20927100 Pavia, ItalyE-mail: valent@ipvsp4.unipv.it,franco@franco.unipv.it
Abstract
Recent advances in technology are leading to increases inthe complexity and applications of analogue and mixed-signal integrated circuits. This trend has been accomponiedby an increase in the complexity of associated testspecifications. Furthermore, the use of functional &specification based test programs for the analogue circuitryis being questioned due to high implementation costs, thedifficulties associated with quantifying the effectivness of thetests and in many cases difficulties in accessing embeddedanalogue macros. In addition quality levels expected byintegrated circuit (IC) users are increasing, with typicaltargets currently being better than 40 ppm defect levels.New test solutions are therefore required for these circuittypes. Design-for-Test (DfT) strategies are well establishedfor digital circuits, whilst for analogue and mixed signalcircuits, few techniques have been proposed andimplementation of custom approaches is rare. This paperpresents a summary of a number of possible approaches forimproving test access by increasing both controllability andobservability of internal functional blocks in analogue andmixed-signal ICs, evaluating both their effectiveness andtheir impact on circuit performance.
1: Introduction
The development of CMOS technology has been drivenmainly by digital electronics. Now the trend towardsintegration of complete systems on single silicon requiresmixed analogue-digital technology to realise both digitalsignal processing and analogue interface functions. Thistrend creates new problems and requires considerableresources to be applied to the development of new designconcepts.Methodologies for digital Design-for-Test (DfT) are wellestablished and include techniques such as scan path,boundary scan, and BILBO that have become widely used byindustry [1].On the other hand, it is well known that analogue design isstill far from the automation level achieved in the digitaldesign domain. Design of analogue blocks is often thebottleneck in the development of mixed analogue-digitalsystems. While the analogue section is usually limited to 5 -10 % of the mixed chip area, its design can take 80 - 90 %of the development time. The trend for test is similar in thatthere are no formal approaches that can be exploited tominimise test time for analogue functions and no coverageevaluation tools available.The importance of mixed-signal system development ismotivating the development of (DfT) techniques inanalogue and mixed signal integrated circuits (ICs), tosupport increased fault coverage and to reduce testing time.This paper presents an oveview of techniques that have thepotential to contribute to these objectives. Section 2discusses the backgound and motivation for research activityin this area. Section 3 defines the concepts of DfT. Section4 presents a survey of various DfT techniques, illustratingtheir capabilities and limitations. Pros and cons of differentapproaches are discussed in Section 5.
2: Background and Motivation
The motivations to employ DfT strategies in IC design arenot obvious at the first glance. Add-on test circuitry does notimprove the primary circuit functions. It does not make acircuit faster, it does not reduce the power consumption, andit does not make it more robust to variations of process orenvironmental parameters.Even worse, the circuitry for testing adds additionalproblems. Circuit performance is degraded by for exampleswitching elements in signal paths. The chip complexity
 
increases. The “beauty” and “elegance” of a particularcircuit solution is often questionable after test circuitry has“ruined” the layout (this is a point to which especiallyanalogue designers react very sensitively).The absolute worst case for an analogue designer seems to bea DfT approach which involves a completely new designstrategy. A DfT strategy which is not merely an add-onmodule to an existing (and working) circuit solution but isdominantly shaping the silicon solution (by for exampledetermining the module boundaries) seems to bringlimitations and restrictions to the freedom of the analoguedesigner (and the circuit implementation) which are oftenexpressed to be “unbearable”.And on top of all, every DfT approach requires additionalcircuitry which increases the chip area, therefore increasingthe die manufacturing costs and increasing the probability ofaults in the chip (through increased die size).
So, why worrying about DfT at all
?The driving force to utilise DfT strategies for analogue andMixed Signal ICs comes from market demands. One mainreason for DfT is to reduce the (final) costs of ICs throughreducing testing time. Testing a mixed-signal chip afterproduction is responsible for between 30 and 80% of thetotal cost, depending on chip system complexity, volume,and applicational demands.Furthermore, DfT increases the testability (per definition)and, therefore, increases the fault coverage which in turnincreases the reliability of a circuit in the field by reducingearly life failures. In the opinion of the authors:
“The current trend in the IC industry towards “single figure ppm levels” necessitates the integration of DfT strategies tosupport high fault coverage and low cost production test with minimal performance penalties to maintain thecompetitive edge
.”A third reason to employ DfT for ICs are demands fromsafety critical, highly dependable, or highly reliableapplications. Complex solutions for the health, the nuclear,or the transportation industries (including automotive,aerospace and public transportation applications) demandhigh testability and (on-line) functional verification to allowsafe, dependable and reliable operation. Furthermore,legislative requirements and demands from insurers in manycases necessiate proof on “completeness” in testing aftermanufacture and even on-line verification capabilities forcertain applications [17].DfT emerges from a mere idea to make the test engineers lifeeasier to a concept which is paramount to successful ICdesign, production, marketing, and sales.
3: The concepts of Design-for-Test (DfT)
What is the definition of Design for Test or Design forTestability? What techniques does the
 DfT 
acronymembrace?Williams and Parker [18] describe DfT as follows:
“The collection of techniques that comprise Design for Testability are, in some cases, general guidelines; in other cases, they are hard and fast design rules. Together they canbe regarded essentially as a menu of techniques, each withits associated cost of implementation and return oninvestment”.
An alternative definition proposed by the authors is;
“To support the implementation of IC test capable of satisfying the demands on exhaustiveness and associated cost such as testing time, circuit overhead, and tester requirements for competitive, marketable products.
An important issue on improving testability is theaccessibility of nodes. Submicron technologies allow us tointegrate millions of transistors into a single chip. How canwe ensure that every component is working? Techniques onhow to inject signals into embedded modules/nodes(controllability) and on how to access the (test) response(observability) with adequate resolution are essential for thispurpose. Other major concerns are the ‘isolation’ of circuitmodules (to fully exploit digital testing techniques) and thepossibility of testing analogue functions separately.The ‘continuous’ and ‘distributed’ nature of signals isparticular to analogue circuits. For this reason, analogueDfT differs from digital DfT (as analogue design differsform digital design).
4: Design-For-Test Approaches
Fig. 1 groups various techniques for DfT in six clusters andgives examples. Despite the differences in their approachthey all have the same aim of improving the testability of ICdesigns.
4.1: Rules and Guidelines
Most DfT rules and guidelines to improve testability are‘good practice’ or ‘common sense’ knowledge on circuitdesign gathered from previous experience [1]. A set of general principles has been developed [19], quite similar tothe ‘ad-hoc’ testing techniques in digital design:
Partition the circuit in macro blocks;
Control macro inputs;
Observe macro outputs;
Disable feedback paths;
Place digital storage elements at A/D and D/A interfaces;
 
Use digital digital test access port to select test mode.These guidelines can also be integrated in CAD tools andmonitored via design rule checkers.
4.2: Support for External Test
Support for external test and evaluation is an importantapplication of DfT.Power supply current monitoring or I
DDQ
testing [20] hasbecome a standard test technique in industry for digitaldesigns. It may well be feasible to use the technique onmixed signal devices where appropriate circuit partitioningstrategies are applied to ensure that analogue sections areeither isolated (eg. separate power supplies) or test modesare used (where for example analogue modules are set into asleep mode) to ensure the analogue circuitry has negligableeffect on current levels during digital I
DDQ
test. Variousforms of current testing have been investigated for analoguecircuitry. Process variations in certain analogue components,particularly the bias chains can cause wide variations infault-free current levels that can effectively mask many faulteffects [14]. Possible solutions have been proposed includingtaking two supply current measurements for two “oppositepolarity” input signals, and processing the results so that thebias current component is effectively cancelled. [21]. It mayalso be feasible for certain circuits to include additionalcurrent mirror structures to effectively mirror the biascurrent for an anaolgue block to an additional probe pad.This would be a form of DfT or partial replication and couldbe used to provide access to the bias current for the analogueblocks during probe test.Other ‘external’ testing techniques in this category areTransient Response Analysis [15] and Residual MultipleFrequency Testing [16].Transient Response Analysis requires the introduction of aspecial interface scan structure between analogue and digitalsubsystems. The analogue part is excited with impulses andits output is digitised and processed to evaluate the frequencybehaviour.Residual Multiple Frequency Testing is suitable for linearanalogue blocks with bandpass frequency response. Twosinusoidal signals are used, which lie just above and justbelow the operation bandwidth. By retrieving theamplitudes of test signals at the analogue output, faults canbe detected. It is worth mentioning that this technique can
Laout Desin RulesDesign for Testability Rules (1)“Good Practice” Circuit DesinScan Path,
1149.4
(2)Sinal Inection in OPA,
SwapAmp
(3)Intermediate Voltage Testing (6)Stead State Current Detection (7)Analoue Shift Reister (4)Analogue Fault Checker (5)Test Partitionin b Reconfiuration (8)
Concurrent Error Detection for ADC (9)
Alorithmic Self-Test (10)Manaed Built-In Test (11)
ADC, DAC Self-Test on CODEC chip (12)
Hbrid Built-In Self-Test,
 HBIST 
(13)IDDx Testin (14)Transient Response Testing (15)Residual Multile Fre. Testin (16)
Designfor Test
General DfT Rules &Guidelines
On-Chip Generation/ Eval. of (Test) Stimuli
Access to EmbeddedModules/ NodesSet-Up & Execution of Module Test (BIST)On-Chip Multi-Module/ System TestSupport for ExternalTest & Evaluation
Figure 1: Various Design for Test (DfT) techniques and implementation examplesFig. 2 - Additional mirror structure on Asymmetric OTA.

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