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MC74LCX00

MC74LCX00

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Published by Randall Mata Rivera
Manuales de Servicio
Manuales de Servicio

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Published by: Randall Mata Rivera on Sep 21, 2013
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***************************************************** Format this file using a monospace font. ** Courier nine point type is the original format. ******************************************************* Motorola Semiconductor Products Sector* Logic and Analog Technologies Group* Logic Integrated Circuits Division** File:* SSDT release ID:* Filename: lcx00.g55j* Device: LCX00 (G55J)* Output type: non-tristating* Model parameters: SPICE Level 3* Date: 4/5/96* Rev: 1.0* ----------------------------------------------------------------------------* Dear Customer,** Presented below are an input/output device netlist and model cards. Before* proceeding with the modeling of this device, there are several points of which* you should be aware:* First, the netlist below is not intended to represent the entire device,* and should not be used to simulate propagation delays through the device,* rather, the netlist should be used only to gauge output performance and input* loading.* Second, this netlist does not include the five volt tolerant circuitry* utilized on the outputs, as that circuitry is proprietary. For this reason,* any attempt to simulate a five volt tolerant situation on the outputs* will be non-functional. However, the information conveyed by simulation of* the netlist will still be accurate for systems design, as deletion of the five* volt tolerant circuitry will only marginally affect the output characteristics* under normal operating conditions.* Last, please be advised that this device was designed using a Motorola* proprietary model, and that these models were not used in the actual device's* design. However, the parameters have been extracted directly from the* Motorola process used for the fabrication of these parts, and hence should* reflect its behavior reasonably well.* Should you need additional assistance or information, please contact your* Motorola applications engineer.** ----------------------------------------------------------------------------* Simulation notes:** This text is not intended to be a full tutorial regarding the simulation of* LCX parts in systems. For more detailed information, please refer to the* current revision data book.*** 1) Data to output* A) Pulse node inAn full range, with 0V and Vcc endpoints. This node is* internal to the chip, and, as such, has a higher switching speed than* that specified for LCX inputs. It is best to use a typical internal* rise and fall times of 1ns, full range, 0V to Vcc. The output, On,* will be inverted relative to the input.* B) Force Vcc at the appropriate voltage: 2.7V, 3V, 3.3V or 3.6V* C) Force the An node to 0V or 2.7V. The state is irrelevant, but it must * be forced to avoid simulator failures during convergence.
 
* D) Set the operating junction temperature.** 2) The An, port is fully represented in the netlist. To simulate bus loading* of the inputs, use the appropriate input structures, as partitioned below,* in the netlist.* 3) The DW and XQC parameters have been commented out of the models, as many* SPICE level 3 simulators will not accept these input variables.** Additional simulation notes:** The user is assigned the responsibility of placing the appropriate forces on* the desired nodes. The LAn, lvcc and lgnd lead inductances are all defaulted* to 2.5nh. These elements are placed early in the netlist, as are the* operating and nominal temperatures, for easy access and simulation control.** Please note that the lead inductance on the On pad (2.5nh, attached at node* 505), must be added by the user, as some simulators will not accept a floating * inductor lead, thus causing the simulator to halt.************************* Top Level Schematic ********************************** Please note inductances, resistances and input protection devices are not* represented in this schematic. It is intended only to give the user an* idea of the circuit topology without direct schematic transfer.** |\* | \* An (Node 504) o-----| \o-------o AnB (Node 510) VCC (node 502)* | /* | /* |/** |\* | \* inAn (Node 506)o-----| \o-------o On (Node 505)* | /* | /* |/*********************************************************************************** Net summary** Port Node Number Force* An 504 0V or Vcc* inAn 506 Pulse 0V to Vcc, 1ns 0 to 100%* On 505 Data output monitor* AnB 510 Output of An inverter interface to the* internal chip. Lead inductance, input* protection devices, and pad* capacitance occur between* this port and the An input.* internal (chip) vcc (ivcc) 509 N/A (couples to global VCC via LVCC)* Global (system) VCC 502 2.7V, 3V, 3.3V or 3.6V* internal (chip) gnd (ignd) 511 N/A (couples to global GND via LGND)* Global (system) GND 0 0V** Note that you must provide forces on the following nodes for the simulation to* function properly:
 
** An 504* inAn 506* VCC 505********************************************************************************* SPICE format circuit netlist********************************************************************************** Run control* Example forces for data in (inAn, node 506) to output (On, node 505)Vdz0 504 0 DC 3 * AnVdz1 506 0 PULSE 0 3 0 1e-09 1e-09 5e-08 1e-07 * inAnVdz2 502 0 DC 3 * Vcc* Temperature.options tnom=27.temp=27* Transient.tran 1e-10 1e-07 0* Lead inductances* Please note that the lead inductance on the On pad (node 505), must be added* by the user, as most simulators will not accept an inductor lead directly* attached to an unforced (output) port. For this situation, the user should* attach an appropriate load, representing the bus, between the added inductor* and the On output lead, node 505.* Internal (chip) ground to global ground inductancelgnd 511 0 2.5nH* Internal (chip) ground to global Vcc inductancelvcc 502 509 2.5nH* A(n) input sectionlan 504 503 2.5nHMamnjznm 503 511 511 511 NMOS AD=7150P AS=1950P W=650U+ NRD=0.007692 NRS=0.001538 PD=1322U PS=1306U L=1UMahvpmos 503 509 509 509 PMOSHV AD=4950P AS=2700P L=1U NRD=0.005556 NRS=0.001111+ PD=922U PS=1812U W=900Uran 503 501 250can 503 511 0.882PMiz5zpmo 510 501 509 509 PMOS AD=120P AS=180P L=1U NRD=0.0125 NRS=0.0125 PD=92U+ PS=138U W=80UMiz6zpmo 510 501 509 509 PMOS AD=60P AS=60P L=1U NRD=0.05 NRS=0.05 PD=46U PS=46U

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