A Current-Starved Inverter-Based Differential Amplifier Design for Ultra-Low Power Applications

William Wilson, Tom Chen, Ryan Selby Department of Electrical & Computer Engineering Colorado State University, Fort Collins, CO 80523 USA
Abstract As silicon feature sizes de crease, more complex circuitry arrays can now be contrive d on a single die. This increase in the numbe r of on-chip de vices per unit area results in increase d powe r dissipation pe r unit area. In order to meet certain power and ope rating temperature spe cifications, circuit design ne cessitates a focus on power efficiency, which is especially important in systems employing hundreds or thousands of instances of the same de vice. In large arrays, a slight increase in the powe r efficiency of a single component is heightened by the numbe r of instances of the de vice in the system. This paper proposes a fully differential, low-power current-starving inve rter-base d amplifie r topology designed in a commercial 0.18m process. This design achie ves 46dB DC gain and a 464 kHz unity gain frequency with a powe r consumption of only 145.32nW at 700mV powe r supply voltage for ultralow powe r, low bandwidth applications. Higher bandwidth designs are also proposed, including a 48dB DC gain, 2.4 MHz unity-gain fre quency amplifier operating at 900mV with only 3.74W power consumption.

schemes have been improving with the usage of active compensation networks. [3-13] Reduced power supply voltage and the increasing demand for low power consumption make sub-threshold operation and design a more viable alternative when a reduction in bandwidth is acceptable. Operation in the sub-threshold region causes the drain current to increase exponentially with VGS as opposed to quadratically in the saturation region [14]. The disadvantage with sub-threshold operation is the reduction in amplifier driving current, and the loss of ability to quickly drive large capacitive loads. In this paper, an inverter-based operational amplifier topology and operation and design principles are discussed and evaluated. We use two previously used figures of merit to objectively compare various aspects of the different circuit topologies. We conclude that the inverter-based differential amplifier topology with current starving provides one of best circuit topologies for energy efficiency.

INTRODUCTION
Operational amplifiers are essential components in many signal processing circuit designs. Almost any type of analog circuits, including most continuous or discrete time amplifiers, analog to digital converters, sense amplifiers, and many other circuits use some variety of operational amplifiers as their basic building blocks. These and various other circuit designs are used in many tasks, including the amplification of small signals, as well as various types of mixeddomain processing for complex audio and video signals.[1] M any large-scale system-on-chip designs such as imaging and sensing arrays use complex signal processing chains. These systems often use mixed-signal chains in sub-m processes. These reduced channel length processes have desirable effects on performance and overall size in digital circuitry; however, reduced channel lengths have undesirable effects in analog circuit designs. Low power supply voltages and decreased output impedance, as well as limited gain of single transistor stages make analog circuit design in sub-m a challenging task [2]. Traditional operational amplifier designs most commonly use transistors in the saturation region, which generally requires at least one DC bias current. As technology size has decreased, low power, high gain amplifier design has become more ch allenging for designers. Since transistor threshold voltage generally doesnt decrease as fast as feature size and power supply voltage, many cascaded or folded designs are not possible with reduced voltage supply. Given that the reduction in headroom reduces the ability to cascode devices, low voltage high-gain amplifiers are commonly built by expanding outward, using two or even three cascaded amplification stages. These multi-stage cascaded designs require the designer to take extra measures to ensure amplifier stability, and, depending on the topology, can be very challenging or complex to stabilize. M ost stabilization schemes require additional compensation capacitors and/or nulling resistors, which use additional silicon area, and can decrease circuit bandwidth; however, these compensation

PROPOSED DESIGN
A prior attempt at achieving high gain with minimal DC current usage and minimal area is the use of CM OS inverters in a differential configuration [15-18].

F IGURE 1: INVERTER-BASED O P -AMP The inverter-based amplifier topology shown in Figure 1 uses CMOS inverters as the amplifier input. This input stage design has the advantage of combining the transconductance of the n and p transistors.
Gm = Gmn + Gmp

This combination of the two transconductances should provide 6dB increase in gain over a traditional common source amplification stage, with approximately the same DC bias current. When this architecture is implemented with a standard supply voltage (>2v t), the overall transconductance can be increased significantly depending on how transistors in the inverters are sized and the resulting current through the inverter. High current through the

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inverter allows significantly high bandwidths to be achieved. Another advantage of this topology is an increase in output swing and linearity when compared to a traditional common source or cascode amplifier if the respective transconductances of the p and n type transistors are approximately equal in magnitude. For noise, the inverter-based topology offers lower equivalent noise resistance compared to the equivalent common source topology [20]. Assuming the p and n type transistors are balanced and the equivalent noise resistances for the n and p type transistors is R Nn, and RNp, respectively, the equivalent noise resistance for the inverter based amplifier is
RN =
2 2 Gmn RNn + Gmp RNp

FIGURE 3: ACTIVE LOAD WITH POSITIVE FEEDBACK The positive portion of the resistance provided by the diode connected inverters helps stabilize the inherently unstable negative impedance of the cross-coupling, as well as providing additional DC bias stability for both the input and cross-coupled inverter pairs. This combination of positive and negative impedances gives the active load circuit an overall output impedance of
Ro = 1 g m 2 - g m3

(G

mn

+ Gmp )

RNn 2

One weakness of the inverter-based amplifier is its limited CM RR when configured in a differential mode as shown in Figure 1. This issue will be addressed in the next sub-section.

Sub-Threshold Operation With Current Starving Tails

When this inverter-based architecture is implemented at a low supply voltage (<2vt), the inverter transistors will operate in the subthreshold region. Because of this region of operation, bias currents and power consumption can be significantly reduced, with the sacrifice of bandwidth and amplifier driving strength. A tail current source can be added to better control the current flow through the inverters, pushing the transistors further into the sub-threshold region, and further reducing power consumption. The tail can also improve the amplifiers CM RR and provide an additional input that can be used for common-mode feedback, circumventing the issue with the original inverter-based design in [15-18]. In addition, the use of tail separates the need for low power consumption and low input offset voltage. Inverters can be sized appropriately to control offset voltage while the tail controls the overall power consumption allowed by the inverter.

Assuming low mismatch between the M 2 and M 3 inverter pairs, this gives extremely high output impedance. Similar to a folded cascode, this circuit combines the transconductance of the input pair with the output impedance of the cross coupling and diode-connected inverters. The overall voltage gain of the amplifiers half-circuit can then be defined as

When sizing the transistors in this design, it is desirable for the input and tail transistors to have reasonably large lengths (typically >1m) and large W/L ratios (typically >16) to improve output impedance, and to have an increased transconductance. Large lengths, especailly in the cross-coupled inverters help alleviate the effects of PVT.

SIMULATION RESULTS AND DISCUSSIONS

The current starved inverter-based amplifier was designed for three different supply voltages of 0.7V, 0.9V, and 1.1V, allowing it to operate at different levels of sub-threshold regions with different driving strength. With the aim for low-power bioelectronics applications, the design goal is to achieve the maximum energy efficiency possible with the performance suitable for driving internal circuit nodes of no more than 2pF load. Table 1 shows the simulation results of the inverter-based Op-Amp under three different supply voltages. T ABLE 1: SIMULATION RESULTS OF T HREE INVERTER O P -AMP S Designed Supply Voltage DC Gain Load GBW Overall DC Current Power Consumption Offset Voltage Input Referred Noise CM RR FOM 1 FOM 2 700mV 46.22dB 1.8pF 463.9kHz 207.6nA 145.32nW 2.273mV 25.524V 124.397dB 4022 5746 900mV 48.36dB 6pF 2.408M Hz 4.157A 3.741W 2.167mV 6.428V 153.055dB 3475 3861 1.1V 47.9dB 15pF 3.94M Hz 20.56A 22.616W 2.443mV 3.5V 177.897dB 2874 2612

FIGURE 2. INVERTER OP -A MP WITH T AILS The proposed topology shown in Figure 2 employs an active load consisting of four additional load inverters (M 2, M 3). The innermost pair of these inverters is connected in a cross-coupled configuration, while the outer pair of inverters is diode-connected as shown in Figure 3. The cross coupled pair provides positive feedback and therefore a negative resistance of -2/gm 3. The diode connected pair provides an equal, yet positive resistance of 2/gm2.

To more effectively compare energy efficiency of the inverterbased design with some of the existing published designs, we use two different Figures of M erit (FOM s) for comparison.

Figure of Merit
The first FOM we use is defined as:

When designing with higher supply voltages, designers have the option of increasing input and tail transistor lengths, keeping the lowcurrent properties of the topology. Again, this approach can be advantageous when the application does not require a high bandwidth amplifier.

Design Comparison
We would like to compare the proposed design in the context of a wide range of existing designs from simple common source amplifiers, to telescopic amplifiers, to traditional M iller compensated amplifiers, and to the more advanced three-stage amplifiers. Simple or folded cascode operational amplifier designs typically can achieve a FOM of 200-300[1, 2]; telescopic amplifiers typically have a higher FOM around 500-700; traditional M iller compensated twostage amplifiers achieve a FOM of around 1000. State-of-the-art three-stage M iller compensated amplifiers can achieve a FOM in the 3000-5000 range, and even over 10,000. [4, 5] As stated previously, these larger three stage M iller amplifiers require complex stabilization and compensation schemes, and can be significantly large on silicon. Table 2 shows the comparison of the amplifiers in this work to various types of operational amplifiers. The table includes all parameters necessary for figure of merit calculation, as well as both the power and current based figures of merit. M any of the existing amplifier topologies listed in Table 2 consist of multiple stages, and employ complex stabilization schemes. These amplifiers are generally designed to have a high bandwidth and drive large capacitive loads. Due to its current-starving nature, the inverterbased amplifiers are more suitable for smaller loads and less stringent settling time requirements. Therefore, low power bioapplications will be able to take the full advantage of the design. Trading for higher power consumption and lower FOM s, the inverter-based designs can be configured with higher supply voltage to drive larger loads as shown in Table 2. Even with the lower FOM associated with the inverter based design at 1.1V supply voltage, its FOM still surpasses some of the more complex designs.

FOM1 =

GBW (MHz ) CL ( pF ) I (mA)

This FOM focuses on return-on-driving-current. It does not directly measure the impact of supply voltage scaling. If comparisons are made on circuits operating on the same supply voltage, this FOM gives an accurate comparison. Otherwise, it tends to penalize designs with lower supply voltages. To compensate for the impact of supply voltage, the second FOM is defined as: GBW ( MHz ) CL ( pF ) FOM 2 = P(mW ) The second FOM is similar to the first, except that total power is used to measure its return on performance and overall driving strength.

TOPOLOGY SCALABILITY AND FLEXIBILITY

The primary advantage with our proposed topology is the scalability (overall number in a system) in terms of both power and area, without a significant compromise in performance. This topology can be used at higher voltage supplies, and even outside the sub-threshold region. As supply voltage increases, the inverter transistors tend to operate less deep into the sub-threshold region, or if supply voltage is raised significantly high, in the saturation region. Higher supply voltages, and in turn, higher currents, tend to have a positive effect on the bandwidth of the amplifier; however, this positive effect isnt significant enough to completely cancel out the effect of the increased overall current on the circuits FOM .

T ABLE 2: COMP ARISON O F VARIOUS AMP LIFIER DESIGNS Existing Designs TSEFC[3] SM CFC[4] M NM C[6] NGCC[7] NM CFNR[8] DFCFC[10] AFFC[11] DLPC[12] ACBCF[13] 700mV supply, Inverter-based 900mV supply, Inverter-based 1.1V supply, Inverter-based Amplifier Type 3-Stage M iller Comp. 3-Stage M iller Comp. M ultipath Nested M iller Comp. M ultistage Nested G m -C Comp. Nested M iller Comp. 3-Stage w/Active Feedback Freq. Comp. 3-Stage w/Active Feedback Freq. Comp. Dual Path, Dual-Loop Parallel Comp. 3-Stage AC Boosting Comp. Inverter-Based Inverter-Based Inverter-Based Process 0.35m 0.35m bipolar 2m 0.8m 0.8m 0.6m 0.6m 0.35m 0.18m 0.18m 0.18m CL(pF) 500 150 100 20 100 100 100 120 500 1.8 6 15 GBW(M Hz) 1.4 1.6 100 0.61 1.8 2.6 5.5 7 1.9 0.4639 2.408 3.94 Power(mW@VDD) 225@1.5 21@1.5 76000@8 680@2 406@2 420@2 250@1.5 330@1.5 324@2 0.14532@0.7 3.741@0.9 22.616@1.1 FOM 1 4666.5 17143 1056 36 886 1238 330 3817.5 5864 4022 3475 2874 FOM 2 3111 11430 132 18 443 619 220 2545 2932 5746 3861 2612

CONCLUSION
In this paper, a fully -differential inverter-based amplifier topology with the current starving feature has been evaluated. While the idea of inverter based amplifiers is not conceptually novel, the idea of better controlling the current through the inverters using the concept of current starving for low power applications, as well as better CM RR and common-mode control makes the concept of inverter-based amplifiers more practical in real applications, particularly for applications for low power and low supply voltages. Simple modifications or considerations during the design phase can considerably increase the circuits usability. The concept of selfcascoded transistors can be applied to the tail transistors to further increase the benefits of increased impedance, such as additional current starvation and added common-mode noise and signal rejection while not giving up too much headroom. The overall size of the transistors in the input inverter pair can be increased, allowing this amplifier to be used in applications requiring a low-offset, lownoise op-amp. Tail transistor width, as well as input inverter pair width can be increased, allowing higher current flow, making this topology useable in applications requiring a high bandwidth. The most advantageous principle of this topology is its simplicity. As the task of designing low-voltage high gain amplifiers in sub-m digital processes is becoming more complicated for designers, this proves to be a simple circuit to design and optimize. This topology efficiently provides a significant gain for a single-stage amplifier, and can be used in many configurations, including both continuous time and switched-capacitor circuitry.

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