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ASIC-CH13

# ASIC-CH13

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This a complete book (Chapter-1 to Chapter-17) on ASIC for basic to advanced level understanding.
This a complete book (Chapter-1 to Chapter-17) on ASIC for basic to advanced level understanding.

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05/11/2014

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ASICs...THECOURSE(1WEEK)1
SIMULATION
Key terms and concepts:
Engineers used to prototype systems to check designs •Breadboarding is feasible for systems constructed from a few TTL parts • It is impractical for anASIC • Instead engineers turn to
simulation

13.1
Types of Simulation
Key terms and concepts:

simulation modes
(high-leveltolow-levelsimulation–high-levelismoreabstract,low-levelmoredetailed): Behavioral simulation • Functional simulation • Statictiming analysis • Gate-level simulation • Switch-level simulation • Transistor-level or circuit-levelsimulation
13.2
The Comparator/MUX Example
Keytermsandconcepts
using
input vectors to
testor
exercise
// comp_mux.v//1
module
comp_mux(a, b, outp);
input
[2:0] a, b;
output
[2:0] outp;//2
function
[2:0] compare;
input
[2:0] ina, inb;//3
begin

if
(ina <= inb) compare = ina;
else
compare = inb;
end
//4
endfunction
//5
assign
outp = compare(a, b);//6
endmodule
//7// testbench.v//1
module
comp_mux_testbench;//2
integer
i, j;//3
reg
[2:0] x, y, smaller;
wire
[2:0] z;//4
always
@(x) \$display("t x y actual calculated");//5
initial
\$monitor("%4g",\$time,,x,,y,,z,,,,,,,smaller);//6
initial
\$dumpvars;
initial
#1000 \$finish; //7
initial
//8
13

2
SECTION 13 SIMULATIONASICS... THE COURSE
begin
//9
for
(i = 0; i <= 7; i = i + 1) //10
begin
//11
for
(j = 0; j <= 7; j = j + 1) //12
begin
//13x = i; y = j; smaller = (x <= y) ? x : y; //14#1 if (z != smaller) \$display("error");//15
end
//16
end
//17
end
//18comp_mux v_1 (x, y, z);//19
endmodule
//20
13.2.1 Structural Simulation
Key terms and concepts:
logic synthesis produces a structural model from a behavioral model •reference model • derived model •
vector-based simulation
(or
dynamic simulation
)
`timescale 1ns / 10ps // comp_mux_o2.v//1
module
comp_mux_o (a, b, outp);//2
input
[2:0] a;
input
[2:0] b;//3
output
[2:0] outp;//4
supply1
VDD;
supply0
VSS;//5mx21d1 b1_i1 (.i0(a[0]), .i1(b[0]), .s(b1_i6_zn), .z(outp[0]));//6oa03d1 b1_i2 (.a1(b1_i9_zn), .a2(a[2]), .b1(a[0]), .b2(a[1]),//7.c(b1_i4_zn), .zn(b1_i2_zn));//8nd02d0 b1_i3 (.a1(a[1]), .a2(a[0]), .zn(b1_i3_zn));//9nd02d0 b1_i4 (.a1(b[1]), .a2(b1_i3_zn), .zn(b1_i4_zn));//10mx21d1 b1_i5 (.i0(a[1]), .i1(b[1]), .s(b1_i6_zn), .z(outp[1]));//11oa04d1 b1_i6 (.a1(b[2]), .a2(b1_i7_zn), .b(b1_i2_zn),//12.zn(b1_i6_zn));//13in01d0 b1_i7 (.i(a[2]), .zn(b1_i7_zn));//14an02d1 b1_i8 (.a1(b[2]), .a2(a[2]), .z(outp[2]));//15in01d0 b1_i9 (.i(b[2]), .zn(b1_i9_zn));//16
endmodule
//17`timescale 1 ns / 10 ps//1
module
mx21d1 (z, i0, i1, s);
input
i0, i1, s;
output
z;//2
not
G3(N3, s);//3
and
G4(N4, i0, N3), G5(N5, s, i1), G6(N6, i0, i1);//4
or
G7(z, N4, N5, N6);//5
specify
//6(i0*>z) = (0.279:0.504:0.900, 0.276:0.498:0.890);//7

ASICs... THE COURSE13.2 The Comparator/MUX Example
3
(i1*>z) = (0.248:0.448:0.800, 0.264:0.476:0.850);//8(s*>z) = (0.285:0.515:0.920, 0.298:0.538:0.960);//9
endspecify
//10
endmodule
//11`timescale 1 ps / 1 ps // comp_mux_testbench2.v//1
module
comp_mux_testbench2;//2
integer
i, j;
integer
error;//3
reg
[2:0] x, y, smaller;
wire
[2:0] z, ref;//4
always
@(x) \$display("t x y derived reference");//5//
initial
\$monitor("%8.2f",\$time/1e3,,x,,y,,z,,,,,,,,ref);//6
initial
\$dumpvars; //7
initial

begin
//8error = 0; #1e6 \$display("%4g", error, " errors"); //9\$finish; //10
end
//11
initial

begin
//12
for
(i = 0; i <= 7; i = i + 1)
begin
//13
for
(j = 0; j <= 7; j = j + 1)
begin
//14x = i; y = j; #10e3;//15\$display("%8.2f",\$time/1e3,,x,,y,,z,,,,,,,,ref);//16
if
(z != ref) //17
begin
\$display("error"); error = error + 1;
end
//18
end
//19
end
//20
end
//21comp_mux_o v_1 (x, y, z); // comp_mux_o2.v//22reference v_2 (x, y, ref);//23
endmodule
//24// reference.v//1
module
reference(a, b, outp);//2
input
[2:0] a, b;
output
[2:0] outp;//3
assign
outp = (a <= b) ? a : b; // different from comp_mux//4
endmodule
//5
13.2.2 Static Timing Analysis
Key terms and concepts:
“What is the longest delay in my circuit?” • timing analysis finds thecritical path and its delay • timing analysis does not find the input vectors that activate the criticalpath •
Boolean relations
false paths
• a timing-analyzer is more logic calculator than logicsimulator