CC2510 Combinational Logic

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CC2510 Digital Logic and Computing Methods Combinational Logic and Boolean Algebra Logic Functions
(Wakerley Ch 4.1) AND produces an output 1 if input A AND input B are both 1 A 0 0 1 1 B 0 1 0 1 X 0 0 0 1

In Boolean Algebra the AND symbol is denoted by a or a In ABEL the AND symbol is denoted by & In VHDL the AND symbol is denoted by and Boolean ABEL VHDL Schematic X= A B X = A&B ; X := A and B ;

Switch configuration

OR produces an output 1 if input either A OR input B (or both) are 1 A 0 0 1 1 B 0 1 0 1 X 0 1 1 1

In Boolean Algebra the OR symbol is denoted by a + or a In ABEL the OR symbol is denoted by # In VHDL the OR symbol is denoted by or Boolean ABEL VHDL X= A + B X = A#B ; X := A or B ;

1998-2007, C. J. Kikkert, James Cook University

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Schematic

Switch configuration
A

NOT inverts the input A 0 1 X 1 0

The NOT symbol is denoted by a , by a / , or by a !, depending on the application Boolean X=A/ ABEL X=!A ; VHDL X := not A ; Schematic

Many logic circuits include inversions at the output of AND and OR functions, resulting in NAND and NOR functions. (Typically NAND gates are faster than AND gates) NAND (NOT AND) produces an output 0 if input A AND input B are both 1 A 0 0 1 1 Boolean ABEL VHDL Schematic B 0 1 0 1 X 1 1 1 0

X=(AB) / X = !(A&B) ; X := A nand B ; which can also be written as X := not ( A and B) ;

1998-2007, C. J. Kikkert, James Cook University

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NOR (NOT OR) produces an output 0 if input either A OR input B (or both) are 1 A 0 0 1 1 B 0 1 0 1 X 1 0 0 0

Boolean ABEL VHDL Schematic

X= (A+B) / X = !( A#B ) ; X := A nor B ; which can also be written as X := not ( A or B) ;

Representing a Logic Function

Truth table The input and corresponding output values are presented in a table, as above for the basic logic gates. It is very easy to indicate the requirements, but it is not so easy to then realise the function in hardware. To cover all the possibilities, for a 3 input Circuit, 8 rows are requires, for a 10 input circuit 1024 rows are required. The truth table is only manageable for less than about 5 inputs. The statement I can catch a fish if I have a fishing rod, worms and if the fish have not yet eaten can be represented as follows: Fishing Rod Worms Fish Full 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Truth table for catching fish Catch 0 0 0 0 0 0 1 0

Boolean Algebra representation The output is described by a Boolean algebra expression as indicated above. The only operators normally used are AND, OR and NOT. This form of expression can be applied to a logic circuit with many inputs. Catch = Rod Worms Full/

1998-2007, C. J. Kikkert, James Cook University

CC2510 Combinational Logic F = ((X+Y/)Z) /+(X/.Y.Z/) Boolean algebra expressions are very useful in representing logic functions.

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Boolean Algebra Theorems

(Wakerley Ch4.1.3) When we design a circuit we must take these specifications and turn them into some hardware with the least complexity and cost. We may have to manipulate the expressions manually or we may use some tools to do the reductions for us. The way we manipulate the expressions depends also on the hardware that is available. (NAND gates etc) Theorems for Boolean Algebra X+0=X X+1=1 X + X =X (X/)/ = X X + X/ = 1 Commutative Law X+Y=Y+X XY=YX Associative Law X + (Y + Z) = (X + Y) + Z = X + Y + Z X (Y Z) = (X Y) Z = X Y Z Distributive Law X (Y + Z) = (X Y) + (X Z) = X Y + X Z X + (Y Z) = (X + Y) (X + Z) Dual Networks Replacing by + and vice versa and replacing 0 by 1 and vice versa, changes an equation into its dual. If the equation is true, so is its dual. Example X 1 = X dual X+ 0 = X Useful expressions X + (X Y) = X X (X + Y) = X X + (X/ Y) = X + Y X (X/ + Y) = X Y / / X + (X Y) = X + Y X/ (X + Y) = X/ Y (X + Y) (X/ + Z) = X X/ + X Z + X/ Y + Y Z = X Z + X/ Y + Y Z De Morgans Theorem If Output = f(A, B, C, D .X, Y, Z, , +) X1=X X0=0 XX=X X X/ = 0

1998-2007, C. J. Kikkert, James Cook University

CC2510 Combinational Logic then Output/ = f(A/, B/, C/, D/ .X/, Y/, Z/, + , )

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Examples: (A B)/ = A/ + B/ A B = (A/ + B/)/

we can thus make an AND gate using a NOR gate.

A B C D E F G H = ((A B C D) / + (E F G H) / ) / 8 input gates are not available in small-scale logic (7400 series) devices but 4 input NAND gates are and two input NOR gates are. We must thus rearrange the Boolean Algebra equations to put these into a form, which includes available devices.

Schematic for 8 input AND gate.

Standard forms
(Wakerly 4.1.6) In many cases the specification of the logic function is obtained from a truth table. Example: 3 input adder A B Cin S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Truth table for Full Adder

0 1 2 3 4 5 6 7

S = (A/ B/ Cin) + (A/ B Cin/ ) + (A B/ Cin/ ) + (A B Cin ) Cout = (A/ B Cin) + (A B/ Cin ) + (A B Cin/ ) + (A B Cin ) An expression which is made up as an AND function, like the expression A/ B/ Cin is called a minterm. These can be written in a simplified form as: S = (1,2,4,7) sometimes the names of the variables are included, as S = A,B,Cin (1,2,4,7). This is called a canonical sum. It is a sum of standard product terms. A canonical sum is thus the sum of minterms corresponding to each row in a truth table. 1998-2007, C. J. Kikkert, James Cook University

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Cout = A,B,Cin (3,5,6,7) Similarly we can use DeMorgans Theorem to write our adder as: S/ = (A + B + Cin/) (A + B/ + Cin ) (A/ + B + Cin ) (A/ + B/ + Cin/ ) Cout/ = (A + B/ + Cin/) (A/ + B + Cin/ ) (A/ + B/ + Cin ) (A/ + B/ + Cin/ ) An expression which is made up as an OR function, like the expression A + B + Cin/ is called a maxterm. This can also be written in a simplified form as: S/ = A,B,Cin (0,3,5,6) Cout/ = A,B,Cin (0,1,2,4) This is a product of standard sum terms and is called a canonical product. Canonical sums are used more often that canonical products. A canonical product is thus a product of the maxterms corresponding to each row in a truth table.

Consider the 2 input AND gate: A 0 0 1 1 B 0 1 0 1 X 0 0 0 1

We can write this as: X= A B Applying DeMorgans Theorem to this gives: X/ = A/ + B/ Or we can write this as X/ = (A/ B/ ) + (A/ B) + (A B/ ) Applying DeMorgans Theorem to this gives: Minterm realisation of X/, ie X=0 Maxterm realisation of X/, ie X=0 Minterm realisation of X

1998-2007, C. J. Kikkert, James Cook University

CC2510 Combinational Logic X = (A + B) (A + B/ ) (A/ + B)

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Maxterm realisation of X, ie X=1

We can thus write any truth table in four standard forms. Realisation of the X as a Canonical sum (using minterms) Realisation of the X/ as a Canonical sum (using minterms) Realisation of the X as a Canonical product (using maxterms) Realisation of the X/ as a Canonical product (using maxterms)

Procedure for construction of Logic Circuits

1 2 Using truth tables or otherwise, develop the logic functional requirements for the circuit to be designed. Write down the Boolean Algebra expressions corresponding to the truth table.

For Medium scale logic (TTL etc) 3 Simplify the Boolean Algebra expressions, using Karnaugh maps or other techniques. 4 Manipulate the simplified expressions into a hardware-oriented form. 5 Construct the hardware. For Programmable Logic 3 Incorporate the Boolean Algebra Expressions into an ABEL or VHDL program. 4 Compile the program to generate the JED file. 5 Construct the required hardware. 6 Program the device using the JED file.

1998-2007, C. J. Kikkert, James Cook University

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Minimisation Techniques Boolean Algebra reduction

Using Boolean Algebra theorems, the expressions can be reduced. This is not straight-forward and one cannot guarantee that the optimum solution can be obtained. Example: T = A/ B/ C/ + A/ B C + A B/ C + A/ B C/ + A/ B/ C + A B C = A/ (B/ C/ + B C +B C/ + B/ C) + C (A/ B + A B/ + A/ B/ + A B) = A/ + C It is unlikely that one would be able to get that answer directly without knowing what it was supposed to be. Boolean Algebra reduction is thus not used to reduce complex circuitry

Karnaugh Map
A Karnaugh map is a simple graphical representation of a Boolean algebra function. For a four variable function, all the possible input combinations can be mapped as follows: YZ 00 01 11 10 00 / / / / WXYZ W/XY/Z/ WXY/Z/ WX/Y/Z/ 01 / / / WXYZ W/XY/Z WXY/Z WX/Y/Z 11 W X/YZ W/XYZ WXYZ WX/YZ
/

WX

10 W X/YZ/ W/XYZ/ WXYZ/ WX/YZ/

/

If instead of entering the variables, we put the numbers corresponding to the canonical sum, we get: YZ 00 01 11 10 00 0 4 12 8 01 1 5 13 9 11 3 7 15 11 10 2 6 14 10

WX

T = A/ B/ C/ + A/ B C + A B/ C + A/ B C/ + A/ B/ C + A B C Has the Karnaugh map as shown below: BC A 0 1 00 1 0 01 1 1 11 1 1 10 1 0

Reduction can take place if adjacent ones can be grouped

1998-2007, C. J. Kikkert, James Cook University

CC2510 Combinational Logic Grouping takes place in 2, 4, 8, 16 etc elements. A two element grouping corresponds to the Boolean algebra reduction: A/ B/ + A/ B = A/ (B/ + B) = A/

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A four element grouping corresponds to the Boolean algebra reduction: A/ (B/ C/ + B C +B C/ + B/ C) = A/ The top row in this map corresponds to this expression and can thus be reduced. The columns BC = 01 and BC = 11 correspond to the expression: C (A/ B + A B/ + A/ B/ + A B) = C Examples of linking T = (A/ B/ C/ D/ ) + (A/ B/ C/ D) + (A/ B/ C D/ ) + (A/ B C/ D/ ) + (A/ B C/ D) + (A/ B C D/ ) + (A B C D) + (A B/ C D)

CD 00 01 11 10 00 01 AB 11 10 1 1 1 1 1 1 1 1

The Karnaugh Map reduction results in: T= A/ C/ + A/ D/ + A C D

CD 00 01 11 10 00 01 AB 11 10
T = C/ + A B

1 1 1 1

1 1 1 1 1 1

Dont Care
Sometimes a value will never occur. In that case we do not care what the output is. In the Karnaugh map we label the appropriate square with a , a X or a d, depending on preferences. The dont care is included in the Karnaugh map loops only if convenient. 1998-2007, C. J. Kikkert, James Cook University

CC2510 Combinational Logic Example1: Consider a 7 segment display.

a

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f g

Seven Segment Display. Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a 1 0 1 1 0 1 1 1 1 1 X X X X X X b 1 1 1 1 1 0 0 1 1 1 X X X X X X c 1 1 0 1 1 1 1 1 1 1 X X X X X X d 1 0 1 1 0 1 1 0 1 1 X X X X X X e 1 0 1 0 0 0 1 0 1 0 X X X X X X f 1 0 0 0 1 1 1 0 1 1 X X X X X X g 0 0 1 1 1 1 1 0 1 1 X X X X X X Code 0 1 2 3 4 5 6 7 8 9 X X X X X X

Truth Table for Seven Segment Display with Numbers 0-9 only. The truth table can be used to map element d onto a Karnaugh map as follows:

00 00 01 D3D2 11 10 1 0 X 1

01 0 1 X 1

D1D0 11 10 1 0 X X 1 1 X X

The resulting reduced Boolean expression is:

1998-2007, C. J. Kikkert, James Cook University

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d = D3 + D1D0/ + D2/D0/ + D2/D1 + D2D1/ D0 To realise this with NAND gates, NOR gates and inverters, De Morgans theorem is applied to this expression and results in: d = (D3/ (D1D0/ ) / (D2/D0/ ) / (D2/D1) / (D2D1/ D0) /) / This requires 3 two input NAND gates, a three input NAND gate and a five input NAND gate, thus requiring three 7400 series packages. (with one quarter of one package and tho thirds of another package not being used.) Alternately the output d/ can be realised as:

00 00 01 D3D2 11 10 1 0 X 1

01 0 1 X 1

D1D0 11 10 1 0 X X 1 1 X X

d/ = D2D1/D0/ + D2D1D0 + D3/D2/D1/D0 To realise this with NAND gates, NOR gates and inverters, De Morgans theorem is applied to this expression and results in: d = ((D2D1/D0/ ) / (D2D1D0) / (D3/D2/D1/D0) /)
//

This requires 3 three input NAND gates, a four input NAND gate and an inverter. By realising the inverter as a 4 input NAND gate, the circuit can be realised using two 7400 series packages. With the use of dont cares the realisation of d is different from the inverse of the d/ realisation. Both the d and d/ expressions are optimum. The use of dont cares significantly reduces the circuit complexity. To show the advantages of using a CPLD for this. Without the use of the dont cares, so that the display can indicate the more usual A, b, C, d, E, F for 10 to 15, at least 3 packages will be required per segment, ie 21 packages per display. For a 4 hexadecimal digit display, 84 packages are required. Each device is about 50 cent in reasonable quantities, making a total of $42 in ICs, These devices fit on a large PCB and require 640 plated through holes. The same function fits inside half of one of the $6 iM4A5-64/32 CPLDs used in our labs, requiring a very small PCB area and no plated through holes. It is however possible to use a 74LS47 MSI 7 segment decoder/driver IC for $1 per display.

1998-2007, C. J. Kikkert, James Cook University

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Example2: (Extra) A BCD to decade multiplexer is a logic circuit that has 4 binary inputs (ABCD) and has 10 binary outputs, (0 to 9), each corresponding to the value of the input as a binary number. For such a BDC to decade multiplexer, the input values A, B, C, D, E and F should never occur. We can thus use those locations as dont cares. This can most easily be shown on the Karnaugh map by noting the location of the decimal numbers, corresponding to each of the squares in the Karnaugh map as shown above. The numbers 10 to 15 correspond to dont cares for the decade multiplexer.

CD 00 01 11 10 00 01 AB 11 10 X 0 X 1 X X X X 0 0 0 0 0 0 0 0

In canonical sums, dont cares are included as an extra term in brackets with a d prefix. For example the output 9 of a BCD to decade decoder as shown above is written as: Output 9 = A,B,C,D (9) + d(10,11,12,13,14,15) And the corresponding reduced output is: Output 9 = AD If dont cares are not used, the output will be: Output 9 = A B/ C/ D . Clearly using dont cares results in a saving in gate count. Example 3: (Extra) Sometimes a single optimum solution cannot be obtained, as shown in the following example: F = (B/ C/ ) + (B D) + (C/ D) + (A C/ ) + (A B) + (B C) + (A/ C D/ ) + (A/ B/ D/ )

1998-2007, C. J. Kikkert, James Cook University

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CD 00 01 11 10 00 01 AB 11 10 1 1 1 1 1 0 1 0 1 0 1 1 0 1 1 1

This can be realised in one of three different ways: The first solution is: F = (B/ C/ ) + (A/ C D/ ) + (B D) + (B C) + (A C/ ) Which uses five minterms.

CD 00 01 11 10 00 01 AB 11 10
A better solution is:

1 0 1 1

1 1 1 1

0 1 1 0

1 1 1 0

CD 00 01 11 10 00 01 AB 11 10 1 1 1 1 1 0 1 0 1 0 1 1 0 1 1 1

F = (B/ C/ ) + (A/ C D/ ) + (B D) + (A B)

1998-2007, C. J. Kikkert, James Cook University

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Which uses only four minterms. By using De Morgans Theorem, this can be realised using three 2 input NAND gates, one 3 input NAND gate and one 4 input NAND gate. F = ((B/ C/ ) / (A/ C D/ ) / (B D) / (A B) / ) / For standard TTL there are two 4 input gates in one package, so that the minimum 2 package realisation requires the 3 input NAND gate to be realised using a 4 input NAND gate, with one input connected to logical 1.

A' C D' 1 B' C' B D A B F

A third solution is: F = (C/ D ) + (A/ B/ D/ ) + (B C) + (A C/ )

CD 00 01 11 10 00 01 AB 11 10 1 1 1 1 1 0 1 0 1 0 1 1 0 1 1 1

The circuit diagram for this realisation is the same complexity as that for the second solution except that the input variables are different. There is thus no real difference in hardware costs between the last two realisations. These last two realisations are both optimum. 5 and 6 Variable Karnaugh Maps (Extra) A four variable Karnaugh map is a two-dimensional map as a single plane. For more that 4 variables, either the Karnaugh maps have to be drawn as a three dimensional drawing, with several four variable Karnaugh maps as a series of stacked planes. The linking is done not only in each plane, but also between adjacent planes. It can be seen that this is quite difficult to visualise. It is easier to place the individual maps 1998-2007, C. J. Kikkert, James Cook University

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next to each other and do the linking between adjacent squares that way. It is probably the most convenient to simply repeat the maps in a planar arrangement as shown for the 5 variable Karnaugh map below:
CD AB

EF

Six variable Karnaugh map

DE 00 01 11 10 000 0 001 ABC 010 4 1 5 3 7 2 6 ABC 011 12 13 15 14 8 9 11 10

DE 00 01 11 10 100 16 17 19 18 101 20 21 23 22 111 28 29 31 30 110 24 25 27 26

Five variable Karnaugh map, planar arrangement. One must remember that for instance 0, 2, 16 and 18 can form a group of four adjacent locations. A 5 variable Karnaugh map is thus more difficult to use than a 4 variable one. For a 6 variable Karnaugh map, we have four 4 variable maps in a similar fashion to the maps for the 5 variable case. The linking for that is more difficult still. For a 6 variable Boolean Algebra reduction, a 6 Karnaugh map will still give a quicker solution than other techniques, like the Quine McClusky reduction.

Computer Based Reduction Methods (Extra)

It is extremely difficult to handle more than 6 variables in a Karnaugh map. If this is the case then other techniques, like the Quine McClusky reduction must then be used. For this course the simplest technique would be to write the Boolean Algebra equations in ABEL and then let the Lattice ispExpert software solve those equations.

1998-2007, C. J. Kikkert, James Cook University

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The reduced equations are included as part of the reports produced by the software. These equations can then be used to either program the EPLDs or to realise the function using say TTL. Quine-McClusky Reduction Method (Chapter 4.4 of Wakerley) The Quine McClusky method of reduction is an algorithm, which is very suitable for computer based implementation and can be applied to any number of variables. The main aims of including this material is firstly to give a fuller understanding of the Karnaugh mapping technique and secondly to give an understanding how the computer programs which do the reduction for EPLDs work. Part 1 Linking Canonical Sum terms. Step 1 Group the binary numbers representing the required output, like canonical sum, into groups with the same number of ones, ie according to index. Step 2 Compare the numbers from adjacent groups, if they differ in one bit only, replace that bit with an X and enter the resulting word in the next column. This column is again grouped according to index. This grouping corresponds to a linking of two adjacent squares in a Karnaugh map. Mark the numbers that have been used with an 9. Step 3 Repeat the process, assuming the x to be a new variable to be compared, until no further reduction can take place. This amounts to making loops of 4, 8 16 etc squares in the Karnaugh map. Dont cares are included in these columns indication the linking of the canonical sum terms. Example T = 0,2,6,7,8,10,12,14,15,41 +d(25,27) # 0 2 8 6 10 12 7 14 25 41 15 27 Column 1 000000 000010 001000 000110 001010 001100 000111 001110 011001 101001 001111 011011 U 9 9 9 9 9 9 9 9 9 9 9 # 0,2 0,8 2,6 2,10 8,10 8,12 6,7 6,14 10,14 12,14 7,15 14,15 25,27 Column 2 0000X0 00X000 000X10 00X010 0010X0 001X00 00011X 00X110 001X10 0011X0 00X111 00111X 0110X1 U 9 9 9 9 9 9 9 9 9 9 9 9

i.e. 6 variables are required. # 0,2,8,10 2,6,10,14 8,10,12,14 6,7,14,15 Column 3 00X0X0 00XX10 001XX0 00X11X U

1998-2007, C. J. Kikkert, James Cook University

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In this example no further merging can take place after the third column. The first column indicates single values. The second column contains loops with two canonical sum terms, the third column contains loops with three canonical sum terms. Part 2 Prime Implicant Table. Step 4 Form the Prime Implicant table using the words, which could not be reduced further, i.e. those entries in the table without a 9. Step 5 Select just sufficient Prime Implicants to cover all the variables and use this to write the reduced equations. # 41 25,27 0,2,8,10 2,6,10,14 8,10,12,14 6,7,14,15 0 2 6 7 8 10 12 14 15 41 X

X X

X X X X X

X X X

X X X

Table 1 Prime Implicant Table In this table we must have: 41 as that is the only linking that covers 41. 0,2,8,10 as that is the only linking that covers 0. 8,10,12,14 as that is the only linking that covers 12. 6,7,14,15 as that is the only linking that covers 7. As each required row is selected, mark the columns that are covered by that row. So for 41, draw a vertical line through 41. For 0,2,8,10 draw vertical lines through 0,2,8 and 10. As each required row is used, place a 9 . The linked terms containing dont cares are included as rows of this table, but the dont cares are not included in the columns. # 41 25,27 0,2,8,10 2,6,10,14 8,10,12,14 6,7,14,15 9 9 9 9 0 I I X I I I 2 I I X X I I 6 I I I X I X 7 I I I I I X 8 I I X I X I 10 I I X X X I 12 I I I I X I 14 I I I X X X 15 I I I I I X 41 X I I I I I

Table 2 Prime Implicant Table, after selecting the required linked terms. As a result 2,6,10,14 is not required, since 2, 6, 10, and 14 are already covered by the other terms in the table. As expected 25,27 is not required since that term only included dont cares.

1998-2007, C. J. Kikkert, James Cook University

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If the numbers are of the form # = FEDCBA, (i.e. A is the least significant bit and F is the most significant bit) the reduced logic function is: T = 41 + (0,2,8,10) + (8,10,12,14) + (6,7,14,15) T = (FE/ DC/ B/ A) + (F/ E/ C/ A/ ) + (F/ E/ DA/) + (F/ E/ CB) Covering all the required canonical sum terms is simple in this example. Sometimes a single optimum solution cannot be obtained. In those cases one has to make a choice and select one of several optimum minimisations. On pages 10 - 12 of these Lecture notes, an example is shown which gives two possible best realisations. The same two best realisations will result using a Quine-McClusky reduction.

Logic Optimisation
The compilers, which perform this type of logic reduction, perform well. Sometimes it is however necessary to obtain a particular reduction in order to ensure that a design still fits inside a PAL, GAL or CPLD. In particular a combined minimisation, where the prime-implicant table covers more than one output variable, can yield a smaller total gate count, at the expense of a more intensive reduction. With most of the compilers, one can optimise the reduction for either high speed or a minimum amount of hardware used. Sometimes a manually done reduction can be much more efficient than one achieved by the compiler. As a result one still needs to know how to do Karnaugh map reductions.

Using Compilers for the Reduction

Consider the BCD to Seven segment display on page 10. One can enter a truth table for all these outputs into the ispLever compiler. The truth table does not include any entries for the dont cares and is as follows: Truth_Table ([BCD] -> [a, b, c, d, e, f, g, h]) [0 ] -> [1, 1, 1, 1, 1, 1, 0]; [1 ] -> [0, 1, 1, 0, 0, 0, 0]; [2 ] -> [1, 1, 0, 1, 1, 0, 1]; [3 ] -> [1, 1, 1, 1, 0, 0, 1]; [4 ] -> [0, 1, 1, 0, 0, 1, 1]; [5 ] -> [1, 0, 1, 1, 0, 1, 1]; [6 ] -> [1, 0, 1, 1, 1, 1, 1]; [7 ] -> [1, 1, 1, 0, 0, 0, 0]; [8 ] -> [1, 1, 1, 1, 1, 1, 1]; [9 ] -> [1, 1, 1, 1, 0, 1, 1]; where BCD is the BCD number and a to h are the corresponding outputs. The above truth table is written in a form suitable for use in an ABEL program. Using this truth table as part of an ABEL program and then looking at the prefit equations in the ispLever software, shows the reduced equations as shown below.

1998-2007, C. J. Kikkert, James Cook University

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It can be seen that the expression for !d is realised by the compiler. The realisation matches the realisation for the zero values on the Karnaugh map shown on page 11 and the reduced Boolean Algebra equation produced as part of the Fitter Report is exactly the same as the equation for d/ shown on page 11. For VHDL a case statement is used: process(Hexin) begin LabSevSeg: case Hexin is -- need to have inverse of output coded here since the -- board displays include inverters. when X"0" => SevSegOut <= "1111110"; --0 when X"1" => SevSegOut <= "0110000"; --1 when X"2" => SevSegOut <= "1101101"; --2 when X"3" => SevSegOut <= "1111001"; --3 when X"4" => SevSegOut <= "0110011"; --4 when X"5" => SevSegOut <= "1011011"; --5 when X"6" => SevSegOut <= "1011111"; --6 when X"7" => SevSegOut <= "1110000"; --7 when X"8" => SevSegOut <= "1111111"; --8 when others => SevSegOut <= "-------"; --Dont Care end case LabSevSeg; end process;

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It is thus much easier to use the ispLever (or equivalent) software to minimise the Boolean algebra equations, than drawing 7 Karnaugh maps and doing 7 reductions as required for conventional Karnaugh Map reduction techniques. There are however situations where Karnaugh map reduction must be used.

1998-2007, C. J. Kikkert, James Cook University