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Vth Instability of MOSFETs with Advanced Gate Dielectrics [phD thesis]

Vth Instability of MOSFETs with Advanced Gate Dielectrics [phD thesis]

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Published by shenchen
The scaling of MOSFET is not only a geometric shrinkage, but also accompanied
by new materials and process technologies. The gate dielectric, as the most critical
component in a MOSFET transistor, is undergoing rapid and substantial changes
with the adoption of ultra-thin plasma-nitrided oxide, and more recently high-
κ dielectrics. The reliability physics of these new gate dielectric materials are
important and urgent tasks to the IC industry. One important aspect of the
transistor reliability is the threshold voltage instability, which causes degradation
of circuit performance, and in some cases, loss of functionality as well.
This thesis examines the dominant Vth instability mechanisms in two advanced
gate dielectric materials, namely the nitrided silicon oxide (or silicon oxynitride),
and the hafnium oxide. Negative bias temperature instability and charge trapping
phenomena in these two dielectric films are the focus of this study, and form the
main chunk of this thesis.
Since the accurate characterization of threshold voltage instabilities is a pre-
requisite of the desired study, much effort was spent on developing the fast Id
−Vg
measurement technique. The minimum measurement time for an Id
−Vg curve of
100 ns is achieved. The operation principle, circuit construction and sources of
errors of this technique are documented in detail. The fast measurement is shown
to be indispensable for accurate characterization of threshold instabilities in the
advanced gate dielectrics, due to the fast recovery of threshold voltage when stress
is removed.
With the accurate measurement technique established, the Vth degradation
mechanisms are studied in detail. In the case of oxynitride dielectric, the relative
importance of interface-state generation and charge trapping is currently under
debate in the community. Analytical and numerical calculations are performed on
each of the two theories, and compared to the extensive experimental data. It is
argued that for the oxynitride dielectric, hole trapping must be present along with the interface trap generation. More specifically, charge trapping is the dominant
mechanism giving rise to the fast transients in NBTI.
In the case of HfO2 dielectric, it is observed that two distinct charge trapping
components exists, with the slower component shows an unexpected dependence
on the frequency of the stress signal. A two-step charge trapping model, possibly
associated with the negative-U traps in HfO2 film, is proposed to explain the
observed frequency dependence. The faster charge trapping component, which
has large magnitude, is modeled with traditional charge trapping theories. The
obtained dynamic model of the fast charge trapping is used to predict its impact
on digital circuits. It is shown that different circuit topologies have very different
sensitivity to the instability of Vth .
The scaling of MOSFET is not only a geometric shrinkage, but also accompanied
by new materials and process technologies. The gate dielectric, as the most critical
component in a MOSFET transistor, is undergoing rapid and substantial changes
with the adoption of ultra-thin plasma-nitrided oxide, and more recently high-
κ dielectrics. The reliability physics of these new gate dielectric materials are
important and urgent tasks to the IC industry. One important aspect of the
transistor reliability is the threshold voltage instability, which causes degradation
of circuit performance, and in some cases, loss of functionality as well.
This thesis examines the dominant Vth instability mechanisms in two advanced
gate dielectric materials, namely the nitrided silicon oxide (or silicon oxynitride),
and the hafnium oxide. Negative bias temperature instability and charge trapping
phenomena in these two dielectric films are the focus of this study, and form the
main chunk of this thesis.
Since the accurate characterization of threshold voltage instabilities is a pre-
requisite of the desired study, much effort was spent on developing the fast Id
−Vg
measurement technique. The minimum measurement time for an Id
−Vg curve of
100 ns is achieved. The operation principle, circuit construction and sources of
errors of this technique are documented in detail. The fast measurement is shown
to be indispensable for accurate characterization of threshold instabilities in the
advanced gate dielectrics, due to the fast recovery of threshold voltage when stress
is removed.
With the accurate measurement technique established, the Vth degradation
mechanisms are studied in detail. In the case of oxynitride dielectric, the relative
importance of interface-state generation and charge trapping is currently under
debate in the community. Analytical and numerical calculations are performed on
each of the two theories, and compared to the extensive experimental data. It is
argued that for the oxynitride dielectric, hole trapping must be present along with the interface trap generation. More specifically, charge trapping is the dominant
mechanism giving rise to the fast transients in NBTI.
In the case of HfO2 dielectric, it is observed that two distinct charge trapping
components exists, with the slower component shows an unexpected dependence
on the frequency of the stress signal. A two-step charge trapping model, possibly
associated with the negative-U traps in HfO2 film, is proposed to explain the
observed frequency dependence. The faster charge trapping component, which
has large magnitude, is modeled with traditional charge trapping theories. The
obtained dynamic model of the fast charge trapping is used to predict its impact
on digital circuits. It is shown that different circuit topologies have very different
sensitivity to the instability of Vth .

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Published by: shenchen on Jul 24, 2009
Copyright:Attribution Non-commercial

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10/19/2011

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THRESHOLD VOLTAGE INSTABILITIESIN MOS TRANSISTORSWITH ADVANCED GATE DIELECTRICSSHEN CHEN
(B.Eng. (Hons.), NUS)
A THESIS SUBMITTEDFOR THE DEGREE OF DOCTOR OF PHILOSOPHYDEPARTMENT OF ELECTRICALAND COMPUTER ENGINEERINGNATIONAL UNIVERSITY OF SINGAPOREFEBRUARY 2008
 
To Sarah 
 
iii
Acknowledgement
After working on other projects for almost a year, I came back to my files onreliability study, to reconstruct my memory on the three years dedicated to it, andto write this thesis. Each graph now tells a story on the guidance, inspiration andsupport I received from many colleagues. Without their contribution, this studywould not reach the depth I had hoped.First of all, I would like to thank my supervisor, prof. Li Ming-Fu for bringingme to the field of transistor reliability study, and the liberal environment he createdin the group. It is difficult to imagine how little I could have done if prof. Lihad not encouraged me to attempt on those ideas seemingly beyond reach. Hedemonstrated to us how a researcher should be confident in his study; how theconfidence comes from the pursue of every detail and continual cross-checking; andhow one should be open-minded and actively seek criticism. Working with him hasbeen very much a character building process to me. I would like to thank Dr. YeoYee-Chia for the many inspiring discussions on a wide range of topics. It has beenvery beneficial to put things into perspective and see the big picture. It is sucha pleasure working with you. Prof. Ganesh Samudra and prof. Kwong Dim-Leeprovided many thoughtful suggestions to many of my manuscripts, to which I amvery grateful.I would like to thank Dr. Yu Hong-Yu, who was my mentor when I first joinedthe group. Many of research plans in the initial year was under his steering. Heprovided many invaluable advices on tackling the challenges in research. SimilarlyI owe debt to Dr. Hou Yong-Tian and Dr. Zhu Shi-Yang for their advices. Manyof the data in this work are results of collaborations with Ms. Yang Tian andMr. Wang Xin-Peng. Their incredible dedication to the project really set a stan-dard for all members in the group, and continually spurred me to work harder. Iwas great pleasure to have your collaboration and friendship. A few undergradu-

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