JOURNAL OF TELECOMMUNICATIONS, VOLUME 22, ISSUE 1, OCTOBER 2013
Design and Simulation of Wideband and Low Phase Noise UHF Synthesizer
M. Majdi, F. Hodjat Kashani
Design and simulation of a UHF wideband and low noise frequency synthesizer from 470 MHz to 860 MHz is presented. The proposed voltage controlled oscillator (VCO) in the phase lock loop (PLL) covers wide frequency bandwidth of 58% while phase noise performance has been optimized simultaneously, using parallel tuning diodes in the LC tank of modified Colpitts VCO. The result of the harmonic balance simulation shows an overall SSB phase noise less than -105 dBc/Hz at 10 KHz offset. The output power is more than 0dBm with maximum variation of 0.93 dB while using a high pass filter in the output.
Frequency Synthesizer, SSB phase noise, Voltage Controlled Oscillator (VCO), Resonator Circuit, phase lock loop (PLL).
The explosive growth of today’s telecommunication market has brought an increasing demand for high performance, low cost, low power consumption radio frequency circuits. Among all the RF blocks, the design of voltage-controlled oscillators (VCOs), which
generate the LO carrier signal, is a major challenge and thus has received the most attention in recent years, as evidenced by the large number of publications [1-9]. The LOs are usually a frequency-synthesizer based on a phase locked loop (PLL) as depicted in the
Fig. 1, in which the output oscillation signal is provided by a VCO. Due to the ever-increasing demand for bandwidth in communications, very stringent requirements are placed on the spectral purity of LOs, making the VCO design as a critical sub-circuit to the overall system performance. Some of digital video broadcasting (DVB) standards which are now spread throughout the world are operating in different parts of the UHF band. Therefore, in order to improve quality of service, RF unit components such as synthesizers should obtain appropriate spectral purity in desired bandwidth. The purpose of this paper is designing the low phase noise wideband UHF frequency synthesizer from 470 MHz to 860 MHz. The paper has been organized as follows: In section 2, UHF frequency synthesizer is designed. In this section, selecting resonator and oscillator structure and VCO topology are explained in detail. Then design and simulation of proposed VCO and proper loop filter are demonstrated. Finally simulation of UHF frequency synthesizer is presented
in section 3, some conclusions are offered.
In this paper, we are going to design the low phase noise UHF frequency synthesizer with the frequency range of 470MHz to 860MHz. So as to design the low noise wideband UHF frequency synthesizer, the
based fractional-N frequency synthesizer has been used which contains a low noise digital phase frequency detector (PFD),a precision charge pump ,a programmable reference divider and also the programmable N-fractional loop divider with the third-order
modulator. Designing VCO with the wideband structure considering the minimum output power variations along the band and also a minimum phase noise, designing an appropriate loop filter, choosing a suitable reference crystal with the minimum phase noise with the highest stability have been considered as important parts in designing of the proposed synthesizer .
ESIGNING THE VOLTAGE CONTROLLED OSCILLATOR
Each VCO contains three main parts. One of them is the active circuit which its main element is the transistor and it converts the dc power to the ac power by creating the negative resistance. The second
part is a load network which receives the generated ac
power and the third part is a resonator network which allows transmitting the generated power to the load only in its resonant frequency. In accordance with the vital VCO features such as the output power, phase noise characteristic and the required frequency bandwidth, the structure of the oscillator and its resonator circuit have been determined. The optimum design of the VCO and decreasing its phase noise level as one of the main sources of the PLL output phase noise plays a significant role in declining the phase noise level of synthesizer.
CTIVE DEVICE AND VARACTOR DIODE SELECTION
Fig. 1. Block diagram of PLL-based frequency synthesizers.
M. Majdi is with the Electrical Engineering Department of Islamic Azad University Tehran south branch.