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Summary notes from:Aendix A nthesis 
 
The Designer’s Guide to VHDL, 2
nd
Ed.
1
 
 Writing VHDL for Synthesis
MotivationCombinational Circuits atc xampesRTL for Finite State Machines
2
 
 Why do we care?
If the code is not synthesizable, then it canbe ver
inefficient
too slow too muchpower, may not be able to implement)
We can expect
optimization tools
to provide us,for
 speed, area, and possibly power.
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