ABSTRACT

UTSi (Ultra-Thin Silicon) on insulator technology has the potential of integrating digital, analog, RF and RF matching circuitry on a single chip. The technology is based on bulk CMOS VLSl technology with fully integrated passive components. UTSi CMOS technology provides high speed and superior RF performance transistors, high quality passive elements and excellent isolation due to the insulating substrate. In this paper, UTSi technology will be briefly reviewed and critical active device performance will be presented. Results show that UTSi CMOS process presents a possible road map for system-on-chip solution for wireless communication systems, especially in low power applications.

INTRODUCTION
Decreasing power consumption, migration toward smaller dimensions, desire to achieve high level of integration, and consumer-driven market are spurring the interest in Si-based technology. However, there are two basic limitations that can not be addressed through lithography improvements in standard CMOS process. The nonlinear parasitic capacitances between the MOSFET and substrate and the low resistivity substrate can not be eliminated from the bulk CMOS process. The nonlinear capacitances will degrade the linearity required for wireless systems. The low resistivity substrate results in strong coupling through the substrate and poor quality passive components. UTSi (Ultra Thin Silicon) CMOS technology has been developed to overcome these limitations.

UTSi technology is a CMOS process with roots in decades of government sponsored research. Recently, UTSi CMOS has been perfected, and can be manufactured in an unmodified CMOS fabrication facility [l]. Fig. 1 sketches cross sections of MOSFETs implemented in a submicron bulk CMOS and UTSi CMOS process. The basic transistor structures are the same except that wells, well contacts, isolated regions and substrate contacts are not required in the UTSi device. Unlike, other Silicon-On- Insulator (SOI) technologies, UTSi has a completely insulating substrate. The insulating substrate provides the required isolation to accommodate RF circuits, analog-to- digital converters and digital logic circuitry in addition to the good quality passive components [2]-[4].

In this paper, technology options for system-on-chip solutions will be assessed. UTSi CMOS process will briefly reviewed. The active device characteristics will be presented. The high frequency performance will be summarized. The potential application for RF-mixed mode will be also described.

TECHNOLOGY OPTIONS FOR RF SYSTEM-ON-CHIP SOLUTIONS

RF circuits are currently being commercially manufactured using four basic technologies. The technology options for RF wireless communications systems are Si bipolar, Si BiCMOS, GaAs and UTSi CMOS [ 5 ] . SOI and SiGe (Silicon Germanium) have recently generated a lot of interest and might be available in high volume production in the near future [6]-[9].

However, the traditional process technologies, Si and GaAs cannot be integrated since they are incompatible with each other. So, the complete integration solution must be implemented in either Si or GaAs. At the present time, no single technology can fulfill integration figure of merit. This integration figure of merit can be defined by isolation of RF, analog, and digital circuitry, and high Q passive components. Standard bulk Si substrates are characterized by their high losses. On the other hand, GaAs has the necessary substrate properties for complete integrated solutions.

Beyond integration, other limitations exist. Bipolar transistors, which are the RF elements in BiCMOS, do not scale well to low voltage and they are the most non-linear of all transistors, especially at low current. These features limit their usefulness in most digital wireless systems for which linearity is critical, like CDMA. Finally, bipolar processes are built with very low Si resistivity substrates, which makes them difficult when dealing with RF loss issues.

The depletion-mode GaAs process, which is mostly used for RF devices, is not suitable for low power digital logic. Digital logic are necessary for PLLs, RF switch logic and eventually for integrating A/D and D/A circuitry on the same substrate. Although, GaAs cost reduces rapidly and its manufacturability matures quickly, it has never been able to match the levels of Si CMOS.

These factors require the introduction of a version of Si CMOS that offers high performance RF along with high speed, low power digital and mixed-signal capabilities supplemented with integrated high Q passive components. This solution would be ideally on a low loss, nondispersive dielectric substrate that eliminates the parasitics and coupling among the different components located on the same integrated circuit. The question then returns to which substrate to use, since most CMOS processes are fundamentally similar.

SIMOX consists of a thin silicon layer on a thin silicon dioxide layer, about 0.1 or 0.2 pm thickness, all prepared by high dose oxygen ion implantation and high temperature anneals of a standard Si wafer. Bonded wafers, often called BESOI, consist of a thin silicon layer on a thicker silicon dioxide layer, about 1 or 2 pm, resulting from bonding two oxide coated wafers together, then grinding and etching one of the wafers to result in the desired final Si film thickness [3]. It is clear that SIMOX and BESOI are silicon layers on a relatively thin silicon dioxide layer, which is transparent to RF energy. At high frequency, the electric field penetrates the thin silicon dioxide layer. Thus, RF losses, from the underlying substrate, are not eliminated. Moreover, silicon dioxide is a strong thermal insulator, varies about 0.01 Wkm-K, and can cause thermal and degradation of device performance, which must be taken into consideration.

SIMOX material has a thin insulator, which increases RF coupling but reduces thermal effects; bonded Si material has a thicker insulator, which increases thermal effects while slightly reducing RF coupling. UTSi CMOS technology has been developed to overcome these limitations and to meet the requirements for system-on-chip solution.

UTSI TECHNOLOGY
UTSi technology is a CMOS process with roots in decades of government sponsored research. Recently, UTSi CMOS has been perfected, and can be manufactured in an unmodified CMOS fabrication facility. Fig. 1 sketch cross sections of MOSFETs implemented in submicron bulk CMOS and UTSI CMOS processes. The basic transistor structures are the same except that wells, well contacts, isolated regions and substrate contacts are not required in the UTSi device. Unlike, other Silicon-On- Insulator (SOI) technologies, UTSi has a completely insulating substrate.

UTSi CMOS is a high quality silicon layer, 100 nm thick, on a pure sapphire substrate. The process starts with standard epitaxial deposition of silicon on R-plane sapphire, followed by a medium dose Si implantation, then low and modest temperature anneals summarizes. Finally, Si film thickness is controlled by oxidation and strip [l]. Solid-phase epitaxy (SPE) regrows the defect-free silicon downward from the surface, removing the defects and resulting in high effective mobility. UTSi CMOS process includes LOCOS isolation, dual doped polycide gates with lightly doped drains, poly-poly capacitors, ion implanted resistors (in the 100 nm thick Si layer), and three levels of Al-Si-Cu metal. Gate oxide thickness is 10 nm and minimum drawn gate length is 0.5 pm. Four threshold adjust implant masks result in six threshold voltages. Table I summarizes different device types and their dc characteristics. Unimplanted transistors (IN) result in intrinsic (0 V) threshold devices. Device manufacturing on a standard CMOS line with standard CMOS process conditions.

TRANSISTOR PERFORMANCE
The DC characteristics of intrinsic (IN) UTSi CMOS are shown in Fig. 2 and Fig. 3. The low carrier life time in UTSi technology, about 1 nsec, and fully depleted transistor result in superior performance compare to other SOI technologies. Moreover, the very low diffusivity of dopants in the crystalline alumina substrate prevents dopant loss to the underlying dielectric, eliminating one of the major causes of threshold voltage variation. The fully depleted operation improves the low-voltage performance, especially when compared to bipolar or standard CMOS transistors. Although, UTSi CMOS is based on sapphire, which has thermal conductivity similar to GaAs, about 0.42 Wkm-K, thermal effects are not seen in UTSi CMOS, which also improves performance.

RF characteristics
The gain and h21 are plotted in Fig. 4 for IN 0.5 m multifinger UTSi CMOS ( W/L = 250 m 0.5 m) at Vds and Ids equals to 2.5 V and 15 mA, respectively. The transistor has the following properties: finger width less than 20 mm, oxide thickness tox of 100 A and polycide sheet resistance of 8 ohm/square. The f T and fmax of the UTSi MOSFET equal to 17 GHz and 50 GHz, respectively. The high fT value for UTSi CMOS compared to standard bulk CMOS is due to the elimination of the nonlinear parasitic drain and source to bulk capacitors and the fully depleted nature of UTSi transistors.

The change in fT and fmax with vgs at different vds is shown in Fig. 5 and 6. These measured data shows that fT and fmax equals to 14 GHz and 40 GHz, respectively, at Vds= 1 V and Vgs= 0.35V. This depicts that UTSi CMOS is suitable for low power operation.

Fig. 7 presents the noise figure and maximum gain of IN and NL UTSi MOSFET transistors ( W L = 250 p d 0 . 5 mm) at 5 mA drain current versus frequency. The maximum gain for both transistors is the same and equal to 12 dB at 2 GHz. The IN and NL MOSFET transistors have of noise figure Fmin 0.55 and 0.6 dB at 2 Ghz. The low noise charasteristics in UTSi CMOS can be explained by the stressed thin film silicon. The effect of the stress is to make the ellipsoids of constant-energy surfaces in the vertical direction, perpendicular to the channel, be of lower energy than the other two ellipsoids. Thus, the carriers will tend to stay inside these constant-energy surfaces, and if they start hoping from one elipsoid to another, it will be largely in the vertical direction. Therefore, if the current flow is in the horizontal direction, parallel to the channel, these vertical hopping, inter-valley scattering, do not change the carrier momentum in the direction of the current and thus render the stressed Si thin film less noisy than bulk silicon at high fields [lo].

One of the most striking features of UTSi CMOS transistors is their extremely high linearity for RF mixing operation. Fig. 8 presents the measured output third-order intercept point of IN 250, 500, 1000 x 0.5 pm FET at Vds = 3V and 2GHz frequency. UTSi CMOS exhibits a value and 1,&0 d. This can be of 23 dBm at V,&v explained by the small variation in the input capacitance with input voltage compared to other FET technologies due to the reduction of gate to bulk capacitance, the superior square law characteristics of the UTSi transistor in addition to the reasons previously mentioned for high fmaX.

The aforementioned data is consistent with the RF transistor performance required for wireless applications. They also show that UTSi technology provide the state of the art RF CMOS transistor.

AC characteristics
Wireless communication system-on-chip requires integration of digital, analog and RF mixed-signal CMOS. Fig. 9 shows unloaded ring oscillator propagation delay versus drain voltage for UTSi and bulk CMOS technologies. The 0.65 and 0.35 pm effective length UTSi offers lower delay than the 0.5 and 0.25 pm bulk, respectively. Moreover, the 0.35 pm effective length (Leff) UTSi CMOS technology presents high-speed performance over the entire voltage range from below 1V to above 3V. It is clear that the fully-depleted transistor operation and dielectric isolation give approximately 1.5 generations of speed advantage over bulk CMOS. In UTSi MOSFET, the bulk charge is minimal and fully eliminated in the accumulation and depletion regions of the transistor, which makes the capacitance characteristics of UTSi CMOS the same at low and high frequencies.

In summary, UTSi CMOS is a version of Si CMOS that offers high performance RF transistor along with high speed, low power digital and mixed-signal capabilities, which can be supplemented with integrated high Q passive components [4]. This solution is implemented on a low loss, nondispersive sapphire dielectric substrate that eliminates the parasitics and coupling among the different components located on the same integrated circuit.

CONCLUSION
UTSi CMOS IC technology has been developed to provide the cost and performance requirements of future integrated system-on-chip solution for wireless communication systems. The R F transistor performance is consistent with wireless applications requirement. The fully-depleted transistor operation and dielectric isolation give approximately 1.5 generations of speed advantage over bulk CMOS. The insulating substrate and subsequently, the high quality on-chip passive component are ideal for wireless applications. Results show that the technology has potential applications for low power system-on-a-chip solutions.