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Libero IDE - Session 1

Libero IDE - Session 1

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Published by: pelotadetrapo2009 on Aug 13, 2009
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1
Libero™Integrated DesignEnvironment
Actel CorporationMountain View, CA –USA
©2005 Actel Corp.
2
LiberoIDEJuly, 2005
Outline
Session 1:Introduction to Actel productsLiberoIDE overview and design flowDesign entry
Session 2:Functional simulationSynthesis
Session 3:Place & Route
Session 4:Post-Layout simulationProgramming
 
2
Introduction to Actel Products
©2005 Actel Corp.
4
LiberoIDEJuly, 2005
Actel Commercial Product Spectrum
Markets
Density
CPLDEquivalentEconomyFPGAFullFeaturedFPGA
eX
250 MHz
 
eX
250 MHz
Axcelerator 
>500MHz
 
Axcelerator 
>500MHz
ProASIC
PLUS
150MHz
 
ProASIC
PLUS
150MHz
3,00010,000100,0001M2MProASIC
100 MHZ
 
ProASIC
100 MHZ
SX-A
250 MHz
 
SX-A
250 MHz
 
3
©2005 Actel Corp.
5
LiberoIDEJuly, 2005
FPGA Technologies Compared
SRAM6TFlash1TAntifuse
ReprogrammableBest of Both WorldsReprogrammable& NonvolatileNonvolatile
©2005 Actel Corp.
6
LiberoIDEJuly, 2005
Flash Product Offering
Benefits of flash FPGA technology
Lowest power in its class
In-system programmable
Non-volatile
Single-chip
Lowest system cost
ProductK Gates Max I/OLeading featuresProASIC475 440 ISP, 2P-RAM/FIFO, FlashLock, Mixed 2.5V/3.3 I/OProASIC
PLUS
1000 712 ISP, 2P-RAM/FIFO, PLLs, LVPECL, FlashLock
 
ProductK Gates Max I/OLeading featuresProASIC475 440 ISP, 2P-RAM/FIFO, FlashLock, Mixed 2.5V/3.3 I/OProASIC
PLUS
1000 712 ISP, 2P-RAM/FIFO, PLLs, LVPECL, FlashLock

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