ALU

Arithmetic & logic

unit

Names
Belal Atef
.Seat no
Bahaa Alsayed
.Seat no
Eslam
.Seta no
Eihab
.Seat no
Khaled elmsiry
.Seat no
Hassan Elsayed

Seat no.191
Hassan Mahmoud
.Seat no
Hamza Shokry
.Seat no
Hossam Mohamed
.Seat no
Hassan abd elrahman
.Seat no

Introduction general
ALU Stands for "Arithmetic Logic
Unit." An ALU is an integrated circuit
within a CPU or GPU that performs
arithmetic and logic operations.
Arithmetic instructions include
addition, subtraction, and shifting
operations, while logic instructions
include BOOLEAN comparisons, such as
AND, OR, XOR, and NOT operations.
ALUs are designed to perform integer
calculations. Therefore, besides adding
and subtracting numbers, ALUs often
handle the multiplication of two
integers, since the result is also an
integer. However, ALUs typically do
not perform division operations, since
the result may be a fraction, or a

"floating point" number. Instead,

division operations are usually handled
by the floating-point unit (FPU), which
also performs other non-integer
calculations.
While the ALU is a fundamental
component of all processors, the design
and function of an ALU may vary
between different processor models.
For example, some ALUs only perform
integer calculations, while others are
designed to handle floating point
operations as well. Some processors
contain a single ALU, while others
include several arithmetic logic units
that work together to perform
calculations. Regardless of the way an
ALU is designed, its primary job is to
handle integer operations. Therefore, a
computer's integer performance is tied
directly to the processing speed of the
ALU.

The CPU is responsible for conducting all

operations
Arithmetic
Logical (such as OR, AND, XOR) in computers,
also conducting comparison to see the result of
logical comparisons, namely: (greater than and less
addition, subtraction and division multiplication) )
note that the unit only one process uses a
combination As for other operations such as
subtraction is the process of collecting and beatings
are the equivalent of the collection several times
and division operations are
Than and equal to or equal to) and derivatives of
these comparisons, as well as it provides
The possibility of temporarily storing information
in addition to the possibility of addressing
Information. It gives its output depending on the
.decision taken inside
Since all processing operations are limited to two
types of operations either
The unit arithmetic and logic unit of the
implementation of the Execution Unit. They
receive commands from the console Control Unit
to execute the stored
.Actually implementing instructions
Any matter required to be addressed, and we can
say that this is the unit that
Be Arithmetic or be logical, this unit is capable of
treating

In the instruction register (Instruction Register) are

implemented then give
The result, which is usually stored in the main
memory RAM and use is
Other

registers

to

complete

its

work.

OUR ALU
Our ALU is a simple arithmetic & logic
unit that performs about 24 functions
for four bit numbers
and supports more additional functions
.that we care about
User can deal with our ALU by some
direct selections for the required
.functions that will be done
inputs of ALU are performed as
eight switches ,four for each 4bit
number , each switch takes the value of
.(one or zero ( On or Off
Outputs of ALU are performed as
LEDs that takes the value of one or
.( zero (On or Off
Our ALU be able to generate the
:following four flags

a.Carry and Borrow Flag to be set on carry

(addition) or borrow (subtraction)
operations.
b. Sign Flag to be set when the resulting
number is negative (2's complement only).
c. Zero Flag to be set if the resulting
number is zero.
d. Overflow Flag to be set if the two most
significant carry outputs are not equal

The objective of the project:

The project is being implemented at the lowest cost
and the required speed and quality in less time.

Action Steps:
1- business perceptions and theoretical planning for
the implementation of the project.
2 -Choose the best visualization in order to be
implemented in the project.
3- Buy the required components of the design.
(Be careful purchase of the same type (Seamus or
Tuttle) until the be equal in speed to complete the
operations inside and even have the same delay so
that they work in perfect harmony and consensus,
which leads in turn to complete the required form
correctly).
4 -Use a rose test circuit is configured to the
experience of the components and the required
elements.
(Importance of the previous step to identify the
damaged components and take the necessary
precautions in the event of defects in components
and find out that there was external influence when
implementing such dump the (IC s )for the Volt or
any other problems and track the sources and try to
resolve before the kidney implementation of the
project)
5 -business simulation system for the project and
keep track of all the stages and ensure his safety

before the completion of the implementation

process.
6- Business test basic circuits in the project on a
rose testing to ensure the completion of required
practically properly before the implementation of
any other step.
7- After the completion of the process are woven
draw the schematic and review and ensure the
safety of implementation.
8- Print board.
9 -production process by soldering components
(after testing).
10 -test board the full practice with the completion
of the process of tracking to make sure the correct
results and work properly.
(During print board and production plan is working
again as an alternative in the event of mistakes in
anticipation and Avoid to any malfunction and the
rest of steps are performed on alternative plan in
case the lack of success of the first).

:The theory of work

:(ALU )
Is a circuit carrying out certain tasks or some
Operations on inputs by introducing some of the
codes used in process control are required
.implementation
(Codes are attached to their own Partial)
the codes is inserted through the keys for each of
.the main circuits
are greeted output on the display units(leds or 7
.(segment
Because that the operations required hold them
many relatively, it was necessary that the process is
shorthand for the process in the form of a set of
codes, for ease of dealing with taking into account
that have the space or the size of the project as
small as possible so it was shortened to
.departments is essential

Functions (all functions will

(be done for 4bit numbers
1. Addition of two 4-bit data
2. Addition with Carry of two 4-bit data
3. Subtraction of two 4-bit data
4. Subtraction with Borrow of two 4-bit data
5. Incrementing the input data
6. Decrementing the input data
7. Integer Multiplication of two 4-bit input
data (resulting in 8-bit outputs)
8. Integer Division of an 4-bit input data by a
2-bit input data (resulting in 4
quotient output bits and an extra 2 remainder
bits)

9. Shifting: Shifting Operations including of

the input data:
i. Ordinary Shift Right and Left with carry
flag.
ii. Arithmetic Shift Right and Left with carry
flag.
iii. Circular Shift Right and Left with carry
flag.
iv. Ordinary Shift Right and Left through carry
flag.
v. Arithmetic Shift Right and Left through
carry flag.
vi. Circular Shift Right and Left through carry
flag.
10. Transferring and Displaying of data.
11. First Complement of the input data.
12. Second Complement of the input data.

13. Negation the input data.

14. BCD Addition of the input data.
.BCD Subtraction of the input data .15

:Summarize the above

Inputs and outputs

The inputs to the ALU are the data to be
operated on (called operands) and a code
from the control unit indicating which
operation to perform. Its output is the
result of the computation. One thing
designers must keep in mind is whether the
ALU will operate on big-endian or littleendian numbers.
In many designs, the ALU also takes or
generates inputs or outputs a set of
condition codes from or to a status
register. These codes are used to indicate
cases such as carry-in or carry-out,
overflow, divide-by-zero, etc.
A floating-point unit also performs
arithmetic operations between two values,

but they do so for numbers in floatingpoint representation, which is much more

complicated than the two's complement
representation used in a typical ALU. In
order to do these calculations, a FPU has
several complex circuits built-in, including
some internal ALUs.
In modern practice, engineers typically
refer to the ALU as the circuit that
performs integer arithmetic operations
(like two's complement and BCD).
Circuits that calculate more complex
formats like floating point, complex
numbers, etc. usually receive a more
specific name such as FPU.

Classification
:of functions
in our ALU we classified all functions into
five main classaes

:the main circuits

.The addition circuit 1
.The multiplication and division circuit - 2
.The shifting circuit 3
.The conversion circuit - 4
5- The logic circuit.
To find out the basic circuit, it must be defined and
functions performed by other private information.

adder
it performs these functions
1. Addition of two 4-bit data
2. Addition with Carry of two 4-bit data
3. Subtraction of two 4-bit data
4. Subtraction with Borrow of two 4-bit
data
5. Incrementing the input data
6. Decrementing the input data
10. First Complement of the input data
11. Second Complement of the input data
12. Negation the input data.

13. BCD Addition of the input data

BCD Subtraction of the input data .14

Truth Table of these operations:

4-Bit Addition Without Carry In
A3 A2 A1 A0 B3 B2 B1
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110

B0

CO

2
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101

0111
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001

1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

10110
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000

4-Bit Addition With Carry In

Ci
A3 A2 A1 A0 B3 B2
n

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111

B1

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110

B0

CO

3 2 1 0
00110
00111
01000
01001
01010
01010
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0111
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001

1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

10111
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001

Subtraction Without Borrow

A3

A2

A1

0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
1000

A0

B3

B2

B1

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000

B0

S3 S2 S1 S0
00101
00100
00011
00010
00001
00000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
00110
00101
00100
00011
00010
00001
00000
10001
10010
10011
10100
10101
10110
10111
11000
11001
00111
00110
00101
00100
00011
00010
00001
00000
10001
10010
10011
10100
10101
10110
10111
11000
01000

1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001

0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

00111
00110
00101
00100
00011
00010
00001
00000
10001
10010
10011
10100
10101
10110
10111
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
10001
10010
10011
10100
10101
10110

Subtraction With Borrow

Bin
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

A3

A2

A1

0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0110
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
1000

A0

B3

B2

B1

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000

B0

B S3 S2 S1 S0
00100
00011
00010
00001
00000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
00101
00100
00011
00010
00001
00000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
00110
00101
00100
00011
00010
00001
00001
10001
10010
10011
10100
10101
10110
10111
11000
11001
01010

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001

0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

00110
00101
00100
00011
00010
00001
00000
10001
10010
10011
10100
10101
10110
10111
11000
01000
00111
00110
00101
00100
00011
00010
00001
00000
10001
10010
10011
10100
10101
10110
10111

Logic Operations
A
3

A
2

A
1

A
0

B
3

B
2

B
1

0101

0000

0101

0001

0101

0010

0101

0011

0101

0100

0101

0101

0101

0110

0101

0111

0101

1000

0101

1001

0101

1010

0101

1011

0101

1100

0101

1101

0101

1110

0101

1111

0110

0000

0110

0001

0110

0010

0110

0011

0110

0100

0110

0101

0110

0110

0110

0111

B
0

AN
D

NAN
D

000
0
000
1
000
0
000
1
010
0
010
1
010
0
010
1
000
0
000
1
000
0
000
1
010
0
010
1
010
0
010
1
000
0
000
0
001
0
001
0
010
0
010
0
011
0
011

111
1
111
0
111
1
111
0
101
1
101
0
101
1
101
0
111
1
111
0
111
1
111
0
101
1
101
0
101
1
101
0
111
1
111
1
110
1
110
1
101
1
101
1
100
1
100

OR

NO
R

XOR

010
1
010
1
011
1
011
1
010
1
010
1
011
1
011
1
110
1
110
1
111
1
111
1
110
1
110
1
111
1
111
1
011
0
011
1
011
0
011
1
011
0
011
1
011
0
011

101
0
101
0
100
0
100
0
101
0
101
0
100
0
100
0
001
0
001
0
000
0
000
0
001
0
001
0
000
0
000
0
100
1
100
0
100
1
100
0
100
1
100
0
100
1
100

010
1
010
0
011
1
011
0
000
1
000
0
001
1
001
1
110
1
110
0
111
1
110
0
100
1
100
0
101
1
101
0
011
0
011
1
010
0
010
1
001
0
001
1
000
0
000

XNOR
1010
1011
1000
1001
1110
1111
1100
1100
0010
0011
0000
0011
0110
0111
0100
0101
1001
1000
1011
1010
1101
1100
1111
1110

NO
T
"A
"
101
0
101
0
101
0
101
0
101
0
101
0
101
0
101
0
101
0
101
0
101
0
101
0
101
0
101
0
101
0
101
0
100
1
100
1
100
1
100
1
100
1
100
1
100
1
100

0110

1000

0110

1001

0110

1010

0110

1011

0110

1100

0110

1101

0110

1110

0110

1111

0111

0000

0111

0001

0111

0010

0111

0011

0111

0100

0111

0101

0111

0110

0111

0111

0111

1000

0111

1001

0111

1010

0111

1011

0111

1100

0111

1101

0111

1110

0111

1111

1000

0000

1000

0001

0
000
0
000
0
001
0
001
0
010
0
010
0
011
0
011
0
000
0
000
1
001
0
001
1
010
0
010
1
011
0
011
1
000
0
000
1
001
0
001
1
010
0
010
1
011
0
011
1
000
0
000
0

1
111
1
111
1
110
1
110
1
101
1
101
1
100
1
100
1
111
1
111
0
110
1
110
0
101
1
101
0
100
1
100
0
111
1
111
0
110
1
110
0
101
1
101
0
100
1
100
0
111
1
111
1

1
111
0
111
1
111
0
111
1
111
0
111
1
111
0
111
1
011
1
011
1
011
1
011
1
011
1
011
1
011
1
011
1
111
1
111
1
111
1
111
1
111
1
111
1
111
1
111
1
100
0
100
1

0
000
1
000
0
000
1
000
0
000
1
000
0
000
1
000
0
100
0
100
0
100
0
100
0
100
0
100
0
100
0
100
0
000
0
000
0
000
0
000
0
000
0
000
0
000
0
000
0
011
1
011
0

1
111
0
111
1
110
0
110
1
101
0
101
1
100
0
100
1
011
1
011
0
010
1
010
0
001
1
001
0
000
1
000
0
111
1
111
0
110
1
110
0
100
0
101
0
100
1
100
0
100
0
100
1

0001
0000
0011
0010
0101
0100
0111
0110
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0111
0101
0110
0111
0111
0110

1
100
1
100
1
100
1
100
1
100
1
100
1
100
1
100
1
100
0
100
0
100
0
100
0
100
0
100
0
100
0
100
0
100
0
100
0
100
0
100
0
100
0
100
0
100
0
100
0
011
1
011
1

1000

0010

1000

0011

1000

0100

1000

0101

1000

0110

1000

0111

1000

1000

1000

1001

1000

1010

1000

1011

1000

1100

1000

1101

1000

1110

1000

1111

000
0
000
0
000
0
000
0
000
0
000
0
100
0
100
0
100
0
100
0
100
0
100
0
100
0
100
0

111
1
111
1
111
1
111
1
111
1
111
1
011
1
011
1
011
1
011
1
011
1
011
1
011
1
011
1

101
0
101
1
110
0
110
1
111
0
111
1
100
0
100
1
101
0
101
1
110
0
110
1
111
0
111
1

010
1
010
0
001
1
001
0
000
1
000
0
011
1
011
0
010
1
010
0
001
1
001
0
000
1
000
0

101
0
101
1
110
0
110
1
111
0
111
1
000
0
000
1
001
0
001
1
010
0
010
1
011
0
011
1

0101
0100
0011
0010
0001
0000
1111
1110
1101
1100
1011
1010
1001
1000

011
1
011
1
011
1
011
1
011
1
011
1
011
1
011
1
011
1
011
1
011
1
011
1
011
1
011
1

Data Negation = 2's Complement

t
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Output
0000
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001

t
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Output
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000

1's Complement

Incrementing the data

t
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Output
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
10000

t
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Output
11111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110

Decrementing the data

:Ingredients
:Illustration
(Blocks)
(tracing)
:Notes
:Suggestions
:Problems
:Solutions

The multiplication and division - 2

:circuit
:Definition
it is a circuit dedicated solely to multiply two
numbers or divide two numbers
:Operations carried out by the circuit
Integer Multiplication of two 4-bit input data -1
((resulting in 8-bit outputs
Integer Division of an 4-bit input data by a 2-bit -2
input data (resulting in 4 quotient output bits and an
(extra 2 remainder bits
:Ingredients
:Illustration
(Blocks)
(tracing)
:Notes
:Suggestions
:Problems
:Solutions

:The shifting circuit 3

:Definition
It is used to complete the circuit and
.implementation shifting operations of all types
Shifting Operations including of the input data
1- Ordinary Shift Right and Left with carry flag
2- Arithmetic Shift Right and Left with carry flag
3- Circular Shift Right and Left with carry flag
4- Ordinary Shift Right and Left through carry flag
5- Arithmetic Shift Right and Left through carry
flag
Circular Shift Right and Left through carry flag -6
:Ingredients
:Illustration
(Blocks)
(tracing)
:Notes
:Suggestions
:Problems
:Solutions

:The conversion circuit - 4

:Definition
A circuit used for the completion of various
.conversion processes for codes
:Conversion types
BCD to Binary conversion circuit for the input -1
data and vice versa
Gray code to Binary conversion circuit of the -2
input data and vice versa
Excess-3 to Binary conversion circuit of the input-3
data and vice versa

Gray Code
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000

Conversion From Binary To Grey Code & Vice Versa

Binary Number
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Gray Code
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000

Conversions From Binary To Excess-3 & Vice Versa

Binary Number
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101

Excess-3 Code
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
xxx
xxx
xxx
xxx

Binary Number
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

1110
1111

xxx
xxx

Excess-3 Code
0011
0100
0101
0110
0111
1000
1001
1010
1011

Binary Number
0000
0001
0010
0011
0100
0101
0110
0111
1000

()
:Ingredients
:Illustration
(Blocks)
(tracing)
:Notes
:Suggestions
:Problems
:Solutions

:The logic circuit-5

:Definition
:It is a circuit that used in logic operation
:Logic operation types
ANDing of input data-1
ORing of input data -2
XORing of input data -3
XNORing of input data -4
INVERTing of input data -5

NANDing of input data -6

NORing of input data -7
:Ingredients
:Illustration
(Blocks)
(tracing)
:Notes
:Suggestions
:Problems
:Solutions

General problems:
We had some problems during
this project like:
1.
2.

We didn't

When we did a simulation

for the final circuit on

Proteus .. it hanged and

stopped work.
3. The final circuit was so big
as we will drill about 2000
holes in the bored!!!
4. The final circuit was
bigger than the A4 paper.
5.
Solutions: