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Question Bank CS1601

Question Bank CS1601

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Published by ainugiri

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Published by: ainugiri on Aug 19, 2009
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11/15/2012

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CS1601
 
Subject Name
 
Computer Architecture
 
Semester
I
Degree
 
ME
 
Branch
 
Computer Science
 
Staff Name
 
Dr. Hari T. S. Narayanan
 
Date of Update
 
1.10.08
 
Part
 
Unit
 
Group
 
No
 1A
2 & 3
1 1
Describe the three types of
instruction 
depe 
ndences 
with appropriate examples
 2A
2 & 3
1 2G
ive examples using assembly level code
segments for each of the three instruction
dependencies. No definitions required
 3A 1 1 3If a computer supports an address space of 4G,
how many bits are required f
or address register?
 4A 4 1 4
Draw
 
the memory hierarchy that is used in atypical desktop computer. List typical size and
performance values for each of these levels.
 5A 4 1 5
Compare
 
three cache mapping functions in terms
of
access speed 
and
cache mis 
s.
6A 5 2 1
Compare
 
coarse grain 
and
fine grain 
 multithreading with their performance trade-
offs.
 
7A 5 2 2
Why
Invalidation 
is preferred over
Write 
distribution 
? State exactly two reasons.
 8A 4 2 3What is the average rotational delay for a disk
sys
tem with 10000 RPM?
 9A 1 2 4
Describe the
relationship between
response 
 
time,
user 
time,
elapsed 
time, and
system 
time
in the context of a process.
 
10
 A 1 2 5
What are Big
Endian 
and
Small Endian 
 
representations
?
11
 A
2 & 3
3 1
Drawa 6
-
stage pipeli
ne with multiple Functional
Units
 
12
 A
2 & 3
3 2
Why
Read After Write (RAW) is not a problem
with extended ID (Issue & RO)?
 
13
 A
2 & 3
3 3
Describe
the three types of
instruction 
dependences 
with appropriate
examples
.
14
 A
2 & 3
3 4
Illustrate
Write Aft 
er Read 
and
Write After Write 
 
hazards
with appropriate
examples
.
15
 A
2 & 3
3 5
Compare
 
static 
scheduling of instructions with
dynamic 
scheduling.
 
16
 A
2 & 3
4 1
Describe the working
of branch predictionalgorithm using prediction buffer of size 1 bit.
 
 
17
 A
2 & 3
4 2
Provide an example to show that
data 
 
dependence 
by itself is not sufficient and
control 
dependence 
needs to be considered as well. Why
Data Flow 
and
Exceptional Behavior 
combinationis preferred over
Control 
and
Data 
Dependence
combination i
n scheduling instructions.
 
18
 A
2 & 3
4 3
Draw a 5
-
stage pipeline with multiple FunctionalUnits.
 
19
 A
2 & 3
4 4
Describe
Write After Read 
Hazard and
Write After Write 
Hazard.
 
20
 A
2 & 3
4 5
Explain Read After Write (RAW) with anappropriate example
 
21
 A
2 & 3
5 1What is the steady state best-case throughputfrom a pipelined architecture where each stagetakes 1 clock cycle of a 4 GHz clock? Give your
answer in number of instructions per second.
 
22
 A 4 5 2
Draw
the memory hierarchy that is used in a
t
ypical desktop computer. List typical size and
access speed for each of these levels
 
23
 A 4 5 3D
escribe cache direct mapping using an example.
For instance, a memory with 512 blocks and a
cache with 32 blocks.
 
24
 A 4 5 4A program accesses cache 4 million times duringits execution. How many of these accesses are
hits if the miss rate is 0.01%?
 
25
 A 4 5 5
A program includes 5 million instructions. On theaverage, each instruction takes 1.5 cycles if the
entire program were to be loaded into cache of a
c
omputer 1 GHz clock. If the program takes 8million CPU cycles to execute; how much
time
 
wasted spent in stalling
 
26
 A 4 6 1
A program accesses cache 4 million times during
its execution. The miss rate is 0.01%. If the CPU
stalls 2000 cycles for each cac
he miss, computethe number of misses
 
27
 A 5 6 2What are two different
shared memory 
 
arrangement used in MIMD architecture?
 
28
 A 5 6 3
Why shared
-
bus MIMD system is referred to as
symmetric multi
-
processor system? What is the
other common name for this
arrangement?
 
29
 A 1 6 4
Compare RISC and CISC architectures
 
30
 A
2 & 3
6 5
What is thebasic principle
behind Tomasulo’s
algorithm? Illustrate that with an example.
 
31
 A 4 7 1
List the essential memory requirements
.
Compare
the memory requirements of De
sktop,
Server, and Embedded Systems.
 
 
32
 A 4 7 2
Draw
the memory hierarchy that is used in atypical desktop computer. List size andperformance values for each of these levels.
 
33
 A 4 7 3
A program accesses cache 2 million times during
its execution. How
many of these accesses arehits if the miss rate is 0.025 %?
 
34
 A 4 7 4
A program includes 4 million instructions. On theaverage, each instruction takes 1.5 cycles if the
entire program were to be loaded into cache. If
the program takes 7 million CPU cy
cles to
execute; how many CPU cycles are spent in
stalling?
35
 A 4 7 5
Do we need cache replacement scheme fordirect mapping?
Justify
your choice.
 
36
 A 4 8 1
Compare
two Write Miss schemes
 
37
 A 4 8 2
Compare
 
Write Back 
and
Write Through 
 
objectively.
 
38
 A 1 8 3
What are bench
-
marks?
 
39
 A
2 & 3
8 4
In the 6
-
stage pipeline if there are threeconsecutive arithmetic instructions and if eacharithmetic instruction take 3 cycles then thethird instruction has to be stalled due to limited
number (2) of ALUs
. This is referred to as
Structural dependence
 
40
 A 4 8 5
Compare
Split cache 
and
Unified cache 
 
42
 
Part B
 
43
 B 1 1 1
i. Write program segments to multiply two
integer numbers that are in memory (A and B)
using different internal storage types (stack,
 
register
-
register, register
-
memory, and
accumulator). The result of this operation is to
be stored in memory. (4)
 
ii. Draw and describe 32 bit floating pointrepresentation (4)
 
iii. List the steps in converting a given decimal
number to a binary 32
-
bit fl
oating
-
point
representation. (4)
 
iv. Convert the following number to 32
-
bit
floating
-
point representation: 255.625. (4)
 

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