APPLICATION NOTE

75W SMPS with TEA1507 Quasi-

Resonant Flyback controller

Draft2 AN00047

Philips Semiconductors
TP97036.2/W97
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Abstract

This application note describes a 75W Switched Mode Power Supply (SMPS) for a typical Monitor or TV-
application based upon the TEA1507 Quasi-Resonant controller. The power supply is based on a Flyback
topology and operates in the critical conduction mode at various frequencies depending on the output load and
input voltage. The TEA1507 uses current mode (on-time) control. This concept allows a very high efficiency also
in low power mode as result of valley (zero/low voltage) switching. Depending on the component values it is
possible to perpetrate the supply in no-load condition.

© Philips Electronics N.V. 2000

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copy-
right owner.
The information presented in this document does not form part of any quotation or contract, is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial
or intellectual property rights.

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APPLICATION NOTE

75W SMPS with TEA1507 Quasi-

Resonant Flyback controller

Draft1 AN00047

Author(s):
J. Kleuskens
R. Kennis
Philips Semiconductors Systems Laboratory Eindhoven,
The Netherlands

Keywords
Flyback converter
Quasi-Resonant
Low power standby
Valley Switching
High efficiency

Number of pages: 39
Date: 2000-06-30

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Summary

TM
The TEA1507 controller is part of the GreenChip family. It is intended for off-line 90VAC-276VAC power supply
applications. The controller is optimized for a very high efficiency operation up to 90% utilizing an integrated
start-up current source, a special valley switching feature, a special standby VCO mode or standby burst mode
feature and low power consumption. The controller is equipped with many protection features, such as an
accurate Over Voltage Protection, Over Current Protection, Over Power Protection, Over Temperature
Protection, Demagnetization Sensing, Maximum and Minimum On Time Protection and Short Winding
Protection. Another feature is the programmable Soft Start at primary side.
This application note starts with the introduction of the main application features (chapter 1) followed by Quasi-
Resonant Flyback topology description in chapter 2. Functionality of the TEA1507 is descriped in chapter 3. In
chapter 4 the design of a typical universal range monitor supply (cookbook) is described in more detail with
some attached measurement results (chapter 5, EMI included). In the appendix a more detailed description of
the QR-waveforms are treated.

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CONTENTS

1. INTRODUCTION................................................................................................................................................... 6

2. QUASI-RESONANT FLYBACK TOPOLOGY ............................................................................................ 8

3. FUNCTIONAL IC DESCRIPTION ................................................................................................................. 11

3.1 Start-up sequence 
3.2 Multi mode operation  
3.3 Safe-Restart mode 
3.4 Protections  
3.4.1Demagnetization sensing 
3.4.2Over Voltage Protection  
3.4.3Over Current and Over Power Protection  
3.4.4Short Winding Protection  
3.4.5Minimum and maximum ‘on-time’ 
3.4.6Over Temperature protection  
3.4.7Mains dependent operation enabling level 
3.5 Burst mode Stand-by 
TM
3.6 Pin description GreenChip TEA1507  
4. DESIGN OF 75W UNIVERSAL RANGE MONITOR SUPPLY (COOKBOOK).............................. 19
4.1 Introduction to design  
4.2 Supply specification  
4.3 Numeric calculations of reference design  
4.3.1Dimensioning the key components  
4.3.2Protections  
4.3.3Burst mode stand-by 
4.4 Circuit diagram  
4.5 PCB design  
4.5.1Layout considerations 
4.5.2PCB layout  
4.5.3Parts list 
5. MAESUREMENTS ............................................................................................................................................. 31
5.1 Static performance 
5.1.1Switching frequency vs output power  
5.1.2Efficiency  
5.1.3Over Voltage Protection  
5.1.4Over Power Protection  
5.2 Dynamic performance  
5.2.1Start-up sequence 
5.2.2Load response 
5.2.3Line and switching ripple 
5.2.4Loop transfer function 
5.2.5EMI results  

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1. INTRODUCTION

TM
The GreenChip TEA1507 is a variable frequency SMPS controller designed for a Quasi-Resonant Flyback
converter operating directly from the rectified universal mains (see Figure 1). The topology is in particular suitable
for TV and Monitor Supplies. During nominal load it operates in a critical conduction mode including zero/low
voltage switching (ZVS/LVS). The ZVS/LVS is achieved by the resonant behavior of the voltage across the power
switch. This is also called the Quasi-Resonant mode. The Valley detection implemented in the controller ensures
this ZVS/LVS operation.
VLINE

VIN VOUT

CIN
NP
NS

VCC

1 Vcc Drain 8
CD
2 Gnd HVS 7

3 Ctrl Driver 6
CSS
4 Demag Sense 5

RSS
RSENSE

NVcc

Figure 1 Quasi-Resonant Flyback converter

The control method applied in the TEA1507 is known by the name ‘Current-mode control’ with the benefit of having
a good input line regulation. Control takes place by regulating the primary peak current that result in a frequency
change depending on the power stage. The input voltage and the output load influence the frequency. The IC
controls the turn-on moment of the power switch for ZVS/LVS operation by using the valley detection.
Feedback is provided by means of an opto-coupler, through which a good stabilization and good ripple suppression
can be obtained.

The controller provides two different types of stand-by possibilities. The first is Frequency Reduction to minimize
the switching losses at minimum output load. This feature enables stand-by power consumption below 3W and
needs no additional circuitry. A second alternative for stand-by power consumption below 1W is called Burst mode,
which needs only little additional circuitry.

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The key features of the TEA1507 are:

Distinctive features
• Operates from universal mains input 85VAC – 276VAC
• High level of integration leads to a very low external component count
• Soft (re)Start to prevent audible noise (ajustable)
• Leading Edge Blanking (LEB) for current sense noise immunity

Green features
• On-chip start-up current source, which is switched off after start-up
• Valley (zero/low voltage) switching for minimal switching losses
• Frequency Reduction at low power stand-by for improved system efficiency (power consumption < 3W)
• Burst mode operation for very low stand-by levels (power consumption <1W)

Protection features
• Safe-Restart mode for system fault conditions
• Mains dependent operation enabling level (Mlevel) (adjustable)
• Under Voltage Protection (UVLO) for foldback during overload
• Continuous mode protection by means of demagnetization detection
• Accurate Over Voltage Protection (OVP) over demag (adjustable)
• Cycle-by cycle Over Current Protection (OCP)
• Input voltage independent Over Power Protection (OPP)
• Short Winding Protection (SWP)
• Ton max Protection
• Over Temperature Protection (OTP)

These features enables an engineer to design a reliable and cost effective supply with a minimum number of
external components and the possibility to deal with requirements on minimum power consumption during stand-by
or other system idle modes.

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2. QUASI-RESONANT FLYBACK TOPOLOGY

The Quasi-Resonant Flyback topology is very appropriate for TV or monitor applications because this topology has
some important benefits compared to the “hard switching” fixed frequency Flyback topology. The efficiency can be
improved up to 90%, which results in lower power consumption. Referring to an important requirement of monitor
and/or TV supply it is possible to keep the input power below 75W, so that an additional PFC/MHR is not required.
This will save total supply costs.
The resonant behavior makes it possible to turn on the MOSFET when the voltage has reached zero (ZVS) or the
minimum value (LVS), which reduces the switch-on losses. Also the switch-off losses and the noise (dV/dt) will be
reduced by the resonance capacitor. Further more the QR Flyback runs at the borderline between discontinuous
(DCM) and continuous conduction mode (CCM). This means smaller peak and RMS currents in the circuit
compared to fixed frequency DCM Flyback, which results in a more efficient power conversion.

For a clear understanding of the Quasi-Resonant behavior it is possible to explain it by a simplified circuit diagram
of the Quasi-Resonant Flyback topology (see Figure 2). In this circuit diagram the secondary side is transferred to
the primary side and the transformer is replaced by an inductance LP. CD is the total drain capacitance including the
resonance capacitor CR, parasitic output capacitor COSS of the MOSFET and the winding capacitance CW of the
transformer. The turns ratio of the transformer is represented by n (NP/NS).

In the Quasi-Resonant mode each period can be divided into four different time intervals (see Figure 3), in
chronological order:
Interval 1: t0 < t < t1 primary stroke tPRIM = t1 – t0
Interval 2: t1 < t < t2 commutation time tCOM = t2 – t1
Interval 3: t2 < t < t3 secondary stroke tSEC = t3 – t2
Interval 4: t3 < t < t00 dead time tDEAD = t00 – t3

VIN V GATE

CIN IL LP COUT
n⋅V OUT
D VD
n⋅VOUT

Valley
V IN
VD
0
Magnetization Demagneti-
VGATE CD zation
IL
1 2 3 4
0
t0 t1 t2 t3 t 00
T

Figure 2 Basic circuit diagram Figure 3 QR waveforms

At the beginning of the first interval, the MOSFET is turned on and energy is stored in the transformer
(magnetization). At the end the MOSFET is switched off and the second interval starts.

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In the second interval the drain voltage will rise from almost zero to VIN+n⋅(VOUT +VF). VF is the forward voltage drop
of de diode that will be omitted from the equations from now on. The current will change its positive derivative,
corresponding to VIN/LP, to a negative derivative, corresponding to -n⋅VOUT /LP.
In the third interval the stored energy is transferred to the output, so the diode starts to conduct and the inductive
current IL will decrease. In other words the transformer will be demagnetized. When the inductive current has
become zero the next interval begins.
In the fourth interval the energy stored in the drain capacitor CD will start to resonate through the inductance LP.
The voltage and current waveforms are sinusoidal waveforms (see Figure 3) with an oscillation frequency of
approximately:

1 1
f OSC = ⋅ Equation 1
2π LP ⋅ C D

The drain voltage will drop from VIN+n⋅VOUT to VIN-n⋅VOUT.

Depending on the input voltage three situations has to be distinguished:

Situation Drain voltage at switch-on

1] VIN = n⋅VOUT ZVS
2] VIN < n⋅VOUT ZVS
3] VIN > n⋅VOUT LVS
Table 1 Zero Voltage Switching/Low Voltage Switching

In situation 1 the minimum drain voltage will be zero because VIN equals n⋅VOUT. The controller detects this
minimum and the MOSFET will be turned on again.
In situation 2 the input voltage is smaller than n⋅VOUT . The drain voltage wants to become negative, but the internal
body diode of the MOSFET starts conducting and the voltage is clamped at the negative voltage drop of this diode.
The controller detects this also as a valley and the MOSFET is turned on again. In both situations the switch-on
losses become zero, which is a big advantage of the Quasi-Resonant Flyback topology.
In the third situation the minimum drain voltage stays above zero (see Figure 3). The controller will detect this
valley and the switch-on losses will be very low even in this situation. For a more detailed description of all the
intervals see APPENDIX 2.

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Frequency behavior:
The frequency in the QR-mode is determined by the power stage and is not influenced by the controller (important
parameters are LP and CD). The frequency varies with the input voltage VIN and the output power POUT. If the
required output power increases more energy has to be stored in the transformer. This leads to longer magnetizing
tPRIM and demagnetizing tSEC times, which will decrease the frequency. See the frequency versus output power
characteristics of Figure 4. The frequency characteristic is not only output power but also input voltage dependent.
The higher the input voltage the higher the frequency will be.

P2
fMAX
VIN_MAX
switching
frequency

VIN_MIN
P1
fMIN

POUT_MIN POUT_MAX
power
Figure 4 QR frequency characteristics at different input voltages

Point P1 is the minimum frequency fMIN that occurs at the specified minimum input voltage and maximum output
power required by the application. Of course the minimum frequency has to be chosen above the audible limit
(>20kHz), but in principle the designer is free to choose the minimum frequency. The minimum frequency mainly
defines the primary inductance and because of this also the (core) size of the transformer. In applications operating
over the entire input voltage range (85Vac … 276Vac) it is not possible to choose a high minimum frequency
because in this case the frequency at minimum load and high input voltage (see point P2 in Figure 4) will end up
unacceptable high. See chapter 4 for a design example.

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3. FUNCTIONAL IC DESCRIPTION
This chapter describes the functionality of the QR Flyback controller and all the different modes in which the
controller can operate. It also describes how the features and protections are implemented in the controller. Table 3
in paragraph 3.6 shows an overview of the different functions behind each pin.

3.1 Start-up sequence

When the rectified line voltage VIN (via the center tap connected to pin 8) reaches the Mains dependent operation
level (Mlevel), the internal Mlevel switch will be opened and the start-up current source is enabled to charge the
capacitor at the VCC as shown in Figure 5. The soft start switch is closed when the Vcc reaches a level of 7V and
the Soft start capacitor CSS between the sense pin and the sense resistor is charged to 0.5V. Once the VCC
capacitor is charged to the start-up voltage (11V) the IC starts driving the MOSFET. Both internal current sources
are switched off after reaching this start-up voltage. Resistor RSS will discharge the soft start capacitor, such that
the peak current will slowly increase. This will overcome audible noise caused by magnetostriction in the
transformer. The time constant of the decreasing sense voltage (representing the increasing primary peak current)
can be adjusted by choosing a different C SS and/or RSS. To use the total soft start window RSS should be larger than
(VOCP = 0.5V divided by ISS = 60µA) 8kΩ to be sure it is charged to 0.5V. During start-up the VCC capacitor will be
discharged until the VCC winding voltage will take over charging the VCC capacitor.

VIN VCC V(start)=11V

Charging of VCC capacitor
taken over by the winding
Iin(Vcc) CVcc charged
by current ≈7V
VCC
1 8
CVcc τ = RSS⋅CSS
ISS
VSENSE
Mlevel

0.5V IL
soft start
VSENSE RSS IL
5 VOUT
CSS
+
VOCP
- RSENSE VGATE
2

Figure 5 Start-up sequence

3.2 Multi mode operation

The supply can run in four different modes depending on the output power:
1. Quasi-Resonant mode QR;
2. Maximum frequency mode MaxF;
3. Frequency reduction mode FR;
4. Minimum frequency mode MinF.

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The QR mode, described in the previous chapter, is used during normal operation, which gives a high efficiency.
The maximum frequency mode is not entered during nominal conditions (probably only at maximum input voltage
and low loads). But also in this mode it is still possible to take advantage of the reduced switch-on losses because
of valley switching.
If referring to most Monitor or TV application it is possible to distinguish two stages: Normal operation and Stand-by
operation. The relation between converter modes and load stages has to be as represented in the table below.

Supply mode Load stage

1. Quasi-Resonant mode A. Normal operation: POUT_MIN < POUT < POUT_MAX
2. Maximum Frequency mode not entered
3. Frequency Reduction mode
B. Stand-by operation: POUT = PSTAND-BY
4. Minimum Frequency mode
Table 2 Converter modes

frequency limit
foscH = 175 kHz
kH MinF RF QR

V VCO,start
switching
frequency

V VCO,max
foscL = 6 kHz

P OUT_MIN P OUT_MAX
power
Figure 6 Multi mode operation

The frequency reduction mode FR (also called VCO mode) is implemented to decrease the switching losses at low
output loads. In this way the efficiency at low output powers is increased, which enables power consumption
smaller than 3W during stand-by.
The voltage at the Sense pin determines where the frequency reduction starts. This fixed sense level of 75mV is
called VVCO,start (see Figure 6). This sense voltage controls the frequency of the internal oscillator over the range
between 75mV and 50mV (At sense level larger than 75mV the oscillator will run on maximum frequency foscH =
175kHz typically). At 50mV (VVCO,max) the frequency is reduced to the minimum level of 6kHz. The valley switching
is still active in this mode.

At sense levels below 50mV the minimum frequency will remain on 6kHz called MinF mode. When the required
output power decreases the controller will decrease the on-time, limited TON_MIN = 350ns. As a result of this low
frequency it is possible to run at very low loads without having any output regulation problems.

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3.3 Safe-Restart mode

This mode is introduced to prevent the components from getting destroyed during eventual system fault conditions.
This mode is also used for one operational issue, namely Burst mode. The Safe-Restart mode will be entered if it is
triggered by one of the following features:
• Over Voltage Protection;
• Short Winding Protection;
• Maximum ‘on time’ Protection;
• Over Temperature Protection;
• detecting a pulse for Burst mode;
• VCC reaching UVLO level.
When entering the Safe-Restart mode the output driver is immediately disabled and latched. The VCC winding will
not charge the VCC capacitor anymore and the VCC voltage will drop until UVLO is reached. To recharge the VCC
capacitor the internal current source (I(restart)(Vcc) ) will be switched on to initiate a new start-up sequence as
described in paragraph 3.1. This Safe-Restart mode will persist until the controller detects no faults or burst
triggers.

3.4 Protections

3.4.1 Demagnetization sensing

This feature guarantees discontinuous conduction mode operation in every situation. The function is an additional
protection feature against saturation of the transformer/inductor, damage of the components during initial start-up
and an overload of the output. The demag(netization) sensing is realised by an internal circuit that guards the
voltage (Vdemag) at pin 4 that is connected to Vcc winding by resistor R1. Figure 7 shows the circuit and the idealized
waveforms across this winding.

VGATE

1 Vcc Drain 8 Demagnetization

2 Gnd HVS 7

3 Ctrl Driver 6

NVcc
⋅VOUT
4 Demag Sense 5
VWINDING
NS
I(opp)(demag) I(ovp)(demag)

R1
0V

NVcc
D ⋅VIN
R2 NP
VCC
winding

Magnetization Comparator
Vdemag 0.7V threshold
Vdemag
0V -0.25V

Figure 7 Demagnetization sensing

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As long as the output diode is conducting (demagnetization of transformer), the winding voltage is positive. In this
case Vdemag is also positive and clamped at a level of 0.7V. The controller will force the driver output to stay off as
long as the voltage at pin 4 is positive and above 100mV. In other words an increase of the switching period is a
consequence of the demagnetization feature. After demagnetization the reflected output voltage at the auxiliary
winding goes down. When the voltage comparator threshold Vdemag < 100mV is reached the controller will wait for
valley detection to allow a new switching cycle. OVP and OPP are using the same pin. These two functions
determine the resistor value of R1 and R2. The following paragraph will describe these features.

3.4.2 Over Voltage Protection

The Over Voltage Protection ensures that the output voltage will remain below an adjustable level. This is realized
by sensing the reflected output voltage across the V CC winding via the current flowing into the Demag pin. This
voltage equals the output voltage corresponding to the turns ratio of the VCC winding and the secondary winding.
The maximum output voltage is set by the resistor value R1 that determines the current into the Demag pin. This
current is mirrored and compared to a threshold level of 60µA. When this is reached the OVP is triggered.
Choosing the maximum output voltage will determine the resistor R1 that is calculated by the following equation:

 N Vcc 
 ⋅ OVP  − Vclamp ,demag ( positive )
R1 =  s 
N
Equation 2
I ( ovp )( demag )
Where,
NVcc = VCC number of turns
NS = secondary number of turns
OVP = maximum output voltage
Vclamp,Demag(positive) = positive clamp voltage of Demag pin (0.7V)
I(ovp)(Demag) = current threshold of OVP protection (60µA)

After triggering the OVP the driver is disabled and the controller enters the Safe-Restart mode. This will stay as
long as the over voltage is present at the output.
The dashed line in Figure 7 shows the more practical waveform at the Vcc winding. The ringing is caused by the
leakage inductance of the transformer. To compensate this ringing (load dependent) the current into the Demag pin
is integrated over the demagnetization time. False triggering of the OVP is prevented in this way, which result in a
very accurate OVP.

3.4.3 Over Current and Over Power Protection

The maximum output power limitation needs some special attention when using a Quasi-Resonant converter.
The maximum primary peak current I L_peak does not only define the output power but also the input voltage because
the operating frequency is input voltage dependent (see equation below).

1
POUT _ MAX = η ⋅ ⋅ L P ⋅ I L _ peak 2 ⋅ f  Equation 3
2
Where f is input voltage depending

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1
f =
t PRIM + t COM + t SEC + t DEAD
 Equation 4
L P ⋅ I L _ peak
t PRIM =
V IN

The maximum output power will increase with the input voltage when the OCP level would be a fixed level. To
prevent over dimensioning of all the secondary power components an internal OCP compensation is used to get an
independent OPP level. This compensation is realized by sensing the input voltage level via the VCC winding. A
resistor is connected between this winding and the demag pin. During magnetization of the transformer the
reflected input voltage is present at this winding (see Figure 7). A negative current into this pin is used to
compensate the OCP level. Figure 8 shows the relation between the negative current and OCP level.

Internal OCP compensation

0.60
0.50
0.40
OCP level[V]

0.30
0.20
0.10
typical OCP level
0.00
-100 -75 -50 -25 0
Idemag [uA]

Figure 8 Internal OCP compensation

The current threshold level where the controller starts to compensate the OCP level is fixed at - 24µA. This
threshold level is used to set the external resistor value at the minimum input voltage. The OVP and OPP
protections are separated by means of a diode in series with R2 (see Figure 7). The forward voltage drop of this
diode is also taken into account when calculating the resistor R2. Resistor R2 is calculated by substituting the
minimum input voltage and the current threshold level (see equation below).
 N Vcc 
 ⋅ VIN _ MIN  + Vclamp , demag ( negative ) − VF
R2 =  NP  Equation 5
 N Vcc 
 ⋅ VIN _ MIN  + Vclamp ,demag ( negative )
I ( opp )( demag ) −  P 
N
R1
Where,
NVcc = VCC number of turns
NP = primary number of turns
VIN_MIN = minimum input voltage
Vclamp,demag(negative) = negative clamp voltage of Demag pin (-0.25V)

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VF = forward voltage drop of diode
I(opp)(demag) = current threshold of OPP protection (-24µA)

3.4.4 Short Winding Protection

The short winding protection is implemented to protect against shorted transformer windings, for example in case of
a secondary diode short. In this case the primary inductance is shorted out and the primary current starts to rise at
very high rate (only limited by the leakage inductance) after turn on of the MOSFET. An extra comparator (fixed
threshold of Vswp = 880mV) implemented in the IC will detect this fault condition by sensing the voltage level (via pin
5) across the sense resistor. Immediately the driver is disabled and the controller enters the Safe-Restart mode.
This protection circuit is activated after the leading edge blanking time (LEB).

3.4.5 Minimum and maximum ‘on-time’

The LEB (Leading Edge Blanking) time is an internally fixed delay that determines the minimum ‘on time’ of the
controller. This minimum on time together with the minimum switching frequency and the primary inductance
defines the minimum input power at which the output voltage is still in regulation. Because this minimum frequency
is low it is possible to run at extremely low loads (without any pre-load).
The IC will protect the system against an ‘on-time’ longer then 50µs (internally fixed maximum ‘on-time’). When the
system requires on times longer than 50µs, a fault condition is assumed, and the controller enters the Save-Restart
mode.

3.4.6 Over Temperature protection

When the junction temperature exceeds the thermal shutdown temperature (typ 140°C), the IC will disable the
driver. When the VCC voltage drops to UVLO, the VCC capacitor will be recharged to the V(start) level. If the
temperature is still too high, the VCC voltage will drop again to the UVLO level (Safe-Restart mode). This mode will
persist until the junction temperature drops 4 degrees typically below the shutdown temperature.

3.4.7 Mains dependent operation enabling level

To prevent the supply from starting at a low input voltage, which could case audible noise, a mains detection is
implemented (Mlevel). This detection is provided via pin 8(no additional pin needed), which detects the minimum
start-up voltage between 60V and 100V. As previous mentioned the controller is enabled between 60V and 100V.
This level can be adjusted by connecting a resistance in series with the drain pin, which increases the level by
R1⋅Iin(Drain) volts.
An additional advantage of this function is the protection against a disconnected buffer capacitor (CIN). In this case
the supply will not be able to start-up because the VCC capacitor will not be charged to the start-up voltage.

3.5 Burst mode Stand-by

Burst mode can be used to reduce the power consumption below 1W at stand-by. During Burst mode the controller
is active (generating gate pulses) for only a short time and for a longer time inactive waiting for the next burst cycle.
In the active period the energy is transferred to the secondary and stored in the buffer capacitor CSTAB in front of the
linear stabilizer (see Figure 9). During the inactive period the load (e.g. microprocessor) discharges this capacitor.
In this mode the controller makes use of the Safe-Restart mode.

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VIN

VCC VSTAB VµC

1 Vcc Drain 8
Linear
2 Gnd HVS 7 stabilizer
CVcc 3 Ctrl Driver 6
CSTAB

4 Demag Sense 5

R1 Burst-Mode stand-by on/off

from microprocessor
Current pulse
generator

Figure 9 Basic Burst mode configuration

For a more detailed description of one burst cycle three time intervals are defined:
• t1 Discharge of VCC when gate drive is active
• t2 Discharge of VCC when gate drive is inactive
• t3 Charge of VCC when gate drive is inactive

t2
t1 t3
Active/
inactive

IL
Soft start

VSTAB
VµC

V(start)
VCC
V(UVLO)

Figure 10 Burst mode waveforms

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During the first interval energy is transferred, which result in a ramp-up of the output voltage (VSTAB) in front of the
stabilizer. When enough energy is stored in the capacitor the IC will be switch-off by a current pulse generated at
the secondary side. This pulse is transferred to the primary side via the opto coupler. When this pulse reaches a
threshold level of 16mA into the Ctrl pin it will stop switching. Because of the large variation on the CTR of the opto
coupler a resistor (R1) is placed in series to limit the current going into the Ctrl pin. Meanwhile the VCC capacitor is
discharged but has to stay above VUVLO (see
Figure 10).
During the second interval the VCC is discharged to VUVLO. The output voltage will decrease depending on the load.
The third interval starts when the UVLO is reached. The internal current source charges the VCC capacitor (also the
soft start capacitor is recharged). Once the VCC capacitor is charged to the start-up voltage the driver is activated
and a new burst cycle is started.
The dotted line in Figure 9 shows an additional switch connected between the high voltage winding (e.g. 185V or
80V) and the output that supplies the microprocessor. Closing the switch during Burst mode gives an voltage
reduction of the unused outputs. Reducing the output voltage will prevent consuming any power by these unused
outputs, which result in lower power consumption during stand-by.

3.6 Pin description GreenChipTM TEA1507

SYMBOL PIN DESCRIPTION

Vcc 1 This pin is connected to the supply voltage. An internal current source charges the
VCC capacitor and a start-up sequence is initiated when the voltage reaches a level of
11V. The output driver is disabled when the voltage gets below 9V(UVLO). Operating
range is between 9V and 20V.
Gnd 2 This pin is ground of the IC.
Ctrl 3 This pin is connected to the feedback loop. The pin contains two functions. Between
1V and 1.5V it controls the on time (oscillator). Above a threshold of 3.5V it is
possible to initiate Burst mode stand-by via a current pulse.
Demag 4 This pin is connected to the V CC winding. The pin contains three functions. During
magnetization the input voltage is sensed to compensate the OCP level for OPP
(independent of input voltage). During demagnetization the output voltage is sensed
for OVP and a comparator is used to prevent continuos conduction mode when the
output is overloaded.
Sense 5 This pin contains four different functions. Soft start, frequency reduction and
protection levels OCP (OPP) and SWP. By connecting an RSS and CSS between the
sense resistor and this pin it is possible create a Soft start. The frequency is reduced
starting from a level of 75mV until 50mV where the frequency is equal to the
minimum frequency of the oscillator (6kHz).
Two different protection levels of 0.5V(this OCP level depends on the Demag current)
and 0.88V(fixed SWP level) are implemented.
Driver 6 This pin will drive the switch (MOSFET). The driver is capable of sourcing and sinking
a current of respectively 125mA and 540mA.
HVS 7 This is a High Voltage Spacer (keep this pin floating)
Drain 8 This pin is connected to the drain of the switch or center-tap of the transformer
depending on the voltage (BVDSS = 650V). The pin contains three functions. The
Mlevel that enables the controller between 60V and 100Vinput voltage, supply the
start-up current and valley detection for zero/low voltage switching.
Table 3 Pin description

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4. DESIGN OF 75W UNIVERSAL RANGE MONITOR SUPPLY (COOKBOOK)

4.1 Introduction to design

This monitor supply is designed for a low/mid end 17” monitor with a universal input voltage range. Because of this
Quasi-Resonant typology it is possible to achieve a high efficiency (above 90%). Another important requirement is
the power consumption during stand-by (<1W). Using the Burst mode stand-by of the controller it is possible to fulfil
this requirement.

4.2 Supply specification

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Input requirements
VLINE line voltage nominal operation 85 264 VAC
fLINE line frequency nominal operation 50 60 Hz
PBurst mode Burst mode power Burst mode, 5V@ 20mA and 1 W
consumption other outputs at no load
Output requirements
185V Deflection output all conditions 185 VDC
line regulation 85VAC-264VAC 100 mVDC
load regulation Iout=60mA – 300mA 100 mVDC
line freq. ripple 85VAC, 405mA 200 mVpp
switching freq. ripple 85VAC, 405mA 20 mVpp
overshoot/undershoot Iout=54mA–405mA visa versa ±1 Vp
output current 300 mA
80V Video output VDC
output current 100 mA
16V Base-drive output 16 VDC
output current 20 mA
12V 12V output(linear 12 VDC
regulator)
output current 400 mA
±10V vertical deflection ±10 VDC
output, cathode heater
output current 0.9 A
5V micro controller(linear 5 VDC
regulator)
output current 20 mA
Miscellaneous
η efficiency VLINE = 110Vac and 230Vac, 90 %
POUT = 75W
Table 4 Supply specification

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4.3 Numeric calculations of reference design

4.3.1 Dimensioning the key components

This chapter could be used as a guide line to calculate the large signal components of the Quasi-Resonant
converter including the primary transformer inductance LP the resonance capacitor CD and the sense resistor.
This design strategy is used to design a monitor supply (see circuit diagram Figure Figure 12, page 26). It will be
clear that the strategy differs in each application depending on costs, volume, efficiency etc.

Calculating the transformer inductance L P and the resonance capacitor CD two important requirements are used:
• Universal input range 85VAC…264VAC;
• Operating power range 20W…85Wpeak.
In normal operation, when the deflection circuit of a Monitor is enabled, there will be a certain amount of power
consumption varying between 20W and 85Wpeak. Due to efficiency reasons the converter has to operate in the
Quasi-Resonant mode within this power range, which makes it possible to achieve efficiency up to 90%.
There are also some other choices and criteria that have to be taken care of before starting the design. These
choices strongly depend on the application as mentioned before.
• No peak clamp to limit the maximum voltage across the switch. Minimize component count and improve
efficiency;
• maximum voltage across the power MOSFET (VD_MAX, including ∆V caused by leakage inductance Ls) which
defines maximum turns ratio n;
• fMIN = 25kHz and fMAX = 150kHz. The choice of fMIN determines the transformer size and fMAX is restricted by the
maximum frequency of the controller.

Some additional requirements should be taken into account:

• dV/dt drain source < 4kV/us (EMI reduction)
• Maximum permitted on-time < 50us (t-onmax = 50us fixed by IC)

Eventually there are five different parameters to design:

• Turns ratio n;
• Primary inductance LP and resonance capacitor CD;
• Volt/turn to get the required voltages at the output;
• Core size (Aeff effective core surface).

In the following description the parameters are defined step by step.

Step 1 Maximum turns ratio n

The turns ratio should be as large as possible to get zero voltage switching also at high input voltages. This will
reduce the switching losses of the MOSFET. However the turns ratio is restricted by the choice of the breakdown
voltage of the MOSFET. In this case an 800V MOSFET is chosen because of the wide input voltage range (85Vac
– 264Vac) and an additional spike caused by the leakage inductance of the transformer (no peak clamp is used).
This means that the maximum drain voltage should be lower than 800V including the voltage caused by the
leakage inductance LS. The maximum drain source voltage is equal to:

V D _ MAX = V IN _ MAX + n ⋅ (VOUT + V F ) + ∆V Equation 6

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Where ∆V (caused by the leakage inductance) is estimated by:

LS
∆V = I L _ peak ⋅ Equation 7
CD
Where,
IL_peak = peak inductor current (at maximum input voltage)
LS = leakage inductance
CD = total drain capacitance

Without a peak clamp ∆V depends on the leakage inductance, the total capacitance on the drain node (CR and
parasitic capacitance’s COSS, CW) and the primary peak current just before switch-off. These parameters are not
known yet but assuming the ∆V would be 125V and substituting VIN_MAX = 264√2V, VOUT = 185V and VF = 0.7V
gives a maximum turns ratio of:

VDS _ MAX − VIN _ MAX − ∆V 800 − 264 ⋅ 2 − 125

n≤ = ≤ 1.62 Equation 8
(VOUT + VF ) 185.7

Choosing the maximum turns ratio close to this value of 1.62 will give minimum switch-on losses at high input
voltages. But keep in mind that the value of the ∆V should be checked afterward because this depends on the
transformer construction (leakage inductance).

Step 2 calculating primary inductance LP and resonance capacitor CD

To simplify the formulas the commutation time is neglected and the dead time is assumed to be constant, which is
not the case when VIN < n⋅VOUT (see APPENDIX 2, page 40). Now LP and CD can be calculated by the following
formulas.

2
 1 1 
 − 
f 
 MIN f MAX 
LP = 2
 POUT _ MAX 1  1 1  P  
 2⋅ ⋅ ⋅ +  − 2 ⋅ OUT _ MIN ⋅ 1 ⋅
1
+
1 
 η f MIN  V IN _ MIN n ⋅ VOUT  η f MAX  V IN _ MAX n ⋅ VOUT 
    

1
C D = t DEAD 2 ⋅ Equation 9
π ⋅ LP 2

Where t DEAD is equal to :

1 2 ⋅ POUT _ MAX  1 1 
t DEAD = − LP ⋅ ⋅ + 
f MIN 
η ⋅ LP ⋅ f MIN  V IN _ MIN n ⋅VOUT 


Substituting two different points P1 and P2 in the above formulas:

P1: fMIN = 25kHz @V IN_MIN = 100VDC, POUT_MAX = 85W
P2: fMAX = 150kHz @VIN_MAX = 373VDC, POUT_MIN = 20W
This gives an LP = 1mH and CD = 1.17nF. In practice the capacitor also consist out of a parasitic part (e.g. COSS and
CW). Because of this an actual capacitor value of 1nF is used.

Note:
Keep in mind that the main reason for placing the resonant capacitor is to limit the switch-off losses and to reduce
the dV/dt for EMI reasons. When using the formulas above and choosing a small frequency range (fMIN…fMAX) it

21
Philips Semiconductors

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AN00047
may end up in a large capacitor value, which will result in higher switch-on losses (at high input voltage). In this
case it is recommended to make another choice for the frequency range or the value of PMIN.
The graphic below shows the frequency as function of POUT at VIN_MAX = 373VDC and VIN_MIN = 100VDC.
180
180
170
VVCO,start
160 P2
150
140
130
f NO_VCO( Pout , Vi_max) 120
110
f VCO( Pout , Vi_max)
100
90
f NO_VCO( Pout , Vi_min)
80
f VCO( Pout , Vi_min) 70
60
50
40
30 P1
20
10 VVCO,max
6 0
0 10 20 30 40 50 60 70 80 90
1 Pout 85

Figure 11 Calculated frequency characteristics

In practice the frequency will deviate from the calculated frequency especially at low output powers. This can be
explained because the commutation time (tCOM) between magnetization and demagnetization is neglected and the
dead time is assumed to be constant in the calculations.

step 3 defining secondary voltage/turn

The following output voltages are required: 185Vmain output, 80V, 16V and ±10V. Because the leakage inductance
increases with the number of layers it is recommended to select the voltage per turn as large as possible to reduce
the number of turns. Assuming NS = 34 secondary turns for the main output gives 5.46V per turn (185.7V divided
by 34 turns). In this case the other outputs requires respectively fifteen turns for the 80Voutput, three turns for the
16V output, VCC winding and two turns for the 10V output.

step 4 defining primary number of turns NP

The primary number of turns NP is equal to:

NP = n ⋅ NS
 Equation 10
N P = 1.62 ⋅ 34 ≈ 55

Sense resistor
The sense resistor in series with the MOSFET limits the maximum inductor peak current. The inductor peak current
is calculated by:

POUT n ⋅ VOUT + V IN
I L _ peak = 2 ⋅ ⋅
(
η n ⋅ VOUT ⋅ V IN ⋅ 1 − π ⋅ L P ⋅ C D ⋅ f ) Equation 11

Limiting the output power to 90W and substituting η = 0.9, n⋅VOUT = 300.5V, VIN = 100V, LP = 1mH, CD = 1.17nF
and f = 23.8kHz gives an primary peak current of 2.9A

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Now the sense resistor can be calculated by:

VOCP
RSENSE = Equation 12
I L _ peak
Where,
VOCP = the Over Current Protection level (fixed at 0.5V @ I(opp)(demag) >-24µA)

Substituting VOCP = 0.5V and IL_peak = 2.9A gives a sense resistor of 172mΩ (two resistors of 330mΩ in parallel
gives a maximum primary peak current IL_peak = 3.03A @ VIN = 100V). It is recommended to use low inductive
current sense resistors preventing noise at the Sense pin.

Step 5 Selecting the core size

The peak flux density in the transformer can be calculated by the following equation:

LP ⋅ I L _ peak
B peak = Equation 13
N P ⋅ AMIN
Where,
LP = primary inductance
IL_peak = primary peak current set by the OCP level
Np = primary number of turns
AMIN = minimum core area

The saturation flux density of a ferrite core (Philips 3C85) is equal to 330mT at 100°C. Substituting the previous
calculated LP, IL_peak and NP will give the minimum required core area.

LP ⋅ I L _ peak 1 ⋅ 10 −3 ⋅ 3.03
AMIN ≥ ≥ −3
≥ 167 mm 2 Equation 14
Bsat ⋅ N P 330 ⋅ 10 ⋅ 55

E42/21/15 core can meet this requirement. The core parameters of the E42 are:

SYMBOL PARAMETER VALUE UNIT

3
Ve effective volume 17300 mm
2
Ae effective area 178 mm
2
Amin minimum area 175 mm
Table 5 Core parameters
APPENDIX 3 shows an overview of the transformer data.
The core area is mainly defined by the minimum switching frequency fMIN that is chosen before.
When the core size should be reduced it is recommended to increase the minimum switching frequency and
calculate the new values for LP and CD.

Recommendation for the transformer construction:

The maximum drain source voltage is proportional to the leakage inductance LS, which is modelled as an
inductance in series with the primary inductance. This will cause an additional voltage spike across the MOSFET.
Because of this it is necessary to minimize the leakage inductance. A layer transformer is a good choice regarding
a low leakage inductance. Using a sandwich construction, where the primary winding is split into two windings with
the secondary positioned between those two, will reduce the leakage inductance even more.

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Philips Semiconductors

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Another recommendation with respect to the transformer construction is to put the primary winding, which is
connected to the drain of the MOSFET, at the inner side. In this case the other windings work as a shielding for E-
field generated by this winding.

4.3.2 Protections
The OVP level is set by the resistor between the VCC winding and de Demag pin.

 N Vcc 
 
 N ⋅ OVP  − Vclamp ,demag ( positive )
ROVP =  S  Equation 15
I ( ovp )( demag )

Substituting an OVP level of 200V gives a resistor value of 280kΩ.

 3 
 ⋅ 200  − 0.7
 34 
ROVP = ≈ 280kΩ = R18
60 µ

The Over Power Protection level is set by the negative current going into the Demag pin. The OVP and OPP
protections are separated by means of a diode in series with R17. The forward voltage drop (VF) of this diode is also
taken into account when calculating R17.

 N Vcc 
 ⋅ VIN (min)  + Vclamp ,demag ( negative ) − VF
R17 =  NP  Equation 16
 N Vcc 
 ⋅ VIN (min)  + Vclamp ,demag ( negative )
I ( opp )( demag ) −  P 
N
R18

Substituting a minimum input voltage of 100V and a VD = 0.6V will give the following resistor value:

 3 
 ⋅100  − 0.25 − 0.6
 55 
ROPP = ≈ 820kΩ
 3 
 ⋅ 100  − 0 .25
 55 
24 µ −
280k

4.3.3 Burst mode stand-by

Burst mode is implemented because the specification requires an input power below 1W during Stand-by. In this
Monitor application it was necessary to reduce the unused output voltages because some of these outputs are still
loaded for example the cathode heater of the CRT (Cathode Ray Tube) that is attached to the –10V output. A
thyristor (D4) connects the higher output voltage winding (see schematic) to output that feeds the µC (in front of 5V
linear stabilizer). Because of this bypass all the other output voltages are reduced depending on the turns ratio
between the secondary windings. For example the –10V is reduced to about –1.3V.

24
Philips Semiconductors

;7147[MXL8)% Application Note

AN00047

N −10V 2
V−10V = ⋅ VSTAB = ⋅ 10 ≈ −1.3V
N 80V 15

The thyristor is activated by an external signal (e.g. DPMS signal from µC or S1 on the demo board). Once the
thyristor is closed the voltage at the stabilizer will rise. When the voltage exceeds the zener voltage of Z2 (and
forward voltage drop of both D19, TR4) the transistor TR5 is turned on to generate the current pulse to switch-off the
IC. R33 limits the current through the opto coupler and C28, R25 are used as feed forward to get a steep pulse. Via
the opto coupler this current pulse will enter the Ctrl pin, which will activate the Burst mode stand-by. The minimum
pulse width is defined by the blanking time of 30µs that prevents false triggering due to spikes. The amplitude
should be larger then 16mA. The driver is immediately disabled and the controller will enter the Safe-Restart mode.
Burst mode operation will continue until the DPMS signal is removed.

25
 1 2 3 4 5 6 7 8

4.4
+5V

A R1 A
22k

C1 S1

220pF
P1 F1 C2 1N4148 R3
2 1 2 R2 220pF 4.7k
2A ** 22k D1
Philips Semiconductors

1 FUSE C3 D5 C4 D6
L1 D3 D2 R4 R5 TR1 R6
BC546 100k TR2
2.2nF BYW54 BYW54 1N4148

1N4148
4 3 4.7M 4.7M D7 BT149G 1nF
** ** BC546
C6 C7 VR25 ** VR25
R7
2.2nF 10k
470nF 470nF ** BYD33G D4
2 1 C9 D8 D9
2.6mH_CU20d3_4 C5
2.2nF BYW54 BYW54
Circuit diagram
;7147[MXL8)%

NTC R8
B - P2 B
10R +5V
T1 L2 P4
BYV27-600
10 33uH

BRIDGE_WIRE
+185V
C10 C11 10
D10 R40
9 100k
47uF 47uF GND
9
200V 200V
C12 +80V
11 8
220uF L3
400V D11
8 12 220uH 7 +12V
C13 C14 +16V
35V 1 8 7 BYV27-400 C15 6
Vcc Drain 47uF
22uF
IC1 100V 47uF +5V
5
100V
2 7 13
R10 Gnd LM7812CT DPMS
4.7 TEA1507 D12 L4 4
100uH IC2
PR01 ** C16 TR3 6
R11 ** +9V
22nF 3 Reg 6 C17 14 OUT C18 3
Driver BYD73A ** IN
C 10 C20 C21 GND
C
R12 1nF GND 47uF
** C19 2
R13 470uF 100nF 25V
4 Sense 5 330nF 4
1k Demag 25V -9V
470 15 1
R14 L6 LM7805CT
L5 D14 IC3
S2

R15
22k D13 16

R16
0.33 0.33 BDW3.5_6-4S2 C22 100uH C23 IN OUT
BYW543 BYD73A
GND C24
1000uF 470uF
16V 16V 47uF
D15 25V
18
BYW54

26
C25 C26
2
L7 1000uF L8 470uF
1N4148 R17 D17 16V 16V
17 100uH
D16 1M BDW3.5_6-4S2
BYD73A
R18 R19 1
D 280k 22 D
PR01
R20
820
Z1

Figure 12 Circuit diagram

C27
D18 BZX79C
7V5 22uF
50V
1N4148 R21 R22
1k 1k
5 1 R23 R24
150k 220k
OC1 BAT85
** D19
CNX82A C29 ** C28
100nF R25
10nF
2 ** C30 10k
4 R26 R27 47nF
R28
470 15k BC556
150 1 TR4
E Z3 ** E
TL431C 3 Z2 C31
2 R29 BZX79C
1k 12V 10nF
R31
47k

R32
1.8k

TR5

BC517

R33
150
Engineer: Philips Semiconductors B.V.
F J. Kleuskens Eindhoven The Netherlands F
PHILIPS PHILIPS SEMICONDUCTORS Drawn by: Size:
Sheet Name: 75W monitor supply A3
I.Lodema
Systems Laboratory Eindhoven Changed by:
ilodema

Date/Time Changed: Tuesday, February 29, 2000 2:31:56 pm Project: PR70181 Variant: None Drwg: 130 - 1 / 1

1 2 3 4 5 6 7 8
AN00047
Application Note
Philips Semiconductors

;7147[MXL8)% Application Note

AN00047

4.5 PCB design

4.5.1 Layout considerations

Some important points for a proper layout are reminded below (see also Figure 13):
• At primary side, keep large signal and small signal separated;
• Put a resistor in series with the soft start capacitor to prevent EMI distortion;
• Keep the area and the length of the drain track(high alternating voltages) as small as possible to prevent noise
coupling with high impedance inputs (sense pin, Ctrl pin, Demag pin);
• Noise can be reduced by minimising the area of the current loops (e.g. 1 and 2) with fast alternating currents;
• Do not use a floating heatsink, but connect the heatsink directly or via a capacitor to the primary GND. Use the
heat sink as EMI shield between the small signal and large signal part;
• Connect Cy, between primary GND and secondary GND, with a short track to the primary buffer capacitor.
Prevent a common GND with the controller!!

M ains
filter

C IN

H e a tsin k L arg e
sig n al + CY

CR
R SE N S E 1
T ransform er
2
S m a ll
MOSFET D ra in
sig n al trac k

8 7 6 5
T E A 1507
1 2 3 4
S oft s ta rt
c ircuit
+

H igh
im p edance

Figure 13 Layout considerations

27
Philips Semiconductors

;7147[MXL8)% Application Note

AN00047

4.5.2 PCB layout

Figure 14 PCB layout

28
Philips Semiconductors

;7147[MXL8)% Application Note

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4.5.3 Parts list

REFERENCE VALUE TYPE PACKAGE 12NC
Capacitors
C1 220pF CER2_1 2222-655-03221
C2 220pF CER2_1 2222-655-03221
C3 2.2nF MKP3366 (Y2) C_B6_L12.5_P10mm 2222-336-60222
C4 1nF CER1_1 2222-630-02102
C5 2.2nF MKP3366 (Y2) C_B6_L12.5_P10mm 2222-336-60222
C6 470nF MKP336 (X2) C_B15_L31_P27mm5 2222-336-10474
C7 470nF MKP336 (X2) C_B15_L31_P27mm5 2222-336-10474
C9 2.2nF MKP3366 (Y2) C_B6_L12.5_P10mm 2222-336-60222
C10 47uF KO151 CASE_R18 2222-151-62479
C11 47uF KO151 CASE_R18 2222-151-62479
C12 220uF 057 PSM-SI CASE_3050 2222-057-36221
C13 22uF 037 RSM CASE_R55_CA 2222-134-50229
C14 47uF 037 RSM CASE_R16 2222-037-69479
C15 47uF 037 RSM CASE_R16 2222-037-69479
C16 22nF MKT 370 C370_A 2222-370-21223
C17 1nF KP/MMKP376 C_B6_L18.5_P15mm 2222-375-44102
C18 47uF 097 RLP CASE_R11_m 2222-037-56479
C19 330nF MKT 370 C370_B 2222-370-11334
C20 470uF 136 RVI CASE_R16 2222-136-66471
C21 100nF MKT 370 C370_A 2222-370-11104
C22 1000uF 037 RSM CASE_R16 2222-037-65102
C23 470uF 037 RSM CASE_R14 2222-037-65471
C24 47uF 037 RSM CASE_R74_m 2222-097-56479
C25 1000uF 037 RSM CASE_R16 2222-037-65102
C26 470uF 037 RSM CASE_R14 2222-037-65471
C27 22uF 037 RSM CASE_R11_m 2222-037-90056
C28 100nF MKT 370 C370_B 2222-370-21104
C29 10nF MKT 370 C_B2.5_L7.2_P5mm08 2222-370-41103
C30 47nF MKT 370 C370_A 2222-370-21473
C31 10nF MKT 370 C_B2.5_L7.2_P5mm08 2222-370-76103
Diodes
D1 1N4148 general purpose SOD27 9330-839-90153
D2 BYW54 control. avalanche SOD57 9333-636-10153
D3 BYW54 control. avalanche SOD57 9333-636-10153
D4 BT149G thyristor TO92 9333-984-40112
D5 1N4148 general purpose SOD27 9330-839-90153
D6 1N4148 general purpose SOD27 9330-839-90153
D7 BYD33G control. avalanche SOD81 9337-234-10113
D8 BYW54 control. avalanche SOD57 9333-636-10153
D9 BYW54 control. avalanche SOD57 9333-636-10153
D10 BYV27-600 control. avalanche SOD57 9340-418-70113
D11 BYV27-400 control. avalanche SOD57 9340-366-90133
D12 BYD73A control. avalanche SOD81 9337-537-40163
D13 BYW54 control. avalanche SOD57 9333-636-10153
D14 BYD73A control. avalanche SOD81 9337-537-40163
D15 BYW54 control. avalanche SOD57 9333-636-10153
D16 1N4148 general purpose SOD27 9330-839-90153
D17 BYD73A control. avalanche SOD81 9337-537-40163
D18 1N4148 general purpose SOD27 9330-839-90153
D19 BAT85 shottky barrier SOD68 9336-247-60112
Z1 BZX79C zener SOD27 9331-177-60153
Z2 BZX79C zener SOD27 9331-178-10153
Z3 TL431C voltage regulator TO226AA TL431C
IC’s
IC1 TEA1507 PWM controller SOT97_s DIL8
IC2 LM7812CT linear stabilizer TO220_vc PN-LM7812CT
IC3 LM7805CT linear stabilizer TO220_vc PN-LM7805CT
OC1 CNX82A Opto-coupler SOT231 9338-846-80127
Magnetics
L1 2.6mH CU20d3_4 common mode choke CU20d3 3112-338-32441
L2 33uH Choke TSL0707_2e TSL0709-33K1R9

29
Philips Semiconductors

;7147[MXL8)% Application Note

AN00047
L3 220uH Choke uChoke_3e LAL03NA221K
L4 100uH Choke TSL0707_5mm0 TSL0709-101KR66
L5 BDW3.5_6-4S2 ferrite bead 4330-030-38741
L6 100uH Choke TSL0707_5mm0 TSL0709-101KR66
L7 BDW3.5_6-4S2 ferrite bead 4330-030-38741
L8 100uH Choke TSL0707_5mm0 TSL0709-101KR66
T1 1000uH CE422v SMPS transformer 8228-001-32811
Resistors
R1 22k SFR16T 2322-180-73223
R2 22k SFR16T 2322-180-73223
R3 4.7k SFR16T 2322-180-73472
R4 4.7M VR25 2322-241-13475
R5 4.7M VR25 2322-241-13475
R6 100k SFR16T 2322-180-73104
R7 10k SFR16T 2322-180-73103
R8 10 NTC 2322-594-XXXXX
R10 4.7 PR01 2322-193-13478
R11 10 SFR16T 2322-180-73109
R12 1k SFR16T 2322-180-73102
R13 470 SFR16T 2322-180-73471
R14 22k SFR16T 2322-180-73223
R15 0.33 SFR25H RES-186-SFR25H
R16 0.33 SFR25H RES-186-SFR25H
R17 820k SFR16T 2322-180-73105
R18 280k SFR16 2322-187-53284
R19 22 PR01 2322-193-13229
R20 820 SFR16T 2322-180-73821
R21 1k SFR16T 2322-180-73102
R22 1k SFR16T 2322-180-73102
R23 150k SFR16T 2322-180-73154
R24 220k SFR16T 2322-180-73224
R25 2.2k SFR16T 2322-180-73222
R26 470 SFR16T 2322-180-73471
R27 15k SFR16T 2322-180-73153
R28 150 MRS25 2322-156-11501
R29 1k SFR16T 2322-180-73821
R31 47k SFR16T 2322-180-73473
R32 1.8k SFR16T 2322-180-73182
R33 150 SFR16T 2322-180-73151
R40 100k SFR16T 2322-180-73104
Miscellaneous
F1 2A fuse GLAS_HOLDER 2412-086-28196
P1 MKS3730_2p_220V connector (mains) MKS3733-1-0-303
P4 MKS3730_10p connector (output) MKS3740-1-0-1010
S1 SPDT FARNELL-150-559
S2 SPDT FARNELL-150-559
Transistors
TR1 BC546 general purpose TO92 9332-055-20112
TR2 BC546 general purpose TO92 9332-055-20112
TR3 STP7NB80FP MOSFET TO220 STP7NB80FP
TR4 BC556 general purpose TO92 9332-055-40112
TR5 BC517 darlington TO92 9335-671-30112
Table 6 Parts list

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5. MAESUREMENTS

5.1 Static performance

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
Line regulation
185V Horizontal 85VAC<Vin<264VAC, I = 405mA 185.00 185.01 VDC
deflection,
EHT
Load regulation
185V Horizontal Vline = 110VAC 185.06 185.02 VDC
deflection, 60mA<Iout_185V <300mA, others
EHT
unloaded
Standby power consumption from line
Pstby Input power VLINE = 230VRMS, 20mA @ 5V 980 mW
Table 7 Static performance

5.1.1 Switching frequency vs output power

Figure below shows the measured switching frequency as a function of output power at two different input voltages.

Frequency vs output power

145.00
125.00
105.00
f[kHz]

85.00 Vin = 155Vdc

65.00 Vin = 325Vdc
45.00
25.00
5.00
0 20 40 60 80 100
Pout[W]

Figure 15 Measured frequency curve

Note: DC input voltage is applied during this measurement

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5.1.2 Efficiency
The figure below shows the efficiency measured at two different input voltages respectively 110Vac and 230Vac.
Both curves showing efficiency above 90% at a nominal output power of 75W. The efficiency stays even above
87% over the power range from 20W to 85W. Efficiency is a big advantage of the Quasi-Resonant Flyback
converter compared to the Fixed Frequency Flyback converter.

Efficiency vs output power

95.0
90.0
eff[%]

85.0 Vin = 110Vac

80.0 Vin = 230Vac
75.0
70.0
0.0 20.0 40.0 60.0 80.0 100.0
Pout[W]

Figure 16 Measured efficiency

Note: Only the 185V output is loaded during this measurement

This high efficiency is mainly achieved because of the ZVS/LVS switching, which reduces the switch-on losses and
makes it possible to use a non-dissipative dV/dt limiter (only a capacitor across the drain-source of the MOSFET).

5.1.3 Over Voltage Protection

To illustrate the accuracy of the Over Voltage Protection a measurement is done at different input voltage and at
different output loads such that the ringing of the reflected output voltage will be different in each condition. As
previous described the ringing of the reflected output voltage is integrated, which makes the Over Voltage
Protection rather accurate. The diagram below shows the OVP level under different conditions.
Over Voltage Protection level

215

210
OVP level[V]

205 110Vac
200 230Vac

195

190
0 50 100 150 200 250 300
Iout[mA]

Figure 17 Measured OVP level

From this measurement it can be seen that the OVP level stays within 5% of the nominal value.

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5.1.4 Over Power Protection

This internal OCP compensation is big advantage when using a Quasi-Resonant Flyback converter. Because of
this compensation the maximum output stays almost equal independent of the input voltage. The diagram below
shows the OPP level over the entire input voltage range.
Over Power Protection level

115

110
OPP level[W]

105

100 Output power

95

90

85
100 200 300 400
Vin[V]

Figure 18 Measured OPP level

From this measurement it can be seen that the OPP level stays within 20% of the maximum value.

5.2 Dynamic performance

5.2.1 Start-up sequence

Figure 19 shows the waveforms during start-up. The Vcc capacitor is charged to V(start) and the driver is activated.
In the meanwhile the voltage at the soft start capacitor C19 is charged to 0.5V. The peak current of the inductor will
increase exponential which can be seen from the voltage (CH3) measured across the sense resistor. The OCP
level, that depends on the input voltage, limits the maximum peak current. In this case the OCP level is close to
0.5V because this measurement is done at low input voltage (110Vac). After about 35 ms the output is in regulation
and the peak current is reduced depending on the output power.

V (start) = 11V
CH1: V CC

OCP level
CH2: V SENSE
Soft start
CH3: V R SENSE

CH4: V OUT_185V

Figure 19 Start-up sequence

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5.2.2 Load response

CH4 : Iout_185V

CH1 : V out_1585 V
Vp
Conditions:
V IN = 110V AC

Figure 20 Load response

Figure 20 shows the response of the 185V deflection output when applying a load step. The load varies between
54mA (10W) and 405mA(75W). This is an even more severely load step than compared to a transition from black
to full white screen in a monitor application. The overshoot is equal to VP = 410mV. From this it can be concluded
that the overshoot stays within the specification of ±1V of its nominal range.

5.2.3 Line and switching ripple

Figure 21 shows the line related AC ripple of the 185V output during minimum input voltage (worst case) and 75W
output power. The output ripple is 90mVPP. This is well within the specification of 200mVPP.

CH2: VC12

VPP CH1: VOUT_185V

VPP CH1: VOUT_185V

Conditions: Conditions:
VIN = 85VAC VIN = 85VAC
POUT = 75W POUT = 75W

Figure 21 Line related ripple Figure 22 Switching ripple

Figure 22 shows the switching frequency related AC ripple of the 185V output at minimum input voltage (worst
case) and 75W output power. The output ripple is 18mVPP. This is within the specification of 20mVPP.

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5.2.4 Loop transfer function

Figure 23 Bode plot

Figure 23 shows the bode plot of the measured loop transfer function including the Gain (trace A) and the Phase
(trace B). This plot shows that the bandwidth is 820Hz and phase margin is 70 degrees at VLINE = 110VAC and POUT
= 75W.

5.2.5 EMI results

70

Quasi−Peak Limit
60

Average Limit
50

40
U [dBuV]

30

20

10

0
3 4
10 10
f [kHz]

Figure 24 CISPR 13/22 measurement (150kHz-30MHz) @ Vin = 230Vac, nominal load

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70

Quasi−Peak/Average Limit
60

50

40
U [dBuV]

30

20

10

0
2 3
10 10
f [MHz]

Figure 25 CISPR 13/22 measurement (30MHz-1GHz) @ Vin = 230Vac, nominal load

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APPENDIX 1 LIST OF SYMBOLS

Symbol Description
n Transformer turns ratio
Nx Number of turns
VLINE Line voltage
fLINE Line frequency
VIN Rectified line voltage
VOUT DC output voltage
IOUT DC output current
VF Diode forward voltage drop
VCC IC supply voltage
VOCP Over Current Protection level
CTR Current Transfer Ratio
RSENSE Primary current sense resistor
RDS(ON) Drain-source on-resistance
CD Total drain node capacitance (including CR, COSS and CP)
CR Drain-source resonance capacitor
COSS Parasitic MOSFET output capacitance
CW Parasitic transformer winding capacitance
VD Drain voltage
IL Inductor current
LP Primary transformer inductance
LS Leakage inductance
ZVS Zero Voltage Switching
LVS Low Voltage Switching
Table 8 List of symbols

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APPENDIX 2 DETAILED PERIOD DESCRIPTION OF QR WAVEFORMS

The period can be divided into four time intervals, in chronological order:
Interval 1: t0 < t < t1 primary stroke tPRIM = t1 – t0
Interval 2: t1 < t < t2 commutation time tCOM = t2 – t1
Interval 3: t2 < t < t3 secondary stroke tSEC = t3 – t2
Interval 4: t3 < t < t00 dead time tDEAD = t00 – t3

Three situations of VIN with regard to n⋅VOUT has to be distinguished:

Situation Drain voltage at switch-on

1] VIN = n⋅VOUT ZVS
2] VIN < n⋅VOUT ZVS
3] VIN > n⋅VOUT LVS

1] VIN = n⋅VOUT
One period of Inductor Current
1.5

I 1( t)

1
I 2( t)

I 3( t)
Iinductor (A)

I 4x ( t ) 0.5 tt 11 t 1t 2 t2
t00
tt00
t3 t3
I 4( t)
t00
__ZERO
0

0.5
1 .10 2 .10 3 .10 4 .10 5 .10 6 .10 7 .10 8 .10 9 .10 1 .10 .10
6 6 6 6 6 6 6 6 6 5 5
0 1.1
t
t (s)

t 0 = 0 t 1 = 3.527 µ t 2 = 4.197 µ t 3 = 7.724 µ t 00x = 11.194 µ T tot = 11.194 µ

One period of Drain Voltage

V 1( t )
600

V 2( t )

V 3( t )
Vdrain (V)

400
V 4x ( t )

V 4( t ) t1 t2
t1 t3
V IN t3
200 t00
__ZERO
t2 t00
tt00

0
1 .10 2 .10 3 .10 4 .10 5 .10 6 .10 7 .10 8 .10 9 .10 1 .10 .10
6 6 6 6 6 6 6 6 6 5 5
0 1.1
t
t (s)

Figure 26 Waveforms VIN = n⋅VOUT

Interval 1: t0 ≤ t < t1 primary stroke:

During this interval inductive current will be built up in the transformer, which is also called ‘Magnetization’ and/or
primary stroke. End point t00 of the period is the start point of the new period t0. As can be seen in Figure 26 the
MOSFET is switched on at zero drain voltage called ZVS. The inductive current and drain voltage during this
interval can be described by:

V IN
I L (t ) = ⋅ (t − t 0 ) + I L (t 0 ) where I L (t 0 ) = 0 and t 0 = 0
LP Equation 17
V D (t ) = I L (t ) ⋅ ( R SENSE + R DS (ON ) )

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Interval 2: t1 ≤ t < t2 commutation time tCOM

At t = t1 the MOSFET stops conduction. The energy in the inductor LP is transferred to the resonance capacitor CD.
A resonance circuit of LP and CD is formed and during this interval the inductive current/voltage will follow a part of
the LPCD-oscillation. The inductive current and drain voltage during this interval can be described by:
CD 1
I L (t ) = V IN ⋅ ⋅ sin{ω (t − t1 )} + I L (t1 ) ⋅ cos{ω (t − t1 )} wher e : ω =
LP LP ⋅ C D
Equation 18
LP
V D (t ) = I L (t1 ) ⋅ ⋅ sin{ω (t − t1 )} − V IN (t1 ) ⋅ cos{ω (t − t1 )}
CD
The inductive current needs this interval to alter its positive derivative, equal to VIN/LP, to the negative derivative,
equal to -n⋅VOUT/LP, with which the transformer in the next interval will be demagnetized. This interval does not
belong to the Magnetization or Demagnetization part, so it can be considered as a commutation time, which is
called tCOM, between the primary and secondary stroke.

tCOM can be approached by:

C D ⋅ (VIN + n ⋅ VOUT )
t COM = Equation 19
I L (t1 )

Interval 3: t2 ≤ t < t3 secondary stroke

During this interval (primary) inductive energy will be transferred to the output. The diode starts conducting and the
inductive current will be decreased, which is also called ‘Demagnetization’ At t3 the transformer is completely
demagnetized, for that reason this point is called Demag. The inductive current and drain voltage during this
interval can be described by:
n ⋅ VOUT
I L (t ) = − ⋅ (t − t 2 ) + I L (t 2 )
LP Equation 20
VD (t ) = VIN + n ⋅ VOUT

In practice the leakage inductance (Ls) will cause an oscillation together with the resonance capacitor CD. The
resulting oscillation current and voltage must be add to respectively the inductive current and drain voltage. This
phenomenon is beyond the scope of this waveform explanation and is neglected for that reason.

Interval 4: t3 ≤ t < t00 dead time tDEAD

At t3 = Demag all energy has been delivered to the load, so the diode stops conducting. Again a resonance circuit
of LP and CD is formed.
The controller measures the derivative of the drain voltage. When at t00 after a negative slope the derivative will
become zero, what occurs in the valley, the MOSFET will be switch-on again.
dV D
VALLEY = derivative drain voltage zero : =0
dt
The inductive current and drain voltage during this interval can be described by:
CD
I L (t ) = −n ⋅ VOUT ⋅ ⋅ sin{ω (t − t 3 )
LP Equation 21
VD (t ) = VIN + n ⋅ VOUT ⋅ cos{ω (t − t 3 )

The actually dead time is almost constant and can be calculated by:
t DEAD = π ⋅ LP ⋅ C D

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New period Interval 1:
Time t00 will be t0 in the next period
dI L n ⋅ VOUT dI L VIN
at t 00 = at t 0 = Equation 22
dt LP dt LP

The derivatives of the inductive current at the end of interval 4 is not equal to that of the begin of interval 1.
Because of that a discontinuity (of the slope) in the current waveform occurs.

2] VIN < n⋅VOUT

One period of Inductor Current
1.5

I 1( t)

1
I 2( t)

I 3( t) t1 t0 0 x
Iinductor (A)

I 4x ( t ) 0.5
t2
I 4( t)
t 0t 0 t3 tZ V tt00 00
__ZERO
0

0.5
2 .10 4 .10 6 .10 8 .10 1 .10 .10 .10
6 6 6 6 5 5 5
0 1.2 1.4
t
t (s)

t 0 = 0 t 1 = 6.125 µ t 2 = 6.62 µ t 3 = 10.619 µ t ZV = 13.16 µ t 00x = 14.089 µ T tot = 14.395 µ

One period of Drain Voltage

600

V 1( t )

V 2( t )
400
t1
V 3( t )
Vdrain (V)

V 4x ( t )
200
V 4( t )
t3 tZ V
t0 t0 0
V IN t2
0
__ZERO
t0 0x

200
2 .10 4 .10 6 .10 8 .10 1 .10 .10 .10
6 6 6 6 5 5 5
0 1.2 1.4
t
t (s)

Figure 27 Waveforms VIN < n⋅VOUT

The description of the period is mainly the same as the previous condition when VIN = n⋅VOUT. The inductive current
and drain voltage during of the intervals-1, -2 and –3 can be described with the same formulas. The main difference
is the voltage/current description of interval-4 and the longer tDEAD in this situation.

Interval 4: t3 < t < t00 dead time tDEAD

The current and voltage will follow a part of the oscillation again of LP and CD. The drain voltage ‘wants’ to cross
zero level but this is avoided by the anti parallel body diode of the MOSFET. When the drain voltage goes negative
the internal MOSFET diode start to conduct en the drain voltage will remain on minus forward diode voltage till the
MOSFET is switched on.
The derivative of the drain voltage is still measured by the controller. When at tZV after a negative slope the
derivative has been become zero due to the clamping of the diode, the controller is judging it as sensing a valley,
so the MOSFET will be switch-on again.
The forward voltage of the internal body diode is neglected, so drain voltage is assumed to be zero. In this situation
interval-4 can be divided into two subintervals. The inductive current and drain voltage during this interval can be
described by:

Subinterval-4a: t3 ≤ t < tZV

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CD
I L (t ) = −n ⋅ VOUT ⋅ ⋅ sin{ω (t − t 3 )
LP Equation 23
VD (t ) = VIN + n ⋅ VOUT ⋅ cos{ω (t − t 3 )

Subinterval-4b: tZV ≤ t < t00

VIN
I L (t ) = ⋅ (t − t ZV ) + I L (t ZV )
LP
dVD
VD (t ) = 0 and so =0 Equation 24
dt
dI L n ⋅ VOUT
=
dt LP

As can be seen in Figure 27 the MOSFET is switched on at tZV , where the drain voltage is zero. The MOSFET will
first conduct the negative current, with derivative VIN/LP. From tZV until t00 there is no energy stored in the
transformer that will be transferred to the output. The result of this is that the dead time is slightly longer compared
to the previous situation. This means also that there is no direct relation anymore between the on time (=width gate
pulse) and the energy that is transferred to the output.
In all three situations Ttot=t00. In this situation t00x represents the value of t00 if there was no ‘head bumping’.

3] VIN > n⋅VOUT

One period of Inductor Current
1.5

I 1( t )

I 2( t ) 1

I 3( t )
Iinductor (A)

I 4x ( t ) 0.5 tt 11 t2
I 4( t ) t0
t3 t00
__ZERO
0

0.5
1 .10 2 .10 3 .10 4 .10 5 .10 6 .10 7 .10 8 .10 9 .10 1 .10
6 6 6 6 6 6 6 6 6 5
0
t
t (s)

t 0 = 0 t 1 = 2.627 µ t 2 = 3.416 µ t 3 = 6.792 µ t 00x = 10.262 µ T tot = 10.262 µ

One period of Drain Voltage

V 1( t )

V 2( t ) 600

V 3( t )
Vdrain (V)

V 4x ( t )
400
V 4( t ) t1 t2
V IN t3
200
__ZERO
t00
t0
0
1 .10 2 .10 3 .10 4 .10 5 .10 6 .10 7 .10 8 .10 9 .10 1 .10
6 6 6 6 6 6 6 6 6 5
0
t
t (s)

Figure 28 Waveforms VIN > n⋅VOUT

The description of the period is mainly the same as the first situation when VIN = n⋅VOUT, so the inductive current
and drain voltage during all intervals can be described with the same formulas. The only difference is the voltage
across the MOSFET during switch-on.

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As can be seen in Figure 28 the MOSFET is switched on again at the valley of the drain voltage. The voltage level
in this situation is not zero but slightly above zero. This is called LVS, which result in switch-on losses in the
MOSFET.

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APPENDIX 3 TRANSFORMER DATA

1 17

2 18

16
15

14
6 13

7 12
8 11

9 10

Figure 29 Transformer pin diagram

Electrical data Conditions Value Unit

1000 ±5% µH
1
Inductance 6-9 1V @ 10kHz
Leakage 0.2V @ 100kHz, all secondary ≤ 10 µH
2
inductance windings shorted
Core data Material Airgap
E42/21/15 3C85 TBD µm
Winding data Description Number of turns Wire
dia
Primary windings
6-7 Main input 28 8 x 0.2
8-9 Main input 27 8 x 0.2
1-2 Auxiliary 3 0.2
Secondary windings
10-11 Main output 185V 34 8 x 0.2
12-13 80V 15 0.2
14-15 16V 3 0.3
16-18 10V 2 0.2
18-17 -10V 2 0.2
Table 9 Transformer data
Note 1: For primary inductance measurements pins 7 and 8 have to be interconnected
Note 2: For leakage inductance measurements all secondary pins have to be interconnected

43