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PCI Local BusSpecification
Revision 2.3March 29, 2002
 
Revision 2.3
ii
REVISIONREVISION HISTORYDATE
1.0Original issue6/22/922.0Incorporated connector and add-in card specification4/30/932.1Incorporated clarifications and added 66 MHz chapter6/1/952.2Incorporated ECNs and improved readability12/18/982.3Incorporated ECNs, errata, and deleted 5 volt only keyedadd-in cards3/29/02
The PCI Special Interest Group disclaims all warranties and liability for the use of this documentand the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update theinformation contained herein.Contact the PCI Special Interest Group office to obtain the latest revision of the specification.Questions regarding the PCI specification or membership in the PCI Special Interest Group may be forwarded to:PCI Special Interest Group5440 SW Westgate DriveSuite 217Portland, Oregon 97221Phone: 800-433-5177 (Inside the U.S.)503-291-2569 (Outside the U.S.)Fax: 503-297-1090e-mail administration@pcisig.comhttp://www.pcisig.comDISCLAIMER This PCI Local Bus Specification is provided "as is" with no warranties whatsoever, including anywarranty of merchantability, noninfringement, fitness for any particular purpose, or any warrantyotherwise arising out of any proposal, specification, or sample. The PCI SIG disclaims all liabilityfor infringement of proprietary rights, relating to use of information in this specification. Nolicense, express or implied, by estoppel or otherwise, to any intellectual property rights is grantedherein.FireWire is a trademark of Apple Computer, Inc.Token Ring and VGA are trademarks and PS/2, IBM, Micro Channel, OS/2, and PC AT areregistered trademarks of IBM Corporation.Windows, MS-DOS, and Microsoft are registered trademarks of Microsoft Corporation.Tristate is a registered trademark of National Semiconductor. NuBus is a trademark of Texas Instruments.Ethernet is a registered trademark of Xerox Corporation.All other product names are trademarks, registered trademarks, or service marks of their respectiveowners.
Copyright © 1992, 1993, 1995, 1998, 2002 PCI Special Interest Group
 
Revision 2.3
iii
Contents
Preface
Specification Supersedes Earlier Documents ..................................................................xiiiIncorporation of Engineering Change Notices (ECNs)...................................................xiiiDocument Conventions.................................................................................................... xiv
Chapter 1 Introduction
1.1. Specification Contents................................................................................................11.2. Motivation...................................................................................................................11.3. PCI Local Bus Applications .......................................................................................21.4. PCI Local Bus Overview............................................................................................31.5. PCI Local Bus Features and Benefits.........................................................................41.6. Administration............................................................................................................6
Chapter 2 Signal Definition
2.1. Signal Type Definition................................................................................................82.2. Pin Functional Groups................................................................................................8
2.2.1. System Pins......................................................................................................................82.2.2. Address and Data Pins .....................................................................................................92.2.3. Interface Control Pins....................................................................................................102.2.4. Arbitration Pins (Bus Masters Only) .............................................................................112.2.5. Error Reporting Pins......................................................................................................122.2.6. Interrupt Pins (Optional)................................................................................................132.2.7. Additional Signals..........................................................................................................152.2.8. 64-Bit Bus Extension Pins (Optional)............................................................................172.2.9. JTAG/Boundary Scan Pins (Optional)...........................................................................182.2.10. System Management Bus Interface Pins (Optional)...................................................19
2.3. Sideband Signals.......................................................................................................192.4. Central Resource Functions......................................................................................19
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