Reexam Control No.: 95/001,166 Attomey Docket No. 2805.003REX8 Remarks Claims 1-25 of U.S. Patent No. 7,287,109 (“the ‘109 patent”) are currently subject to inter partes reexamination. All the claims stand rejected in the Office Action dated May 15th 2009 (“Office Action”). The patent owner Rambus respectfully traverses, Based on the following remarks, Rambus respectfully requests that the Examiner reconsider all outstanding rejections and that they be withdrawn. Section I provides a brief description of the applied references. Section II addresses the adopted substantive rejections in the order they were presented in the Office Action. Section IIT presents objective indicia of non-obviousness. Section IV briefly addresses claim construction issues in this reexamination. I. BACKGROUND A. Brief Description of the Applied References J. U.S, Pat. No. 6,584,037 and U.S. Pat. No. 5,319,755 to Farmwald ef al. ‘The disclosures of U.S. Pat. No. 6,584,037 and U.S. Pat, No. 5,319,755 (collectively “the Farmwald patents”) are sufficiently similar for them to be discussed concurrently in this background section. Citation in this section will be to the ‘037 patent. Unless otherwise noted, substantially identical material will be present in the ‘755 patent at a similar location. The Farmwald patents claim priority to the same original application—Application No, 07/510,898, filed on April 18, 1990. The patent owner Rambus also owns the Farmwald patents. Farmwald “755 was cited and applied during original prosecution of the above captioned ‘109 patent and the ‘037 disclosure is cumulative to the *755 patent disclosure. The Farmwald patents describe in one embodiment a system where a write request is provided to the memory device and in response to that request, the memory device will sample data after a delay time has transpired. (‘755 patent, 8:56-12:24.) Additionally, in another embodiment, a transceiver is disclosed that addresses the problem of the physical limitation on the number of memory devices that can be connected to a single bus. (‘755 patent, 20:47-22:31.) 2. U.S. Pat. No. 5,218,684 to Hayes ef al. Many early DRAM devices were asynchronous, meaning that transmission of command and address information was not timed according to a clock signal. U.S. Patent Number 5,218,684 to Hayes (“Hayes”) discloses an example of such an asynchronous system that includes a memory controller that interfaces with asynchronous memory devices. (Hayes, 4:1-4; 4:22-24; 6:1-20.). More specifically, Hayes relates to “a method and apparatus for configuring additional memory used with a stand alone digital computer system including a single board central processing unit and limited on-board memory. The invention provides an efficient memory system configuration adaptable to accommodate and effectively utilize additional memory that is not of a pre-determined size and also that is not physically restricted to be connected in any specific backplane slot.” (Hayes, 1:11-19) 3. A.500-Megabyte/s Data-Rate 4.5M DRAM, by Kushiyama et al. ‘The 500-Megabyte/s Data-Rate 4.5M DRAM article, by Kushiyama et al. (“Kushiyama”) appears to have been published in the April 1993 volume of IEEE Journal of Solid-State Circuits. Kushiyama describes a request-oriented synchronous DRAM device. -8-Reexam Control No.: 95/001,166 Attorney Docket No. 2805,003REX8 4, High Speed DRAMs with Innovative Architectures by Ohshima ‘The High Speed Innovative DRAMs with Innovative Architectures article by Ohshima et al. (“Ohshima”) appears to be an article published in an August 1994 issue of IEICE Transactions on Electronics. Ohshima discusses several different types of DRAMs that it labels Synchronous DRAM (“SDRAM”), cache DRAM, and Rambus DRAM (“RDRAM”), which is also synchronous. 5. Future of DRAMs by Nicky C-C Lu et al. ‘The Future of DRAMs by Nicky C-C Lu et al. (“Lu”) appears to be a preview for a panel discussion given at the 1988 IEEE International Solid State Circuits Conference. The digest indicates that the panel discussion was expected to address high-speed DRAM. Rambus notes that Lu is not a digest of what actually was discussed. Rather, it is simply a preview of what was expected to be discussed during the IEEE panel discussion. (Murphy Dec., | 36.) Lu is exceedingly brief and does not provide any details; nor does it provide any enabling technical disclosure. 6. The RAM Reference by Intel Corporation The iRAM reference appears to be an excerpt from a 1985 Memory Components Handbook by Intel Corporation. For completeness, Rambus provides thee entire handbook. iRAM discloses an “Integrated RAM” or “iRAM” for “relatively small memories in microprocessor environments.” (RAM, 1-1.) One of ordinary skill in the art would interpret the RAM reference as being directed to only asynchronous systems. Further, the majority of its teachings are narrowly directed to integrating “a dynamic RAM and its control and refresh circuitry on one substrate, [thereby] creating a chip that has dynamic RAM density characteristics, but looks like a static RAM to users.” (RAM, 1-2.) Il, _ RESPONSE TO SUBSTANTIVE REJECTIONS A. Review of Legal Standards Governing the Rejection 1, Standard of Review ‘The standard of review for determining patentability is “preponderance of the evidence.” (MPEP § 706.1.) The examiner must weigh the evidence presented for and against patentability and if it is more likely than not that the claims are patentable, they must be allowed. (Id.) Patentability is determined through the lens of one having ordinary skill in the art at the time the application was filed. Phillips v. AWH Corp., 415 F.3d 1303, 1316 (Fed. Cir. 2005) (en banc), Further, the scope of the claims in patent applications is to be determined “not solely on the basis, of the claim language, but upon giving claims their broadest reasonable construction “in light of the specification as it would be interpreted by one of ordinary skill in the art.” Id, (quoting In re Am, Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004)). 2. Anticipation For a prior art reference to anticipate the claimed invention, it must disclose each and every element as set forth in the claim. See Finnigan Corp. v. United States Int'l Trade Comm'n, 180 F.3d 1354, 1365-66 (Fed. Cir. 1999). The requirement of strict identity between the claim and the prior art reference is not met if a single element or limitation required by the claim isReexam Control No.: 95/001,166 Attomey Docket No. 2805,003REX8 missing from the prior art source. See Structural Rubber Prods. Co. v. Park Rubber Co., 749 F.2d 707, 716 (Fed. Cir. 1984), 3. Obviousness “A patent may not be obtained . .. if the differences between the subject matter sought to be patented and the subject matter as a whole would have been obvious at the time the invention was made to a person of ordinary skill in the art to which the subject matter pertain.” 35 U.S.C. §103(a). In KSR Int'l v. Teleflex 550 U.S. 398 (2006), the Supreme Court reaffirmed its decision in Graham v. John Deere that said to find an invention obvious “the scope and content of the prior art [must] be determined; differences between the prior art and the claims at issue [must] be ascertained; and the level of ordinary skill in the pertinent art [must be] resolved.” Graham v. John Deere Co., 383 US. 1, 17 (1966). Graham also set forth “secondary considerations” relevant to nonobviousness such as “commercial success, long felt but unsolved needs, [and] failure of others.” Id. at 17-18. To guard against impermissible hindsight, the Office must fully articulate its obviousness. rejections, See In re Kahn, 441 F.3d 977, 986 (Fed. Cir. 2006). For instance, the Examiner may not use the challenged claims as a roadmap on how to combine references. Instead, the Examiner must rely solely on the prior art teachings and knowledge of a person of ordinary skill at the time the invention was made to determine whether an invention is obvious. See id’; see also MPEP 2145.X.A. For this reason, obviousness analysis is not an armchair exercise. If a person of skill in the art would not have identified the proposed combination, or if the proposed modification would have been inoperable, a conclusion of obviousness is improper. Further, “[if [a] proposed modification would render the prior art invention being modified unsatisfactory for its intended purpose, then there is no suggestion or motivation to make the proposed modification.” MPEI 2143.01.V. An Examiner must also weigh teachings in favor of combination against teachings against the combination. “A prior art reference that ‘teaches away” from the claimed invention is a significant factor to be considered in determining obviousness”. MPEP 2145.X.D.1. “It is improper to combine references where the references teach away from their combination.” MPEP 2145.X.D.2. Using these legal standards, each of the substantive rejections in the Office Action is addressed below in the order they were presented in the Office Action. B. Rebuttal of Rejection of Claims 1-6, 11-13, and 20-24 over Farmwald ‘037 for Double Patenting Claims 1-6, 11-13, and 20-24 stand rejected over Farmwald ‘037 for obviousness-type double patenting. Patent Owner respectfully traverses. Obviousness-type double patenting is a judicially-created doctrine designed to prevent unjustified extension of the patent term. “A nonstatutory obviousness-type double patent rejection is appropriate where the conflicting claims are not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claimn(s).” MPEP 804.B.1. “An obviousness rejection must make clear [t]he differences between the inventions defined by the conflicting claims—a claim in the [prior] patent compared to a claim in the [patent under examination].” MPEP 804 (emphasis added). Therefore, to make an obviousness-type double -10-