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Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–2 Sampledvalue representation (quantization) of the analog quantity in Figure 1–1. Each value represented by a dot can be
digitized by representing it as a digital code that consists of a series of 1s and 0s.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–3 A basic audio public address system.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–4 Basic block diagram of a CD player. Only one channel is shown.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–5 Logic level ranges of voltage for a digital circuit.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–6 Ideal pulses.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–7 Nonideal pulse characteristics.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–8 Examples of digital waveforms.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–9
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–10 Example of a clock waveform synchronized with a waveform representation of a sequence of bits.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–11 Example of a timing diagram.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–12 Illustration of serial and parallel transfer of binary data. Only the data lines are shown.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–13
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–14
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–15 The basic logic operations and symbols.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–16 The NOT operation.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–17 The AND operation.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–18 The OR operation.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–19 The comparison function.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–20 The addition function.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–21 An encoder used to encode a calculator keystroke into a binary code for storage or for calculation.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–22 A decoder used to convert a special binary code into a 7segment decimal readout.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–23 Illustration of a basic multiplexing/demultiplexing application.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–24 Example of the operation of a 4bit serial shift register. Each block represents one storage “cell” or flipflop.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–25 Example of the operation of a 4bit parallel shift register.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–26 Illustration of basic counter operation.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–27 Cutaway view of one type of fixedfunction IC package showing the chip mounted inside, with connections to input and
output pins.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–28 Examples of throughhole and surfacemounted devices. The DIP is larger than the SOIC with the same number of leads.
This particular DIP is approximately 0.785 in. long, and the SOIC is approximately 0.385 in. long.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–29 Examples of SMT package configurations.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–30 Pin numbering for two standard types of IC packages. Top views are shown.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–31 Programmable logic.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–32 Block diagrams of simple programmable logic devices (SPLDs).
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–33 Typical SPLD package.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–34 General block diagram of a CPLD.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–35 Typical CPLD packages.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–36 Basic structure of an FPGA.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–37 A typical ballgrid array package configuration.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–38 Basic configuration for programming a PLD or FPGA.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–39 Basic programmable logic design flow block diagram.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–40 A typical dualchannel oscilloscope. Used with permission from Tektronix, Inc.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–41 Comparison of analog and digital oscilloscopes.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–42 Block diagram of an analog oscilloscope.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–43 Block diagram of a digital oscilloscope.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–44 A typical dualchannel oscilloscope. Numbers below screen indicate the values for each division on the vertical (voltage)
and horizontal (time) scales and can be varied using the vertical and horizontal controls on the scope.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–45 Comparison of an untriggered and a triggered waveform on an oscilloscope.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–46 Displays of the same waveform having a dc component.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–47 An oscilloscope voltage probe. Used with permission from Tektronix, Inc.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–48 Probe compensation conditions.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–49
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–50 Typical logic analyzer. Used with permission from Tektronix, Inc.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–51 Simplified block diagram of a logic analyzer.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–52 Two logic analyzer display modes.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–53 A typical multichannel logic analyzer probe. Used with permission from Tektronix, Inc.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–54 Typical signal generators. Used with permission from Tektronix, Inc.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–55 Illustration of how a logic pulser and a logic probe can be used to apply a pulse to a given point and check for resulting
pulse activity at another part of the circuit.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–56 Typical dc power supplies. Courtesy of B+K Precision.®
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–57 Typical DMMs. Courtesy of B+K Precision.®
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–58 Simplified basic block diagram for a tabletcounting and bottling control system.
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–59
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–60
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–61
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–62
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–63
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.
Figure 1–64
Thomas L. Floyd Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Digital Fundamentals, 9e All rights reserved.