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r059210203 Switching Theory Logic DesignRatings:

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(1)|Views: 724|Likes: 12Published by Srinivasa Rao G

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https://www.scribd.com/doc/1910370/r059210203-Switching-Theory-Logic-Design

09/28/2010

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Code No: R059210203

Set No. 1

II B.Tech I Semester Supplementary Examinations, February 2007SWITCHING THEORY & LOGIC DESIGN( Common to Electrical & Electronic Engineering, Electronics &Instrumentation Engineering, Bio-Medical Engineering, Electronics &Control Engineering, Electronics & Computer Engineering andInstrumentation & Control Engineering)Time: 3 hours Max Marks: 80Answer any FIVE QuestionsAll Questions carry equal marks

⋆⋆⋆⋆⋆

1. (a) Perform the following using BCD arithmetic. Verify the result. [2

×

4 = 8]i. 1273

10

+ 9587

10

ii. 7762

10

+ 3838

10

(b) Convert the following. [4

×

2 = 8]i. 977

10

= ( )

16

ii. 657

10

= ( )

8

iii. 754

10

= ( )

2

iv. 1001

16

= ( )

10

2. (a) Draw the NAND logic diagram that implements the complement of the fol-lowing function. [8]F(A,B,C,D) = Σ (0,1,2,3,4,8,9,12)(b) Obtain the complement of the following Boolean expressions.i. AB+A(B+C)+B’(B+D)ii. A+B+A’B’C [4](c) Obtain the dual of the following Boolean expressions.i. A’B+A’BC’+A’BCD+A’BC’D’Eii. ABEF+ABE’F’+A’B’EF [4]3. (a) Reduce the following function using K- map and implement it in AOI logic aswell as NOR logic F=

M

(0

,

1

,

2

,

3

,

4

,

7) [10](b) What do you mean by K-map? Name its advantages and disadvantages [6]4. (a) Implement the following Boolean function using 8:1 multiplexer.

f

(

ABCD

) =

m

(0

,

2

,

4

,

6

,

8

,

10

,

12

,

14)

f

(

ABCD

) =

m

(2

,

4

,

5

,

7

,

10

,

14)(b) Explain how to use decoder as a demultiplexer. [6+6+4]5. Write a brief note on:(a) Architecture of PLDs(b) Capabilation and the limitations of threshold gates. [8+8]1 of 2

Code No: R059210203

Set No. 1

6. (a) Find a modulo-6 gray code using k-Map & design the corresponding counter.(b) Compare synchronous & Asynchronous. [10+6]7. A clocked sequential circuit is provided with a single input x and single output Z.Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of thesequence it produce an output Z = 1 and overlapping is also allowed.(a) Obtain State - Diagram.(b) Also obtain state - Table.(c) Find equivalence classes using partition method & design the circuit using D- ﬂip-ﬂops. [4+4+8]8. (a) Draw the ASM chart for the following state transistion, start from the initialstate

T

1

, then if xy=00 go to

T

2

, if xy=01 go to

T

3

, if xy=10 go to

T

1

, otherwise go to

T

3

.(b) Show the exit paths in an ASM block for all binary combinations of controlvariables x, y and z, starting from an initial state. [8+8]

⋆⋆⋆⋆⋆

2 of 2

Code No: R059210203

Set No. 2

II B.Tech I Semester Supplementary Examinations, February 2007SWITCHING THEORY & LOGIC DESIGN( Common to Electrical & Electronic Engineering, Electronics &Instrumentation Engineering, Bio-Medical Engineering, Electronics &Control Engineering, Electronics & Computer Engineering andInstrumentation & Control Engineering)Time: 3 hours Max Marks: 80Answer any FIVE QuestionsAll Questions carry equal marks

⋆ ⋆ ⋆ ⋆ ⋆

1. (a) Explain, How error occurred in a data transmission can be detected usingparity bit. [6](b) Perform the subtraction with the following unsigned binary numbers by takingthe 2’s complement of the subtrahend. [5

×

2 = 10]i. 111011 - 111000ii. 1110 - 110110iii. 10010 - 1101iv. 110 - 10100v. 11011 - 100002. (a) Reduce the following Boolean expressions. [8]i. AB’(C+BD)+A’B’ii. A’B’C+(A+B+C’)’+A’B’C’Diii. ABCD+AB(CD)’+(AB)’CDiv. (A+A’)(AB+ABC’)(b) Obtain the complement of the following Boolean expressions. [8]i. ABC+A’B+ABC’ii. (BC’+A’D)(AB’+CD’)iii. x’yz+xziv. xy+x(wz+wz’)3. (a) Write short note on prime implicant chart.(b) Minimize following function using Tabular minimization.F (A, B, C, D) =

m

(6

,

7

,

8

,

9) +

d

(10

,

11

,

12

,

13

,

14

,

15). [4+12]4. (a) Realize Full Adder Using two half adders and logic gates.(b) Draw the block diagram of BCD adder using two 4-bit parallel binary addersand logic gates. [4+12]5. Write a brief note on:(a) Architecture of PLDs1 of 2

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