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Microprocessors and Interfacing r05220504

Microprocessors and Interfacing r05220504

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09/08/2009

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Code No: R05220504
Set No. 1
II B.Tech II Semester Regular Examinations, Apr/May 2007MICROPROCESSORS AND INTERFACING( Common to Computer Science & Engineering, Information Technologyand Computer Science & Systems Engineering)Time: 3 hours Max Marks: 80Answer any FIVE QuestionsAll Questions carry equal marks
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1. (a) Draw the internal architecture of 8085? Explain each block.(b) What are the special functions of GPRs in 8086? And explain them? [8+8]2. Explain clearly with examples the following 8086 instructions. [16](a) REP prefix(b) XLAT(c) IN and OUT(d) MOV(e) ADD AX, ES:[SI](f) PUSH.3. (a) Consider a string of characters stored in STRING through STRING+99. Sup-pose that bit 5 of register DL is to be set to 1 if the string contains a digit;otherwise this bit to be set to zero .In any case only bit 5 is to be affected.Draw a flow chart of the problem and implement it in assembler language.(b) Write a program sequence for interchanging the contents of two locations.[8+8]4. (a) With a neat sketch explain 8237 DMA controller and its operation?(b) With the help of basic cell explain SRAM and DRAM? [8+8]5. (a) What is sensor matrix mode of 8279? Describe the function of the 8x8-bitRAM in the sensor matrix mode.(b) Interface the keyboard and display controller 8279 with 8086 at address ABC0H.Write an ALP to set up 8279 in scanned keyboard mode with encoded scan,N-key rollover mode. Use 16-character display in right entry display format.[8+8]6. (a) What is the purpose of operational command words of 8259? Explain theirformat and the use.(b) Draw and explain the interrupt acknowledge cycle of 8086. [8+8]7. (a) Explain the operation of 8251 in Asynchronous mode of communication.(b) How TTL to RS-232C and RS-232C to TTL conversions are achieved? [8+8]1 of 2
 
Code No: R05220504
Set No. 1
8. An 8051 based system requires external memory of four 8 K bytes of SRAM eachand two chips of EPROM of size 4 K bytes. The EPROM starts at address 1000H.SRAM address map follows EPROM map. Give the complete memory interface.[16]
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Code No: R05220504
Set No. 2
II B.Tech II Semester Regular Examinations, Apr/May 2007MICROPROCESSORS AND INTERFACING( Common to Computer Science & Engineering, Information Technologyand Computer Science & Systems Engineering)Time: 3 hours Max Marks: 80Answer any FIVE QuestionsAll Questions carry equal marks
⋆⋆⋆⋆⋆
1. (a) How does 8086 manage, when the instruction pointer pointing to the nextinstruction asking for branching?(b) Write a note on interrupt handling in 8086.(c) Draw the maximum mode conguration of 8086. [4+6+6]2. (a) Write a program to move a block of memory with out over lapping.(b) Discuss the following instructions. [8+8]i. ADCii. AASiii. IMULiv. CBW.3. Write a FAR procedure SER WORD that searches a word array for a given wordand sets the value of a word parameter to the index of the element in the arrayif a match is found; otherwise, it puts a -1 in the index word parameter. Theparameters are to be passed to the procedure via a parameter address table. Givea sequence for calling SER WORD to search ARRAY1 of length LENGTH1 forvariable ID? and put the index in INDEDX 1? [16]4. (a) How DRAM’s are different from SRAM’s? Why DRAMs are said to employaddress multiplexing?(b) What are the conditions that will cause EU to enter a ‘Wait State’?(c) What logic levels would you find on
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:i. When an 8086 is writing a byte to the memory address 04032H,ii. When it is writing a word to the memory address 04032H. Also, describethe 8086 bus operations required to write a word at memory address04031h. [4+4+8]5. (a) Explain the methods for excitation of stepper motor.(b) Interface stepper motor with 8086 microprocessor system and write an assem-bly language program to rotate it by 180
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. [8+8]6. (a) Describe the response that an 8259 will make if it receives an interrupt signalon its IR3 and IR5 inputs at the same time. Assume fixed priority for the IRinputs. What response will the 8259 make if it is servicing an IR5 interrupt,and an IR3 interrupt signal occurs.1 of 2

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