ECE 428 Programmable ASIC Design

Fundamentals of Digital IC Design

Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901

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Semiconductor Devices
Bipolar Transistors:
c
N

b
P
N

e
NPN transistor

Junction Field Effective Transistor (JFET):

N-channel FET

S
P
N P

Metal-Oxide-Semiconductor (MOS) Devices:

B
P+

G G D
N+
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Metal N+

NMOS Device

P-

CMOS Process
Cross-Section Diagram

Layout

Source from http://infopad.eecs.berkeley.edu/~icdesign For a great tour of IC fabrication process, see http://www.fullman.com/semiconductors/semiconductors.html
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Digital Signals and Basic Logic Gates

Digital signal values
True 1 High Voltage (e.g. 5V)12

False

Low Voltage (e.g. 0V)

Basic logic gates

1. Inverter
X X Y 0 1 Z 0 0 0 1 Truth Table of an AND gate Truth Table of an inverter

Y=X

1 0 X Y 0 1 0 1

2. AND

X Y

Z=XY

3. NAND

X Y

Z=XY

0 0 1 1

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Basic Logic Gates

X Y 0 1 0 1 Z 0 1 1 1

4. OR

X Y

Z=X+Y

5. NOR

X Y

0 0 1 1

Truth Table of an OR gate

Z=X+Y

Y 0 1 0 1

Z 0 1 1 0

4. XOR

X Y

Z = XY +XY Z=X+Y

0 0 1 1

Truth Table of an XOR gate

5. XNOR

X Y

Z = XY +XY Z=X+Y
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Basic Logic Gates

Tri-state Buffer
C I C I X 0 1 O Z 0 1
Truth table of a tri-state buffer

1 0 0

I1
O I2 S Mux C X Y

2-to-1 multiplexer

Bi-direction circuit
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Gate Delay Definition

Vout

Vin
50% Vin Vout 90% 90% 50% 50% 10% 50%

tpHL

tpLH

10%

tf

tr
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Sequential Logic Circuits

D latch
D CLK Q D CLK Q When CLK=1, Q always reflects the signal value at input D If CLK=0, Q stores the last D value which appears at D just before CLK falls to 0

D Flip-flop
D CLK Q Q D CLK Q D flip-flop will not change its output values unless there is a negative edge event at CLK input (CLK switches from logic 1 to 0). When a negative edge appears at CLK input , D Flip-flop updates Q to the current D value
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Timing Parameters for D Flip-Flops

Clock-Q Delay
D D Q CLK Q DFF Clock-Q delay

CLK

Setup Time
D CLK Setup time

Hold time
D CLK Hold time
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Decoder Circuits
A decoder circuit uniquely selects one of its outputs according to its
input signals

N inputs

Decoder

2N outputs

2-to-4 decoder implementation

X X Y Z1 Z2 Z3 Z4 Z1 (00) Z2 (01)

0 0 1 1

0 1 0 1

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

Z3 (10)
Z4 (11)
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Decoder Circuit
3-to-8 decoder implementation
Assume that we have 2-to-4 decoders available as standard components When CS is low (0), all the outputs of the decoder are low (0)
X Y Z
X
Y CS X Y CS

X
Y CS

2-to-4 decoder

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Sequential Logic Circuits

Counter
Basic binary counter
A
DFF Q D Q DFF Q D Q

Clk
B
DFF Q D Q

C 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

Init.

CLK

Synchronous counter
A B C

DFF Q D Q

DFF Q D Q

Q Q

CLK 2-12

Sequential Logic Circuits

frequency divider
Divide clock frequency by 4
DFF Q D Q DFF Q D Q

CLK CLK_4 CLK_4

CLK

Divide clock frequency by 3

DFF Q D Q

DFF Q D Q

CLK CLK_3 CLK_3

CLK

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Sequential Logic Circuits

Register
A row of storage elements (e.g. D flip-flops)
Q3
DFF Q D Q DFF Q D Q

Q2
DFF Q D Q

Q1
DFF Q D Q

Q0

Q[3:0]

Data CLK

Shift register
Q3 0 CLK
DFF Q D Q
DFF Q D Q

Q2
DFF Q D Q

Q1
DFF Q D Q

Q0

CLK

Q3

Q2

Q1

Q0

Init.

1 0 0 0 0

0 1 0 0 0

1 0 1 0 0

0 1 0 1 0
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Major Parasitic Effects in Digital ICs

Ideal Circuit
Vin
Vin Interconnect Vout Vout No delay!

Real Circuit
C

Vin
C C C C

Vin
C

Vout Vout Significant delay!

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Power Consumption of CMOS Gates

Dynamic Power Consumption
Vin
Id
Vout

ISC

C
2 PDynamic 0.5 C VDD f

Short-Circuit Power Consumption

ISC

PSC I SC (t )Vdt

Vin

Leakage Power Consumption

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Transistor Sizing

C
C C C

Delay

Power

Silicon area

Driver Size

Driver Size

Driver Size
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Design Constraints for Digital ICs

Vin1 Vin2 Vin3 CLK

Circuit Under construction

Vout1
Vout2

Delay (speed) constraints

For example, the delay from Vin1 to Vout1 should be smaller than 10 ns; the clock frequency should be greater 100MHz

Power constraints Area constraints

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How to Find Circuits Complying with Design Constraints

Full-custom approach Standard-cell based approach Gate-array approach FPGA approach 1. 2. It heavily depends on designers expertise. Finding a proper circuit implementation can be very time consuming. Very creative circuit implementations can be achieved. 1. These approaches heavily use design automation techniques to search circuits complying with constraints. They are time saving approaches. These approaches require pre-developed technology libraries. The quality of the final implementation depends on algorithms and libraries used in the search.
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3.

2. 3.

4.

Example: How to Search a Proper Circuit Implementation in FPGA Design Flow

FPGA Design Flow
Schematic Capture
netlist FPGA cell library Fail Verification Pass Generate FPGA Bit Stream FPGA
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HDL coding & Logic Synthesis

Implementation

Technology mapping Placement & routing Timing verification

Download

Example: How to Search a Proper Circuit Implementation in FPGA Design Flow

Given Logic Function
This circuit is either from schematic capture or from logic synthesis

a b

FPGA Library Components

The library contains five components Three inverters at size 1, 3, 5 Two two-input NAND gates at size 1 and 3

Design Constraints
The maximum delay between an input and an output should not exceed 5 ns

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Example: How to Search a Proper Circuit Implementation in FPGA Design Flow

Step 1: Use the available logic gates to implement the given function. (Technology Mapping)
INV1

a b
INV2

NAND1

e
NAND2

c
INV3

Step 2: Select proper size for each gate used in the above circuit. (Gate Sizing) 1X
After this step, the circuit can be simulated to verify that it complies with timing constraints. b In the simulation, the parasitic capacitance and resistance on c interconnects are estimated (Estimated wire load)

3X

d
1X 3X

e
1X
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Example: How to Search a Proper Circuit Implementation in FPGA Design Flow

Step 3: Determine where to place these gates and how to connect them (Placement & Routing).
Some algorithms first place the components and then route the interconnects. Some algorithms perform the placement and routing simultaneously

INV1

NAND1

NAND2

INV2

INV3

Steps 1, 2, and 3 are included in the implementation phase of the FPGA design Flow

Step 4: Perform post-layout simulation to verify that the generated circuit complies with timing constraints
Since detail information of each interconnect is available, the circuit can be simulated with accurate wire load. The process that writes the accurate wire load into the circuit netlist is called back annotation 2-23

What Information Should Be Stored in FPGA Library

Logic function

Timing (delay) information

Power consumption information Silicon area

Layout information
Placement & routing constraints

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Example: How to Store Delay Information

Normally, the delay of gate is proportional to the load on its output
Delay K D0 Load Delay = D0 + K*Load So, we can store two parameters (D0 and K) for each gate to model its delay property.
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Binary Number System

Converting binary numbers to decimal numbers
Binary 1011 0111 1*2^3 + 0*2^2 + 1*2^1 + 1*2^0 0*2^3 + 1*2^2 + 1*2^1 + 1*2^0 Decimal = 11 = 7

Converting binary numbers to hexadecimal numbers

1 1 1 1 0 1 0 1 1 0 1 0 0 0 1 1 F 5 A 3

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Binary Addition
Example
0 1 0 1 + 1 0 0 1 1 1 1 0
C_in

A single-bit full adder

A B

Full adder

C_out

4-bit adder
A[0] B[0] C_in
Full adder

A[1] B[1]
Full adder

A[2] B[2]
Full adder

A[3] B[3]
Full adder

C_0

C_1

C_2

C_out

S[0]

S[1]

S[2]

S[3]
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Handling Negative numbers

Signed magnitude
The left-most bit is a sign bit 0 indicates positive a number and 1 indicates negative a number
Signed magnitude Decimal

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 2 3 0 -1 -2 -3
Decimal

Ones complement
For positive number A, it is
represented as usual binary number

1s complement

For negative number -A, its

representation is obtained by flipping the bits of the binary representation of A

0 0 0 0 1 1 1 1

0 0 1 1 1 1 0 0

0 1 0 1 1 0 1 0

0 1 2 3 0 -1 -2 -3
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Handling Negative numbers

Twos complement
For positive number A, it is the
same as the ones complement
2s complement Decimal

For negative number A, add one

to the ones complement representation

0 0 0 0 1 1 1 1

0 0 1 1 1 1 0 0

0 1 0 1 1 0 1 0

0 1 2 3 -1 -2 -3 -4

By using twos complement number representation, minus operations can be performed by adders
3 1 2
Overflow Ignore

0 1 1 1 1 1

2 3 -1

0 1 0 1 0 1 1 1 1 -1
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1 0 1 0 2