ECE 428 Programmable ASIC Design

FPGA Microprocessor
Part 1

Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901

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Microprocessor v.s. ASIC

For a given function, we can implement it by using a general purpose microprocessor or by designing an ASIC Microprocessor
1. General purpose 2. Flexible and easy to update by loading new software 3. Typically, the performance is not optimized for a given task

ASIC
1. Application specific 2. Less flexible and almost impossible to Update unless the ASIC contains programmable circuits 3. Normally, optimal performance

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How Does A Microprocessor Work?

First, an instruction is fetched into the microprocessor Second, the instruction is decoded for execution Finally, the instruction is executed.
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Advantages of FPGA Microprocessors

The architecture of FPGA microprocessor can be easily modified to achieve
optimal performance for a given application.

Example: calculate Y = AX2 + BX + C

FPGA

General purpose microprocessor

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Introduction to GNOME Microprocessor

0 3 R15 R14 7

Data : Instruction : Data RAM : Instr. RAM :

4 bits 8 bits 16 X 4 128 X 8

Data Memory

data[7:0] FPGA microprocessor

C ACC Z

R1 R0

addr [14:0] 32Kx8 Memory csb web

oeb

Inst [127] Inst [126]

C : Carry flag Z : Zero flag ACC : Accumulator Register [3:0]

Instruction memory

Inst [1] Inst [0] 14-5

Instructions of GNOME Microprocessor

Mnemoni c Operation Description

load Rd

ACC Rd
ACC d Rd ACC

Load the accumulator with the contents of the

memory location whose address is d.

loadi d store Rd

Load the accumulator with the immediate data d Store the value in the accumulator into RAM location Rd.

add Rd

ACC ACC+Rd+C Add the content of RAM location Rd and the C flag to the Accumulator.

addi d xor Rd

ACC ACC+d+C ACC ACC Rd Z ACC Rd

Add the value d and the C flag to the accumulator. EXCLUSIVE-OR the content of RAM location Rd with the Accumulator.

test Rd

AND the contents of RAM location Rd with the accumulator, but do not store the results in the 14-6 accumulator. Instead, set the Z flag if the result is 0,

Instructions of GNOME Microprocessor

Mnemoni c Operation Description

clear_c
set_c skipc

C0
C1 PC PC+1+C

Clear the C flag to zero.

Set the C flag to one. If C=1, skip the next instruction by incrementing the program counter by two instead of one. Otherwise, execute the next instruction If Z=1, skip the next instruction by incrementing the program counter by two instead of one. Otherwise, execute the next instruction Jump to program address a and execute instructions from address a. a is an address in the range [0..127]

skipz

PC PC+1+Z

jump a

PC a

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Instruction Encoding
Instruction Format
Fixed length instructions (8 bits) Each instruction can have one or zero operand
7 0

Opcode
3 0

clear_c

set_c

load Rd, loadi d, store Rd, add Rd, addi d,

Opcode
6
Opcode

Operand
0

xor Rd, xori d, test Rd, testi d

address

jump a

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Instruction Encoding
Mnemonic load Rd loadi d store Rd add Rd addi d xor Rd test Rd clear_c set_c Encoding 0 1 0 0 d 3 d2 d1 d0 0 0 0 1 d 3 d2 d1 d0 0 0 1 1 d 3 d2 d1 d0 0 1 0 1 d 3 d2 d1 d0 0 0 1 0 d 3 d2 d1 d0 0 1 1 0 d 3 d2 d1 d0 0 1 1 1 d 3 d2 d1 d0 00 0 0 0 0 0 0 00 0 0 0 0 0 1 Comment d3 d2 d1 d0 is the address of RAM location d3 d2 d1 d0 is the immediate data d3 d2 d1 d0 is the address of RAM location d3 d2 d1 d0 is the address of RAM location d3 d2 d1 d0 is the immediate data d3 d2 d1 d0 is the address of RAM location d3 d2 d1 d0 is the address of RAM location

skipc

00 0 0 0 0 1 0
00 0 0 0 0 1 1 1 a6 a5 a4 a3 a2 a1 a0 a6 a5 a4 a3 a2 a1 a0 is the new instruction address
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skipz
jump a

Operation of GNOME Microprocessor

Execution of a single instruction

Fetch
1. Fetch instruction 2. Update PC register

Decoding
1. Decode instruction 2. Fetch operand if it is needed

Execution
1. Execute the instruction

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GNOME Block Diagram

clk clk rst alu_op(2:0) sel_data_ram write read ld_ir ld_ir_lsn inc_pc jump_pc rst curr_ir(7:0) data(7:0) sel_data_ram addr(14:0) write read ld_ir ld_ir_lsn curr_acc(3:0) curr_pc(6:0) csb web oeb

curr_ir(7:0) curr_carry curr_zero

data(7:0) addr(14:0) csb web oeb

FSM & decoder

Fetch

clk rst curr_ir(7:0) clk rst alu_op(2:0) curr_ir(7:0) curr_acc(3:0) inc_pc curr_carry curr_zero jump_pc

curr_pc(6:0)

datapath clk rst

U5
d(3:0) s(6:0)

addgen s(6:0)

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leddcd

Address Generation

If inc_pc = 1, the adder output goes to the input of the register (for normal instruction address update and skipz and skipc instructions).

If jump_pc =1, curr_ir goes to the input of

the register (for jump instruction)

If jump_pc =0 and inc_pc=0,

the output of the register goes to the input of the register. and inc_pc=1 at the same time.

It is prohibited to have jump_pc =1

After reset, curr_pc=0. Thus, the microprocessor

fetches the first instruction from address 000000

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Instruction Latch & Data Bus Circuits

For write operation (store rd), the write buffer is on and data on curr_acc are written into memory. During other time, the write buffer is off (high impedance output) To fetch an instruction, both muxs pass the data on the data bus to the instruction register To fetch data from data RAM, only the least significant mux passes the pass the data on the data bus to the instruction register

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Control & decoding Unit

Reset Fetch
reset set D Q D reset Q D reset Q

DFF

DFF

DFF

Execution

Decoding

clock

curr_ir

Current state
Curr_zero Curr_carry

Combinational circuits for instruction decoding and generating control signals

Control signals

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Control & decoding Unit

Example: how generate control signal write
write signal should be driven to high to enable the write buffer during the execution state of store rd instructions write = exe_state AND store_instruction 1. 2. Signal exe_state is high when GNOME is during execution states Signal store_instruction is high if the current instruction is store rd

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Execution Unit
Accumulator-Based Architecture
B
Cin Cout

ALU operations
Name Operation Encoding

PASS

ACC B
ACCACC+B+Cin ACC ACC B

001
010 011

ACC

ADD XOR

AND

Zero flag = ACC B

Set carry flag Clear carry flag

100
101 110

For operations with two operands, one operand is accumulator. The execution result is store in
accumulator

SET_C CLR_C

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ALU Circuit

alu_op[1]

alu_op[0]

Operation
PASS

0
1 1

1
1 0

XOR ADD*

* Extra circuits are needed for carry generation

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Complete ALU Circuit

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Programming GNOME Processor

Example: writing a program to calculate 48H + 29H
Instructions
Loadi Store Loadi Store Loadi Store Loadi Store Clear_c Load Add Store Load Add Store 8 R0 4 R1 9 R2 2 R3 R0 R2 R4 R1 R3 R5

Machine code
18H 30H 14H 31H 19H 32H 12H 33H 00H 40H 52H 34H 41H 53H 35H
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Put Everything Together

Reset

Connect to Ext. Data Bus

Execution

Fetch

Decoding

Instruction Decoding & Control logic

Connect to Ext. Addr. Bus

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