FIFO Chip Design Example

EE166 SJSU David Parent

EE166 FIFO Example 1

FIFO Example
We will now try to put together the concepts of:
Cell based design Super Buffer Clock trees IP reuse Getting a chip into a Pad frame

FIFO
Simple, Regular
EE166 FIFO Example 2

Getting Started
The first thing we must do is decide the pins in an actual pad frame with the package. This will give us the context we need to make intelligent decisions about routing.

EE166 FIFO Example

MOSIS Pad frame

The stand tiny chip from MOSIS can support 40 pins. You need to start with the pin out of the actual packaged chip to make the part useable and testable. We will use pin 1 as VDD and 21 as GND as a standard. This inputs will come in the top (2-20) and out puts in general will be out the bottom (21-40) We will choose pin 2 for CK, 3 for NPRE and 4 for NCLR A0-A15 will map to pins 5-20. Y0-Y15 will map to pins 40-25.

EE166 FIFO Example

Packaged Part
Pin# Pin Name Pin# Pin Name 1 VDD 40 Y0 2 CK 39 Y1 3 NPRE 38 Y2 4 NCLR 37 Y3 5 A0 36 Y4 6 A1 35 Y5 7 A2 34 Y6 8 A3 33 Y7 9 A4 32 Y8 10 A5 31 Y9 11 A6 30 Y10 12 A7 29 Y11 13 A8 28 Y12 14 A9 27 Y13 15 A10 26 Y14 16 A11 25 Y15 17 A12 24 UNUSED 18 A13 23 UNUSED 19 A14 22 UNUSED 20 A15 21 GND

Note: I will not fab a part without the pins list!

EE166 FIFO Example 5

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DP40 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Sample Pad frame

Area inside is 895m by 895m.
pin 21 pin 1

You can get more area buy using less pins. (Read Data in serially?) You can have larger circuits but they use up more MOSIS money

EE166 FIFO Example

Bonding Diagram

This goes in the package.

EE166 FIFO Example

How big a FIFO can we make?

Our DFF is 72m x 36m in area A MOSIS tiny chip gives you about 900m x 900m of space Assume that we can only use the space.
This can be increased if you use less than 40 pads. Number of rows 450/36 gives 12 Number of columns 900/72 gives 12
EE166 FIFO Example 8

Saving Space

We could get rid of not clock by adding an inverter and save 3m.

We could overlay the clock and reset signals and save 10m.

We could overlay the ground wires and save 3 m.

EE166 FIFO Example 9

Trade offs
Replacing not clock with an inverter.
New Cell Height 33 (450/33 gives 13) New Cell Width 72+8 (900/ gives 11) Routing is easier Do not have to worry about skew between not clock and clock Will the power go up?
Maybe. You would need another super buffer to drive not clock. In this case you only need one.
EE166 FIFO Example 10

Trade offs
Overlay the reset and clock signals
New average Cell Height 31 (450/31 gives 14) No New Cell Width Need two DFF parts one flipped with different wiring to the global signals one unchanged
We already need two type of FF one with D and not D and the other with D input only. This would make 4 different FF!
EE166 FIFO Example 11

Trade offs
Overlay the ground signals
New average Cell Height 34.5 (450/34.5 gives 13) No New Cell Width Electro migration?

Nothing works!
We have to try it all! Still only 15 wide! We could shrink height by 3m which would give us 16 bits wide but then AOI logic would not fit into the cell height. We beg the senior engineer for 50m more space.
EE166 FIFO Example

12

40 min

20 min

4 DFFs
5 min
Not D Internal Not D External Routing UP DFF_DI_RU DFF_DE_RU Routing Down DFF_DI_RD DFF_DE_RD

7 min

All The FFs need to have the Not clock removed! Need to have to verify 4 new parts from one old part! This will take some time! No choice. New Average Cell Height 31.375 16 bits high will give less than 500 microns so it it will fit in the expanded space.
EE166 FIFO Example 13

Derivative DFF Design

I really saved some time by reusing the same template. It also helped that my NAND3 was designed to have flexible routing, rather than minimum area.
Time 45 40 35 Time (Mins.) 30 25 Time 20 15 10 5 0 0 1 2 DFF Design 3 4 5

EE166 FIFO Example

14

Not D Internal Routing Up

Not CK are provided by inverters to be added as required. Not D is generated by the NAND2 from D. Since we will not be operating at less than 1ns the increase setup time will not matter.

EE166 FIFO Example

15

CK

NCLR

NPRE

DFF_DI_RU

Use the nand as an inverter. Q QN

EE166 FIFO Example

16

DFF_DI_RD

CK NPRE NCLR
EE166 FIFO Example 17

DFF_DE_RU

EE166 FIFO Example

18

DFF_DE_RU

D ND

EE166 FIFO Example

19

DFF_DE_RD

D ND

Q QN

EE166 FIFO Example

20

DFF_INV

EE166 FIFO Example

21

Design Review
After looking at the parts so far it looks like there could be an electro migration problem where the VDD is bought into the circuit
Since all the FF use the same basic parts, We just have to fix it once in each cell. You can even edit it in place! I had to flatten the NTAP to do this. I had to add some nwell due to a DRC error.
EE166 FIFO Example 22

New DFF Structure

EE166 FIFO Example

23

Back to the FIFO

We can fit 16 bits high within 500 microns We can fit 900/80 long (11) We can do a FIFO 10 bits deep. We will use 16 x 10 DFF (160)
8 DFF_DI_RU 8 DFF_DI_RD 72 DFF_DE_RU 72 DFF_DE_RD
EE166 FIFO Example 24

Gut check on power

160 DFF
Each one has 21 NMOS and 21 PMOS
This is like having 21 inverters Total number of inverters is 3360 (6720 transistors) The power for one inverter at 30 Mhz is

The power for an alfa of one and 3360 Inverters is 58mW We know that not all transistors do not switch every clock cycle so this is an upper bound.
EE166 FIFO Example 25

30 MHz! What happened to 200MHz?

With no PLL and the data coming from off chip the maximum clock rate and off chip speed is about 30 MHz! One could design special output buffers but these are tricky and would use more power! We will continue to test at a higher speed because the simulation will go faster! For the final pin to pin simulation we will have to simulate at 30 MHz for at least 20 clock periods.
EE166 FIFO Example 26

FIFO Schematic

Start off with the basic structure that can be copied and pasted.

EE166 FIFO Example

27

FIFO Schematic

Hard to see!

EE166 FIFO Example

28

FIFO Schematic Complete

EE166 FIFO Example

29

FIFO Symbol

EE166 FIFO Example

30

Verilog takes less than a second to verify.

EE166 FIFO Example

31

Verilog Test bench

EE166 FIFO Example

32

Spice Test Bench

EE166 FIFO Example

33

Input Vectors

EE166 FIFO Example

34

Input Vectors

EE166 FIFO Example

35

Input Vectors

EE166 FIFO Example

36

Output

EE166 FIFO Example

37

Output

EE166 FIFO Example

38

Spice Summary
The circuits has been validated The simulation took about 10 minutes to run!

EE166 FIFO Example

39

Set up The first 4 FF

Layout

Pre Rout CK NPRE and NCLR

Then make it 10 across

EE166 FIFO Example

40

Layout with only cells

EE166 FIFO Example

41

Route VDD and Ground

EE166 FIFO Example

42

VDD

GND

Final FIFO Layout

DATA FLOW

EE166 FIFO Example

43

Final Layout Verification

EE166 FIFO Example

44

Post Extraction Simulation

EE166 FIFO Example

45

Modify a Pad frame

The parts we need are: input buffer (padinc) output buffer (padio) corners (fc) VDD pad (padvdd) GND pad (paddgnd) You can FTP a sample pad frame from mosis: http://www.mosis.org/Technical/Designsupport/pad-libraryscmos.html The Docs are there as well.
EE166 FIFO Example 46

Sample Padframe
Load in a sample padframe. To change a pin just select it and press q for edit, and then change the same to what you want.

EE166 FIFO Example

47

Change Pin 21 from padinc to padgnd

padinc to padgnd

EE166 FIFO Example

48

Make sure pads abut.

correct But Metal 1 together and make sure the PSEL line is on he horizontal axis.

Not correct!

Pin 26
EE166 FIFO Example 49

Change pins 22-24 to unused

EE166 FIFO Example

50

FIFO_PF
After you make a padframe open up a new cell and add the the instance of your padframe. Then add pins.

EE166 FIFO Example

51

Finished pin

Create Pin Names

Do not use a global Variable for VDD and GND!

Use metal 3 input/output Use a width of 50

EE166 FIFO Example 52

Pin to Pin Test Bench

VDD and GND can not be global then have to be direct pins. The test bench and symbol are almost identical to to FIFO part
Copy the FIFO to a new cell called FIFO_PF Edit the symbol to add two ne pins VDD and GND which are in/out. Change the schematic accordingly.
EE166 FIFO Example 53

FIFO_PF Layout
Parts:
Super buffer for clock FIFO Padframe

Stamp them down and wire them up!

EE166 FIFO Example

54

PAD I/O
OEN: Output enable DO: sends output to pad DIB: inverts data coming from the pad DI: does not invert data coming in from the pad

OEN

DO

EE166 FIFO Example

DB

DI

55

PAD VDD/GND

GND

EE166 FIFO Example

56

Connect a metal 2 path 2.7u wide to DI

EE166 FIFO Example

57

DRC
The pads do not pass DRC. Pads are an exception to the rule, and these pads have proven themselves in the field. We have to do DRC on everything else.
Draw a Do not do DRC layer around the pads with the edge of the pads just over the metal 2 connection (We want to make sure we are connect right?)
EE166 FIFO Example 58

Do not DRC Layer

Put it just over the metal 2

EE166 FIFO Example

59

FIF0_PF Symbol

Rearrange ports to match chip.

Note: Delete the schematic view of the FIFO_PF.

EE166 FIFO Example 60

FIF0_PF_TB

EE166 FIFO Example

61

Simulation Trouble
I ran into some major trouble that took two days to fix.
The pad frame I had built was off a little bit It takes 3 minutes to extract and almost 10 minutes to simulation (Then you see an error.) That is almost 15 minutes to try each solution. Also the pad frame kept moving on me when I would inadvertently moved it when I was zoomed in on a small feature.
EE166 FIFO Example 62

Solutions
Start off with just the pad frame and just wire the input and outputs together and see if it acts like a buffer. Build the pad frame in the top most cell.
Put all the parts in the center. Select everything inside the pad frame and make it a cell. Edit the cell in place.

Do the shortest simulation possible to make sure everything is connected (Like a reset or set operation) You can probe the extracted wires by descend editing to the extracted view and selecting the wire you want. Get the pad frame working on its own in parallel with the circuit design.
EE166 FIFO Example 63

The rise time on the when NPRE goes low is 4ns! The output Y seems ok and since the circuit is supposed to work at 30 MHz I will not try to buffer the signal. This simulation ran for 8mins 40 secs to get 20ns

EE166 FIFO Example

64

EE166 FIFO Example

65

Analysis
Point A is when NCLR goes low thus changing the state of every FF (notice the power surge Point B is when NCLR goes high and the FIFO begins to fill Point C is when the all the FF are turning on at the same time. (Note the power surge.) We will take the average power from ~600 to 700ns, and average over 4 clock cycles. Average Power 305mW/4 gives 76mW
EE166 FIFO Example 66

Outputs Y15-Y8
10 Clock Cycles for Y to get A after NCLR goes high. A B

EE166 FIFO Example

67

Outputs Y7-Y0

EE166 FIFO Example

68

Inputs A15-A8

EE166 FIFO Example

69

Inputs A7-A0

EE166 FIFO Example

70

Final FIFO Layout

See how much area is taken up by routing!
D A T A

Super Buffer A0 NCLR NPRE CK VDD Y0

A15 GND

F L O W

Y15
EE166 FIFO Example 71

Statistics (Working alone in the middle of the summer)

FIFO_PF
DRC 55 seconds Extract 190s Quick simulation (20ns: 520s) Long 30MHz simulation (500ns: XXXs) Whole Chip 48 man hours.

EE166 FIFO Example

72

Design Statistics
DRC Extract Time to Simulation Design Part #Transistors Time Time Simulate time time DFF_INV 2 1 1 6 4 0.08333333 DFF 42 1 1 6 8 1.2 FIFO 6720 41 101 519 40 8 FIFO 9636 55 227 1949 720 24 CHIP

This does not include the time to write the documentation. The total project took somewhere between 40 to 60 hours. This means that documentation can take a lot of time. The numbers do not add up but one can easily see that the time required to complete a step goes up at the best linearly with # of transistors and at worst exponentially! EE166 FIFO Example 73 You need to plan accordingly!

DRC and Extract time vs. gate count

250

200

Time (s)

150 DRC Time Extract Time 100

50

0 0 2000 4000 6000 # Transistors 8000 10000 12000

EE166 FIFO Example

74

Simulation time vs. gate count

Time to Simulate 2500

2000

Time(s)

1500 Time to Simulate 1000

500

0 0 2000 4000 6000 8000 10000 12000 Number of transistors

EE166 FIFO Example

75

Design time vs. gate count

Chart Title 30 25 20 15 10 5 0 0 2000 4000 6000 # Transistors 8000 10000 12000 Design time Expon. (Design time) y = 0.3188e0.0005x R2 = 0.8082

Time(hours)

EE166 FIFO Example

76

How fast do I work?

Can you measure your output in transistors per hour?
#T/hour 900 800 700 600 500 #T/hour 400 300 200 100 0 DFF_INV DFF FIFO FIFO CHIP

EE166 FIFO Example

77

Design Review
Clock Rate:30MHz Power:76mW Area : 1500m x 1500m=2.25x106m Power Density:76mW/Area gives .33 3x10-7 W/m2 . No cooling required!
2.3x10-7 W/m2 no cooling 1.0x10-6 W/m2 with expensive cooling
EE166 FIFO Example 78

Lessons Learned
Design re-use is a faster method of design. Getting the circuit into a pad frame can take a large amount of time.
Get pad frame done before you need it.

Verilog simulation are very fast but give no timing data unless it is built in. The project will all ways take longer than expected! (even if you plan for it!)
EE166 FIFO Example 79