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How to Size Baulk Processing Power to CPU

How to Size Baulk Processing Power to CPU

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Published by Acharne Dokument
The simple days of computing: Sizing a computers CPU's was based on only one CPU's Hz, the amount of transistors and the L cache sizes of that CPU. All software written back in the 90's were centered on single thread processing (time-division multiplexing).
Now a single box computer is in reality multiple computers in one simply by the new technology of multi-threading (kernel threading) CPU technology.
The simple days of computing: Sizing a computers CPU's was based on only one CPU's Hz, the amount of transistors and the L cache sizes of that CPU. All software written back in the 90's were centered on single thread processing (time-division multiplexing).
Now a single box computer is in reality multiple computers in one simply by the new technology of multi-threading (kernel threading) CPU technology.

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Published by: Acharne Dokument on Jan 11, 2014
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How To Size Bulk Processing Power By CPU
The simple days of computing: Sizing a computers CPU's was based on only one CPU's Hz, the amount of transistors and the L cache sizes of that CPU. All software written back in the 90's were centered on single thread processing (time-division multiplexing). Now a single box computer is in reality multiple computers in one simply by the new technology of multi-threading (kernel threading) CPU technology.
Welcome to the Xeon E5Lvy Bridge EP.
Single 6c Die socket:
6 CPU's (a core is a CPU), 24 logical CPU's (a logical CPU is a software image of a core times 4), One L3 15M cache, one front side bus controller. Note: 3+ GHz for each CPU, bus speed based on 15M cache. Multitasking shared by 24 logical CPU'swith a 15M L buffer.* Size according to I/O speed of your outputs.** The horsepower of the software. ***
Single 10c Die socket:
10 CPU's(a core is a CPU), 40 logical CPU's (a logical CPU is a software image of a core times 4), One L3 25M cache, one front side bus controller. Note: 3+ GHz each CPU, bus speed increased by 25M cache. Note: 3.5 GHz for each CPU, bus speed based on 25M cache. Multitasking shared by 40 logical CPU's with a 25M L buffer.* Size according to I/O speed of your outputs.** The horsepower of the software. ***
 
Single 12c Die socket:
12 core (a core is a CPU), 48 logical CPU's (a logical CPU is a software image of a core times 4), Two L3 30M cache, two front side bus controllers. Note: 3+ GHz for each CPU, bus speed based on 30M cache. Multitasking shared by 48 logical CPU's with two 30M L buffer.* Size according to I/O speed of your outputs.** The horsepower of the software. *** *The larger the cache on the CPU the faster processor arrays regardless of the internal processor speed. L1 to L3 cache keeps copies of requested items in case a different core makes a subsequent request. The advantage of having on-
board cache is that it’s faster, more
efficient and less expensive than placing separate cache on the motherboard. **Size by bus Speed: I/O chipset bus speed (motherboard), hard drive access and bus speed (interface, SATA, SAS, RPM, buffer), physical memory RAM (DDR3) bus speed, EthernetMbps speed, video controller buffer size and speed. High priced, fast CPUs will only bottleneck on the backend thus wasting the high front end cost. Example: oversized expensive CPU's processors, process arrays in microseconds then have to sit and wait for the slow Southbridge,(hard drive to deliver the data through the LAN then to the monitor). *** Not all programs will utilize (HT) "hyper threading" to utilize multiple processors. The difference between a server database, a high end gaming program, or use of office/internet software is comparable to 100 horse power motor to a 1 horse power motor. Office software will benefit by a high speed processor (like a small fast hair dryer fan), less cores for the price. A large server hosting many clients or a multi user game will require more cores at a lower speed processor (like 4 large turbine fans). If you have money to burn, then purchase highest CPU speeds across 10+ cores at the highest
 
cache for servers (like 10 jet engines). For an office computer (internet & MS Office), 10 cores at the highest cache is a total waste of money for the speed and horsepower and will buy you nothing; a quad core is all you would need for the processing power of low end software (a single 4-core will get the work done with less than half the cost of a 12-core). Check the internet for benchmark hardware test for the software you will run to determine the CPU horsepower you will need. Programs best suited for multi core technology: Database servers, such as SQL's, can license each core (CPU) as a separate computer. Also, SQL uses a software architecture called Parallelism that divides computations between all available cores. Parallelism programs such as CAD and gaming utilizing rendering add ons and multiplayer additions, will utilize multiple CPU's.
The Xeon E5-2600 V2 or "Ivy Bridge EP"(HashwellAchitecture)
The core architecture inside the latest high-end model of the Xeon E5-2600 V2 or "Ivy Bridge EP" is, aside from the core architecture, completely different from the Ivy-bridge "i7 \-3xxx". With up to twelve cores, two integrated memory controllers, no GPU and 30MB L3 cache, it is the big brother of the recently reviewed Ivy-bridge E (Core i7-4960X). Intel has three die flavors of the Ivy-bridge EP: The first lowest core count (4/6 cores), (high frequencies) or low power SKUs; this is the core being used in the enthusiast Ivy Bridge-E processors. The second one is targeted at the typical server environment with higher core counts (6 to 10 cores) and a larger L3 cache (25MB). The third and last one is the high performance HPC and server die, with 12 cores, two memory controllers for lower memory latency, and 30MB of L3 cache. The EP uses DDR3 in all of its forms (vanilla, ECC, buffered ECC, LRECC) where as the EX version is going to use a serial interface similar in concept to FB-DIMMs. There will be two types of memory buffers for the EX line, one for DDR3 and later another that will use DDR4 memory. No changes need to be made to the new EX socket to support both types of memory.

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