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VLSI Project Titles, 2009 - 2010 NCCT Final Year Projects

VLSI Project Titles, 2009 - 2010 NCCT Final Year Projects

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Published by: ncctrtp on Sep 23, 2009
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ncctchennai@gmail.com, www.ncct.in,www.ieee2009.com
044-28235816, 9841193224,9380102891
NCCT, 109. 2
nd
Floor, Bombay Flats,Nungambakkam High Road,Nungambakkam, Chennai – 600034. Nextto ICICI, Above IOB
NCCT
 
PROMISE FOR THE BEST PROJECTS
 VLSI PROJECTS
IEEE PROJECTS in various Domains
Latest Projects, 2009 - 2010
#109, 2
nd
Floor, Bombay Flats, Nungambakkam High RoadNungambakkam High Road, Chennai – 600034 Above IOB, Next to ICICI
044-28235816, 9841193224ncctchennai@gmail.com www.ncct.inEMBEDDED SYSTEM PROJECTS
Microcontrollers | VLSI | DSP | Matlab | Robotics
 
 VLSI PROJECTS
An Area-Efficient Universal Cryptography Processor for SmartCards – 2009
The CSI Multimedia Architecture – 2009
FPGA Based Power Efficient Channelizer for Software DefinedRadio – 2009
Improvement of the Orthogonal Code Convolution Capabilitiesusing FPGA Implementation 2009
A VHDL Model of a IEEE1451.2 Smart Sensor: Characterizationand Applications – 2008
Fuzzy based PID Controller using VHDL/VERILOG foTransportation Application – 2008
Implementation of IEEE 802.11 a WLAN baseband Processor – 2008
A Lossless Data Compression and Decompression Algorithmand its Hardware Architecture – 2008
A Verilog Implementation of UART Design with Bist Capability –2008
ncctchennai@gmail.com, www.ncct.in,www.ieee2009.com
044-28235816, 9841193224,9380102891
NCCT, 109. 2
nd
Floor, Bombay Flats,Nungambakkam High Road,Nungambakkam, Chennai – 600034. Nextto ICICI, Above IOB
 
A Robust Uart Architecture based on Recursive Running SumFilter for Better Noise Performance – 2008
FPGA Implementation of USB Transceiver Macrocell Interfacewith Usb2.0 Specifications
A VLSI Architecture for Visible Watermarking In A Secure StillDigital Camera (S2dc) Design (Corrected)
A Low-Power Multiplier with the Spurious Power SuppressionTechnique
Design of Reconfigurable Coprocessor for CommunicationSystems
Block-Based Multiperiod Dynamic Memory Design for Low Data-Retention Power 
A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
On the Design of a Multi-Mode Receive Digital-Front-End for Cellular Terminal RFICS
Design Exploration of a Spurious Power Suppression Technique(SPST) and its Applications
Implementation of a Multi-Channel UART Controller based onFIFO Technique and FPGA
ncctchennai@gmail.com, www.ncct.in,www.ieee2009.com
044-28235816, 9841193224,9380102891
NCCT, 109. 2
nd
Floor, Bombay Flats,Nungambakkam High Road,Nungambakkam, Chennai – 600034. Nextto ICICI, Above IOB

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