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Vlsi Notes

Vlsi Notes

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Published by: arvindron on Sep 25, 2009
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07/31/2013

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Design of High Speed CMOS Logic Networks
(Chapter 8 of John.P.Uyemura and Chapter5 of EC74)In VLSI technology, switching speed of logic circuits is an important parameterand is closely related to the timing specifications. Modern CMOS technology is capableof fabricating MOSFETS with channel lengths smaller than 65 nm. Here, the aspect ratio(W/L) is the important critical parameter in high speed CMOS logic networks.
Gate delays:
Gate delay is defined as the time taken by the Logic gate to respond to thesignal given at its input. As shown in fig.1, the NAND gate takes a fixed duration to givethe output after the input is given. This time is the gate delay. The parameters associatedwith the gate delay are transistor resistance, Capacitance and the load capacitance, CL.
 
Fig.2 illustrates the variation of the gate delay for different values of CL.
0
U1A7400123
 
Fig.1 Circuit to illustrate the definition of Fig.2 Graph of delay time v/s loadof gate delay
 
capacitanceFET unit Resistance
is given by
 
( )
 DDu
 L R
 ⎠ ⎞⎝ ⎛ =
'1 Where is unit transistor Resistance, W and L are the width and Length of thetransistor, K’ is
 Ru
oxn
μ 
 
uSSmu D DmGuGm um
mC mC mC  m R R
====
,,, 
VLSI circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore
BVout
00
ACL
1n
Vdd
 
3.3Vdc
 
- 2 -
u
=
min
 
Fig.3 Minimum-Size FET Fig.4 3X Scaled- FET
 Fig.3 shows the layout of FET and Fig.4 shows the scaled FET, 3 times theoriginal size. The parasitic capacitances for unit size FET are given by
uSBGSSu u DBGD Du uOX Gu
WL
)()()(
+=+==
 where CGu, CDuand Csuare the Gate, Drain and Source Capacitances. The width of unit size FET is the minimum size given by Wmin= Wu.Fig.4 shows the scaled FETwith m = 3. The aspect ratio becomes 3 times the unit FET and the aspect ratio alsobecome e times unit FET. In general, the size of scaled FETs are integer multiples of theminimum
u
 L L
 ⎠ ⎞⎝ ⎛ = ⎠ ⎞⎝ ⎛ 
3
3
( )
u
3
3
=
The FET parasitic resistance and capacitance becomes
uSSuu D DuGuGuuu
mC mC mC mR R
====
,,,
VLSI circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore
2
 
- 3 -It can be seen from the above expressions that, the capacitances are increased 3times and the resistance is decreased by 3 times. But, an important observation is that, theRC product remains same RmCm=RuCu.The Resistance and capacitance of 3X FET of fig.4 is given by
uSSxu D DxGuGxu
 R Rx
3,3,3,3
====
 
 HL f  LH 
==
 
uSSu D DGuGu
 R R
3333
3333
====
 The rise time and fall time of 3X FET are given by 33
33
 Lun fo f  L puro
α α 
+=+=
 If we connect the minimum size FET for both PMOS and NMOS as shown inFig.5, results in an inverter. The layout of the inverter is shown in Fig.6.
M2V13.3Vdc
0
M1
0
 
inout
 
Fig.5 Schematic diagram of Inverter Fig.6 Layout of InverterVLSI circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore
3

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