Design of High Speed CMOS Logic Networks
(Chapter 8 of John.P.Uyemura and Chapter5 of EC74)In VLSI technology, switching speed of logic circuits is an important parameterand is closely related to the timing specifications. Modern CMOS technology is capableof fabricating MOSFETS with channel lengths smaller than 65 nm. Here, the aspect ratio(W/L) is the important critical parameter in high speed CMOS logic networks.
Gate delay is defined as the time taken by the Logic gate to respond to thesignal given at its input. As shown in fig.1, the NAND gate takes a fixed duration to givethe output after the input is given. This time is the gate delay. The parameters associatedwith the gate delay are transistor resistance, Capacitance and the load capacitance, CL.
Fig.2 illustrates the variation of the gate delay for different values of CL.
Fig.1 Circuit to illustrate the definition of Fig.2 Graph of delay time v/s loadof gate delay
capacitanceFET unit Resistance
is given by
V V LW k R
−⎟ ⎠ ⎞⎜⎝ ⎛ =
'1 Where is unit transistor Resistance, W and L are the width and Length of thetransistor, K’ is
uSSmu D DmGuGm
mC C mC C mC C
m R R
VLSI circuits - Prof.M.J.Shanthi Prasad, HOD of E & C, BIT, Bangalore