NTDCTV05

TECHNICAL TRAINING MANUAL

N5SS (TG-1, C) CHASSIS

COLOR TELEVISION
CN27E90, CX32E70
CN32E90, CN35E15
CF35E50, CX35E60
CX35E70, CX35E81
CN35E90, CN35E95

PRINTED IN JAPAN Aug. 1995 So

 Contents
SECTION I
OUTLINE ...................................................................... 6
1. OUTLINE OF N5SS CHASSIS (CN32E90, CN35E90) .................................................................... 7
2. PC BOARD CONFIGURATION ........................................................................................................ 7
3. MAJOR SPECIFICATIONS (NEW FUNCTIONS IN ADDITION TO THOSE OF N5SS) ........ 7
4. MODIFICATIONS ON CHASSIS ..................................................................................................... 7
5. CONSTRUCTION OF CHASSIS ...................................................................................................... 8
6. LOCATION OF CONTROLS ............................................................................................................ 9
7. CN32D90 BLOCK DIAGRAM ......................................................................................................... 13
8. [US, CANADA] SPECIFICATION FOR MODEL's 1995 ............................................................ 14

SECTION II
TUNER, IF/MTS/S.PRO MODULE ......................... 16
1. CIRCUIT BLOCK ............................................................................................................................. 17
2. TUNER ................................................................................................................................................ 18
3. IF/MTS/S.PRO MODULE ................................................................................................................. 19
4. PIP TUNER ......................................................................................................................................... 23

SECTION III
CHANNEL SELECTION CIRCUIT ........................ 24
1. OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM .................................................... 25
2. OPERATION OF CHANNEL SELECTION CIRCUIT ................................................................ 25
3. MICROCOMPUTER ......................................................................................................................... 26
4. MICROCOMPUTER TERMINAL FUNCTION ........................................................................... 27
5. EEPROM (QA02) ............................................................................................................................... 29
6. ON SCREEN FUNCTION ................................................................................................................. 29
7. SYSTEM BLOCK DIAGRAM ......................................................................................................... 30
8. LOCAL KEY DETECTION METHOD .......................................................................................... 31
9. REMOTE CONTROL CODE ASSIGNMENT ............................................................................... 32
10. ENTERING TO SERVICE MODE ................................................................................................ 35
11. TEST SIGNAL SELECTION ......................................................................................................... 35
12. SERVICE ADJUSTMENT .............................................................................................................. 35
13. FAILURE DIAGNOSIS PROCEDURE ......................................................................................... 36
14. TROUBLE SHOOTING CHART .................................................................................................. 38

SECTION IV
AUDIO OUTPUT CIRCUIT ..................................... 41
1. OUTLINE ............................................................................................................................................ 42
2. AUDIO OUT IC .................................................................................................................................. 43

2
SECTION V
A/V SWITCHING CIRCUIT .................................... 44
1. OUTLINE ............................................................................................................................................ 45
2. IN / OUT TERMINALS ..................................................................................................................... 45
3. CIRCUIT OPERATION .................................................................................................................... 45

SECTION VI
VIDEO PROCESSING CIRCUIT ............................ 47
1. OUTLINE ............................................................................................................................................ 48
2. SIGNAL FLOW .................................................................................................................................. 48
3. CIRCUIT OPERATION .................................................................................................................... 48

SECTION VII
V/C/D/IC ...................................................................... 52
1. OUTLINE ............................................................................................................................................ 53
2. LARGE SCALE EMPLOYMENT OF BUS CONTROL OF PARAMETER FOR PICTURE
CONTROLS ...................................................................................................................................... 53
3. EMPLOYMENT OF CONTAINING EACH VIDEO BAND FILTER INSIDE.......................... 53
4. EMPLOYMENT OF CONTAINING EACH FILTER (FOR S/H) INSIDE................................. 53
5. LOW COST OF IC ............................................................................................................................ 53

SECTION VIII
PIP MODULE ............................................................. 55

SECTION IX
SYNC SEPARATION, H-AFC,
H-OSCILLATOR CIRCUITS .............................. 58
1. SYNC SEPARATION CIRCUIT ...................................................................................................... 59
2. H AFC (Automatic Frequency Control) CIRCUIT ......................................................................... 60
3. H OSCILLATOR CIRCUIT ............................................................................................................. 61

SECTION X
VERTICAL OUTPUT CIRCUIT ............................. 63
1. OUTLINE ............................................................................................................................................ 64
2. V OUTPUT CIRCUIT ....................................................................................................................... 65

3
SECTION XI
HORIZONTAL DEFLECTION CIRCUIT.............. 69
1. OUTLINE ............................................................................................................................................ 70
2. HORIZONTAL DRIVE CIRCUIT ................................................................................................... 70
3. BASIC OPERATION OF HORIZONTAL DRIVE ........................................................................ 71
4. HORIZONTAL OUTPUT CIRCUIT ............................................................................................... 74
5. HIGH VOLTAGE GENERATION CIRCUIT ................................................................................. 79
6. X-RAY PROTECTION CIRCUIT ................................................................................................... 82
7. OVER CURRENT PROTECTION CIRCUIT................................................................................ 83
8. KINK CORRECTION CIRCUIT ..................................................................................................... 84

SECTION XII
DEFLECTION DISTORTION CORRECTION
CIRCUIT (Side DPC Circuit) .............................. 85
1. DEFLECTION DISTORTION CORRECTION IC (TA8859P) .................................................... 86
2. SIDE DPC ............................................................................................................................................ 87
3. DIODE MODULATOR CIRCUIT ................................................................................................... 88
4. ACTUAL CIRCUIT ........................................................................................................................... 89

SECTION XIII
CLOSED CAPTION/EDS CIRCUIT ....................... 92
1. OUTLINE ............................................................................................................................................ 93
2. DATA TRANSMISSION FORMAT ................................................................................................ 93
3. DISPLAY FORMAT ........................................................................................................................... 94
4. CIRCUIT OPERATION .................................................................................................................... 95

SECTION XIV
POWER CIRCUIT ..................................................... 98
1. OUTLINE ............................................................................................................................................ 99
2. RECTIFYING CIRCUIT AND STANDBY POWER SUPPLY ................................................... 100
3. MAIN SUPPLY CIRCUIT............................................................................................................... 100
4. OUTLINE OF CURRENT RESONANT TYPE SUPPLY ........................................................... 101
5. FUNDAMENTAL THEORY ........................................................................................................... 101
6. ACTUAL CIRCUIT ......................................................................................................................... 102
7. OTHER POWER CIRCUIT ........................................................................................................... 105
8. PROTECTOR MODULE (Z801) .................................................................................................... 106

4
SECTION XV
DSP CIRCUIT .......................................................... 109
1. ORIGINS OF DOLBY SURROUND ............................................................................................. 110
2. THE DOLBY MP MATRIX ............................................................................................................ 110
3. THE DOLBY SURROUND DECODER ......................................................................................... 111
4. DSP CIRCUIT ................................................................................................................................... 111
5. DSP (Digital Surround Processor) IC ............................................................................................. 114
6. SURROUND CIRCUIT ................................................................................................................... 116
7. INPUT BALANCE CIRCUIT ......................................................................................................... 116
8. MATRIX CIRCUIT ......................................................................................................................... 117
9. FILTER CIRCUIT (ANTI-ALIAS FILTER)................................................................................. 117
10. DSP CIRCUIT (DELAY) ............................................................................................................... 118
11. 7 kHz LOW PASS FILTER ........................................................................................................... 119
12. DOLBY NR CIRCUIT ................................................................................................................... 120
13. DSP FRONT ADDITION CIRCUIT ............................................................................................ 121
14. BUS CONVERTER ........................................................................................................................ 122
15. NEUTRAL BIAS ............................................................................................................................ 122
16. AUDIO OUTPUT AMPLIFIER (For Rear SP) .......................................................................... 123
17. TROUBLESHOOTING CHART ................................................................................................. 124

SECTION XVI
FAILURE DIAGNOSIS PROCEDURES ............... 125
1. H STARTING CIRCUIT FAILURE DIAGNOSIS PROCEDURES........................................... 126
2. DEFLECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES ......................................... 127
3. LEFT-RIGHT PIN-CUSHION DISTORTION CORRECTION CIRCUIT .............................. 128
4. X-RAY PROTECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES ........................... 129
5. PROTECTION CIRCUIT DIAGNOSIS PROCEDURE ............................................................. 130
6. VIDEO CIRCUIT DIAGNOSIS PROCEDURES ......................................................................... 131

5
SECTION I
OUTLINE

6
1. OUTLINE OF N5SS CHASSIS 3. MAJOR SPECIFICATIONS (NEW
(CN32E90, CN35E90) FUNCTIONS IN ADDITION TO THOSE
OF N5SS)
The N5SS chassis is a complete bus control type
chassis where the deflection circuit is controlled by a newly (1) EOS (Extended-Data-Service)
developed I2C-bus line control system. (2) Center-Ch-Audio-Input provided

2. PC BOARD CONFIGURATION 4. MODIFICATIONS ON CHASSIS

(1) Serviceability improved with direct, front access system
(1) Signal unit employed.
(2) Power/def unit (2) One touch cabinet securing (CN32E90) to the chassis.
(3) A/V, CRT-D, SP-TERM (3) Improved serviceability with the bus control system
(4) CCD, comb (CN32E90) employed for the defection circuits.
Digital comb (CN35E90) (4) Improved serviceability with the white balance bus
(5) D.S.P unit control system employed.
(6) C.C, EDS/R.G.B SW (5) Digital comb/CCD miniaturized into a socketable size.

7
 5. CONSTRUCTION OF CHASSIS

DPC circuit

CCD circuit
PIP circuit
SIGNAL circuit
EDS, RGB SW
circuit
IF/MTS/A-PRO
module
AUDIO OUT

CRT circuit

REAR AMP circuit

CONVERTER trans
A/V circuit
8
Fig. 1-1

RF SW

POWER/DEF circuit

V. OUT

DPC circuit
H.OUT

H.OUT trans
6. LOCATION OF CONTROLS
6-1. TV Set

For specific use of each control, consult the corresponding page numbers in brackets.

Front View

POWER indicator
POWER

POWER button
Remote sensor

Press to open
the door

Behind the door

VIDEO/AUDIO IN
jacks <VIDEO 3> CHANNEL buttons

DEMO button VOLUME buttons

-/+buttons

MENU button ANT/VIDEO button

ADV button

Fig. 1-2

9
 Rear view

S-VIDEO IN jack <VIDEO 1>

VARiable AUDIO OUT

ANTenna terminals jacks

EXTernal SPEAKER
terminals

VIDEO AUDIO OUT

MAIN SPEAKER jacks
switch
PIP AUDIO OUT
jacks
REAR SPEAKER
terminals
VIDEO/AUDIO IN jacks
<VIDEO 2>

VIDEO/AUDIO IN jacks
<VIDEO 1>

Fig. 1-3

10
6-2 Location of Controls (Remote Control)

Only the buttons that are used to operate the TV set are described here.
For details on the use of each control, refer to pages in brackets.

Aim at the remote sensor on the TV

Learn/Transmit indicator TIMER button

EDS button RECALL button

POWER button
TV/CABLE/VCR/AUX switch
Set to "TV" to control the TV.
MUTE button

TV/VIDEO

Channel Number buttons CHANNEL buttons

VOLUME buttons

RTN buttons
PIP function buttons

AUDio button
SET UP button
PICture button
OPTION button
RESET button EXIT button
ANT 1/2 button -\+ buttons
C.CAPT button FAV -/+ buttons

CYS/SBS button DSP/SUR button

Learning buttons DSP F/R button
You can use these eight
buttons only as Learning
function buttons. LEAR/USE switch
They are not affected by
Mode selection (TV/CABLE/
VCR/AUX).
To operate buttons inside the cover,
slide the cover down and toward you.

Fig. 1-4

11
6-3 Monitor Panel

This TV set is equipped with S-VIDEO INPUT jacks,

VIDEO/AUDIO INPUT jacks, VIDEO/AUDIO OUTPUT
jacks, VARIABLE AUDIO OUTPUT jacks, PIP AUDIO
OUTPUT jacks and EXTERNAL SPEAKER terminals for
connecting your desired video/audio equipment.

5 3 9 4 7
TV Rear

TV Front

10 11 1 2 8 6

Fig. 1-5

, , VIDEO 1/VIDEO 2/VIDEO 3 IN Jacks —
provide for direct connection of video devices
(VCR, video disc player, camcorder, etc.) with
video/audio outputs.
, S-VIDEO IN Jacks —provide for direct S-video
connection from an VCR or a video disc
player. The TV's VIDEO 1/3 audio jacks can
also be used to connect the VCR's audio cables.
VIDEO/AUDIO OUT Jacks --- provide fixed-
level audio and video outputs from whatever is
displayed on the screen.
VARIABLE AUDIO OUT Jacks --- feed
volume-controlled stereo audio out from
whatever is displayed on the screen, allows
connection of audio amplifier and lets you adjust
sound level with TV's remote.
PIP AUDIO OUT Jacks — provide fixed-level
audio outputs from whatever is displayed on the
PIP window screen.
EXTERNAL SPEAKER Terminals — provide
for direct connection of external speakers.
MAIN SPEAKER Switch — lets you turn off
TV's built-in speakers so that sound will instead
come through speakers connected to
EXTERNAL SPEAKER terminals.
REAR SPEAKER Terminals — provide for
direct connection of the supplied Surround
Speakers.

12
 CRT DRIVE PCB

U/V SIGNAL UNIT

HY01(CHILD) SPEED MOD
SYNC SIGNAL DET.
TUNER IF
RED OUTPUT
EL922L 12
SDA SCL 58 Y SYNC R 43 143 143
4 3 GREEN OUTPUT CRT
38 I G 42 144 144
37 O B 41 145 145 BLUE OUTPUT
35 Q501 +200V V H
H001(MOTHER) H002 34 TA1222N
S(L)
TUNER 9 2 V/SIF/MTS 18
IF Ys 1 32 Ys 301
EL466L MVUS34S 16 V 31 35 83
8 PIP R 4 35 R V OUTPUT 2
11 12 6 22 S(R) R370
34 G H 23 83 84 TA8427K
FOCUS

SDA SCL V V MODULE G 5

SCREEN

+27V
B 6 33 B SDA SCL Q302
HIGH VOLTAGE

27 28 13 Q370
7. CN32D90 BLOCK DIAGRAM

E/W CORRECTION
C 2SA933SQ
TA8859AP Q462 DPC
32 31 30 29 I2C-BUS LINE Q402 Q404 T461
2SC1740S-Q
KEY SDA SCL STOP SYNC H DRIVE H OTUTPUT
CONTROL QA01 MICROCOMPUTER 2SC1569FA-5 2SD2253(FA)
TMP87CS38N-3152 I 2C Bus line
-27V FBT
EDS/C.C
TB40 D840
5 6 D371

13
VIDEO SDA SCL KEY TFB
INPUT 3 ICA02 CONTROL CCD UNIT HEATER
MEMORY
4132AD
PB5419 4132BD
24LCO4BI/P V Y C F801 TB01
ST24C04CB6
DG DC DD T862
5A SR801 D801

Fig. 1-6
D883 F470 2A +125V

Q801 33V
V-AV D471
Z801
EA
L78MR05 D847 D885 F883 5A PROTECTOR
TRANS

EH +24.5V
Q840
CONVERTER

36 38
V L R Y R V 43 AB +12V
} PROTECTOR

RESET Q420 9V-1

VIDEO QV01 SIGNAL SW L 45 AA
INPUT 2 EJ STBY 5V
TA1218N Y 30 Y-COMB
VOLTAGE REG.

POWER/DEF UNIT
STR-

2SC1B15Y
V SDA SCL C C 32 EI C-COMB
VIDEO 42 25 24 1 2 34 AJ QE06
INPUT 1 Q670 SW
OVER VOLTAGE
OVER HEAT

AUDIO OUT
VIDEO VAR-L
L 4 11
AI R883
OUTPUT Q862
R 2
AT VAR-R PHOTO-COUPLER
W 1 8 TLP621GR-L
TA8256H

12
9V-2 Q832
L R L R R L W
A/V PCB
40
PIP VAR 5V-3 Q831
AUDIO AUDIO
R L WOOFER
5V-2 Q830
8. [US, CANADA] SPECIFICATION FOR MODEL's 1995

CHASSIS C C C C C
MODEL Nbr CN27E90 CX32E70 CN32E90 CE35E15 CF35E50
DERIV
CRT
SPECIFICATION HITACHI TDD TDD *TDD *TDD
1 Picture Tube *FST-D/T NF-D/T NF-D/T *FST-D/T FST-D/T
* 2 Channel Capacity 181ch 181ch 181ch 181ch 181ch
G 3 C. Caption ● ● ● ● ●
E 4 MTS with dbx ● ● ● ● ●
N 5 Bass, Tre, Balance ● ● ● ● ●
E 6 Sub-Audio-Program ● ● ● ● ●
R
7 Remote band unit *A-Univ (42k) *A-Univ (42k) *Intelig+EZ *Unive (36k) *Unive (36k)
A
L 8 Picture-in-Picture ● (2TN) ● (2TN) ● (2TN) *● (1TN) ● (1TN)
9 LED Indicators (RED) ● (Power) ● (Power) ● (Power) *● (Power) ● (Power)
10 Local Keys 8key 8key 8key 8key 8key
11 Dolby Surround — — ● — —
12 Dig-Sound Processor — — ● (DSP4ch) — —
* 13 Front Surround ● ● — ● ●
S 14 Cyclone ABX ● — ● — —
O
15 Sub-Bass-System — ● — — —
U
N 16 Audio Output *10Wx2 & 13W 10Wx2 10Wx2 & 10Wx2 10Wx2
D 13W & 5Wx2
17 Speaker Size & Nbr *80x120x2 70x130x2 80x120x2 70x130x2 70x30x2
& 100R (Hon) 100R & REAR
18 Comb Filter *● (GLS) ● (CCD) ● (CCD) ● (CCD) ● (GLS)
* 19 Dy-Quadruple Focus — — — — —
P 20 Scan Velocity Modu ● ● ● ● ●
I
C 21 Vert Contour Corre ● ● ● ● ●
T 22 Black Level Expand ● ● ● ● ●
U 23 Flesh Tone Correct *● ● ● ● ●
R 24 Dynamic Noise Reduc *● ● ● ● ●
E 25 Picture Preference ● ● ● ● ●
26 Horiz Resolution 650 700 700 800 800
27 Parental-Ch Lock ● ● ● ● ●
* 28 Channel Label (32ch) ● ● ● ● ●
O
29 3-Language Display ● ● ● ● ●
T
H 30 Clock/Off-Timer *●/● ●/● ●/● ●/● ●/●
E 31 Favorite Channel *● *● *● *● *●
R 32 Extended-Data-Servi *● *● *● *● *●
33 Star-Sight-decoder — — — — —
34 S-Video In-Term ● (1+1) ● (1+1) ● (1+1) ● (1) ● (1)
* 35 Audio, Video-In/Out 1+2/— 1+2/1 1+2/1 *3/1 3/1
T 36 Front AV Jack *● ● ● — —
E 37 Variable Audio Out ● ● ● ● ●
R 38 2-RF Input ● ● ● — —
M
39 Ext Speaker Term ● ● ● ● ●
S
40 PIP Audio Out Jack — *— *● — —
41 Center-Ch-Aud-Input — *● *— — —
* 42 Speaker-Box -- — ● SS-SR94 — —
AC 43 Others — — — — —
*Cabinet NEW CX32D70 CN32D90 *CE35D10 CF35D50
PARTS SUPPLY (ISO) — — — — —
14
 CHASSIS C C C C C
MODEL Nbr CX35E60 CX35E70 CX35E81 CN35E90 CN35E95
CONSOLE CINEMA
CRT
SPECIFICATION TDD TDD TDD TDD TDD
1 Picture Tube FST-D/T NF-D/T NF-D/T NF-D/T NF-D/T
* 2 Channel Capacity 181ch 181ch 181ch 181ch 181ch
G 3 C. Caption ● ● ● ● ●
E 4 MTS with dbx ● ● ● ● ●
N 5 Bass, Tre, Balance ● ● ● ● ●
E 6 Sub-Audio-Program ● ● ● ● *●
R
7 Remote band unit *A-Univ (42k) *A-Univ (42k) *A-Univ (42k) *Intelig+EZ *Intelig+EZ
A
L 8 Picture-in-Picture ● (2TN) ● (2TN) ● (2TN) ● (2TN) ● (2TN)
9 LED Indicators (RED) ● (Power) ● (Power) ● (Power) ● (Power) ● (Power)
10 Local Keys 8key 8key 8key *8key *8key
11 Dolby Surround — — — ● ●
12 Dig-Sound Processor — — — ● (DSP4ch) ● (DSP4ch)
* 13 Front Surround ● ● ● — —
S 14 Cyclone ABX — — — ● ●
O
15 Sub-Bass-System ● ● ● — —
U
N 16 Audio Output 10Wx2 10Wx2 10Wx2 10Wx2 10Wx2
D & 13W, 5Wx2 & 13W, 5Wx2
17 Speaker Size & Nbr 70x130x2 70x130x2 70x130x2 80x120x2 & 80x120x2 &
*100R, REAR *120R, REAR
18 Comb Filter ● (DIG) ● (DIG) ● (DIG) ● (DIG) ● (DIG)
* 19 Dy-Quadruple Focus ● ● ● ● ●
P 20 Scan Velocity Modu ● ● ● ● ●
I
C 21 Vert Contour Corre ● ● ● ● ●
T 22 Black Level Expand ● ● ● ● ●
U 23 Flesh Tone Correct ● ● ● ● ●
R 24 Dynamic Noise Reduc ● ● ● ● ●
E 25 Picture Preference ● ● ● ● ●
26 Horiz Resolution 800 800 800 800 800
27 Parental-Ch Lock ● ● ● ● ●
* 28 Channel Label (32ch) ● ● ● ● ●
O
29 3-Language Display ● ● ● ● ●
T
H 30 Clock/Off-Timer ●/● ●/● ●/● ●/● ●/●
E 31 Favorite Channel *● *● *● *● *●
R 32 Extended-Data-Servi *● *● *● *● *●
33 Star-Sight-decoder — — — — —
34 S-Video In-Term ● (1+1) ● (1+1) ● (1+1) ● (1+1) ● (1+1)
* 35 Audio, Video-In/Out 1+2/1 1+2/1 1+2/1 1+2/1 1+2/1
T 36 Front AV Jack ● ● ● ● ●
E 37 Variable Audio Out ● ● ● ● ●
R 38 2-RF Input ● ● ● ● ●
M
39 Ext Speaker Term ● ● ● ● ●
S
40 PIP Audio Out Jack — *— *— *● *●
41 Center-Ch-Aud-Input — *● *● *— *—
* 42 Speaker-Box — — — ● SS-SR94 ● SS-SR94
AC 43 Others — *VCR-Storate — *VCR-Stora
*Cabinet C35D60 CX35D70 NEW (DAX) CN35D90 NEW (BLK)
PARTS SUPPLY (ISO) — — — — —
15
 SECTION II
TUNER, IF/MTS/S.PRO MODULE

16
1. CIRCUIT BLOCK

IF/MTS/S.PRO Module MVUS34S

EL466L SIF
VIF/SIF output Sound
SAW
Tuner Multiplex S.PRO Circuit
Filter Circuit
Circuit

RF AGC

C-IN
R-IN L-IN
TP12 TV TV
Video output R-OUT L-OUT
C-OUT
R-OUT
To A/V switch circuit L-OUT
AFT output
(L+R)
-OUT

Fig. 2-1 Block diagram

1-1. Outline

(1) RF signals sent from an antenna are converted into
intermediate frequency band signals (video: 45.75 MHz,
audio: 41.25 MHz) in the tuner. (Hereafter, these signals
are called IF signals.)
(2) The IF signals are band-limited in passing through a
SAW filter.
(3) The IF signals band-limited are detected in the VIF
circuit to develop video and AFT signals.
(4) The band-limited IF signals are detected in the SIF
circuit and the detected output is demodulated by the
audio multiplexer, developing R and L channel outputs.
These outputs are fed to the A/V switch circuit.
(5) A sound processor (S.PRO.) is provided.
(5) VIF/SIF circuit uses PLL sync detection system to
improve performances shown below:
• Telop buzz in video over modulation
• DP, DG characteristics (video high-fidelity
reproduction)
• Cross color characteristic (coloring phenomenon at
color less high frequency signal objects)
(6) HIC SBX1637A-22 is used in the audio multiplexer
circuit to minimize the size with increased performance.
(7) As a sound control processor, TA1217N is used. I2C-
bus data control the DAC inside the IC to perform
switching of the audio multiplexer modes.

1-2. Major Features

(1) The VIF/SIF circuit is fabricated into a small module by

using chip parts considerably.
(2) As the tuner, EL466L that which contains an integrated
PLL circuit is employed.
(3) Wide band double SAW filter F1802R used.
(4) FS (frequency synthesizer) type channel selection system
employed.

17
 2-2-2. Terminals (Tuner section)
2. TUNER
Name Function
2-1. Outline IF OUT IF outputs (P=45.75 MHz, C=42.17 MHz,
(1) Type name: EL466L S=41.25 MHz)
(2) Applicable 181CH
BM Tuner power supply (9V)
(3) I2C-bus version
(4) PLL-integrated RF AGC Gain control terminal to obtain constant
IF output
VT Control voltage to select channels
EL466L
PLL Selection
Tuner Section

2-2-3. Tuner VT Voltage (unit: V)

(1) VHF (2) UHF

1 2 3 4 5 6 7 8 9 CH VT voltage (TYP) CH VT voltage (TYP)
2 1.4 MM 1.1
6 6.4 QQ 2.2

Terminal No. Name A-2 12.8 WW 4.0

1 32V B 20.0 14 5.8

2 5V C 1.4 20 7.8

3 S-CLOCK I 3.5 26 9.2

4 S-DATA 10 5.6 32 10.8

5 ADDRESS J 7.6 38 12.5

6 IF OUT N 9.7 44 13.9

7 BM (9V) R 11.8 50 15.0

8 RF AGC W 14.2 56 17.2

9 VT FF 17.9 62 19.4
LL 24.2 69 23.6
Fig. 2-2 Tuner terminal layout
* VT voltage not indicated for a channel falls between
those values for channels just upper and lower the channel.

2-2. Operation of the Tuner

2-2-1. Receiver Channels

VHF 2~13CH
UHF 14~69CH 181CH in total
CATV A-6~, J~W, AA~BBB, 65~92, 100~127CH

18
3. IF/MTS/S.PRO MODULE
The IF/MTS/S.PRO module (MVUS34S) limits bandwidth
of IF signals and detects video and audio signals. The module
consists of IF amplifiers, SAW (surface acoustic wave)
filter, and PIF IC. The SAW filter has a wideband response
to improve picture quality and audio buzz characteristic and,
develops separate outputs of video and audio signals. The
PIF IC employs a PLL complete sync detection + audio split
carrier system.
3-1-2 Video PIF Circuit
A PIF detector switching carrier is oscillating at a frequency
adjusted to 45.75 MHz with L051 (VCO CW coil) under no
RF signal input. When an RF signal enters, an IF video
carrier is fed to APC section from IF AMP inside the IC, and
the detector switching carrier is adjusted by the APC, VCO,
etc. in the PLL circuit so that its frequency and phase are
matched to those of the IF video carrier to perform precise
sync detection. Thus processed video output is developed at
pin 21.

3-1. IF/MTS/S.PRO Module (MVUS34S) PLL lock speed is automatically controlled by adding the
3-1-1. Module Terminal Layout video signal at pin 21 to pin 1. That is, since the video signal
is not output at operations of power on, CH switching, etc.,
the APC filter between pin 16 and GND consists of C022 and
C053, and R018, and the filter effect decreases, thus increasing
PLL lock speed.
Next, when a video out exists, the internal resistance is short-
circuited and the APC filter consists of C022 and C053,
internal resistance, and R018. As a result, the filter effect
increases and the PLL lock speed decreases. Consequently,
under normal signal reception, phase of the detector switching
carrier is locked in a stable condition if an IF video carrier is
lost for a short time due to over modulation, etc. By combining
9 1
such a PLL complete sync detection system and a wideband
27 12
SAW filter shown in Fig. 2-4, a wideband (4.2 MHz) video
detection output with less beat interference will be obtained.

3-1-3. Audio PIF Circuit

Pin No. Name Pin No. Name
The IF signal fed through Q003 (Fig. 2-4) enters an audio
1 GND 15 DAC-OUT2 section of the SAW filter (Z001) which has an IF bandwidth
2 IF-IN 16 R-IN for dedicated audio signals, and only the audio signal of
3 NC 17 C-IN 41.25 MHz is fed to pin 7. The signal is sync-detected with
4 +9V 18 L-IN the detection carrier completely synchronized with the IF
video carrier and pin 14 develops a 4.5 MHz SIF signal. By
5 RF AGC 19 GND
using the PLL split carrier system just stated, audio signals
6 AFC 20 SCL with less buzz by the video signal will be reproduced. The 4.5
7 VIDEO OUT 21 SDA MHz SIF enters pin 15 through a 4.5 MHz filter, Z003 and
8 ADR SW 22 W-OUT pin 9 develops a FM-detected audio signal.
9 MPX OUT 23 C-OUT
10 --- 24 L-OUT
11 --- 25 GND
12 TV R-OUT 26 R-OUT
13 DAC-OUT1 27 +9V
14 TV L-OUT

Fig. 2-3 IF/MTS/S.PRO module terminal layout

19
 4.5MHz SIF SIGNAL
Z003
FM DET. COIL
L053
SIF BANDWIDTH
15 11 12

SIF LIMIT FM DET. 9

TO SOUND
14. R151
17. MPX IC
APC L051
S
Q002 SIF DET VCD VCO C106
18
CW COIL

23
Q003 L502
Z001 7
AFT COIL
SAW
IF AMP
FILTER 5 IF VIDEO
GAIN – 14dB 21
AMP DET.
F1802R 4 TP12
R021
22
LOCK
Z002
-6dB 1 Q004
CONTROL
AGC

2 13 16 20
-15dB
R022
R018

RF AGC C022
S C P
R051
41.25M 45.75M C053
VIDEO IF BANDWIDTH

1 2 3 4 5 6 7 8 9
GND IF-IN N.C +B(9V) RF AGC AFC VIDEO OUT ADR SW M

Fig. 2-4 IF/MTS/S. PRO circuit diagram

20
3-1-4. Audio Multiplex Demodulation Circuit
The sound multiplex composite signal FM-detected in the
PIF circuit enters pin 12 of HIC (hybrid IC) in passing
through the separation adjustment VR RV2 and amplified.
After the amplification, the signal is split into two: one enters
a de-emphasis circuit, and only the main signal with the L-
R signal and a SAP signal removed enters the matrix circuit.
At the same time, the other passes through various filters and
trap circuits, and the L-R signal is AM-demodulated, and the
SAP is FM-demodulated.
Then, both are fed to the matrix circuit. At the same time,
each of the stereo pilot signal fH and the SAP pilot signal 5fH
is also demodulated to obtain an identification voltage. With
the identification voltage thus obtained and the user control
voltage are used to control the matrix.
The audio signals obtained by demodulating the sound
multiplex signal develop at pin 10 and 11 of HIC and develop
the terminals of 12 and 14 of the module.

MVUS32S

MPX TV DAC-out1 TV DAC-out2

Out R-Out (SURR OFF) L-Out (RFSW)
9 10 11 12 13 14 14

Monitor the input Stereo 0V SAP 0V OFF 0V RF1 0V

pin for multiplex
sound IC Other 0V Other 0V ON 9V RF1 9V
Not used for
CN32E90.
TV waveform detection TV waveform detection
output (R) output (L)

To AV select circuit

Fig. 2-5 Block diagram of MVUS32S

Table 2-1 Matrix for broadcasting conditions and Note:

reception mode Of the mode selection voltages, switching voltages for STE,
SAP, MONO do not output outside the module.
Output OSD display
Broad- Switching They are used inside the module to control the BUS.
12 pin 14 pin
casted mode Stereo SAP
(R) (L)
Stereo STE R L O X
SAP R L O X
MONO L+R L+R O X
Mono STE L+R L+R X X
SAP L+R L+R X X
MONO L+R L+R X X
Stereo STE R L O O
+ SAP SAP SAP O O
SAP MONO L+R L+R O O
Mono STE L+R L+R X O
+ SAP SAP SAP X O
SAP MONO L+R L+R X O

21
3-1-5. A.PRO Section (Audio Processor) All these processing are carried out according to the BUS
The S.PRO section has following functions. signals sent from a microcomputer.
(1) Woofer processing (L+R output)
(2) High band, low band, balance control Fig. 2-6 shows a block diagram of the A.PRO IC.
(3) Sound volume control, cyclone level control
(4) Cyclone ON/OFF

TA1217N

1 27 29 22 32 33 30 9 8 28

Lin 30 26 Lout
BALANCE
TONE CONTROL
Rin 34 25 Rout

2 Center
Cin LEVEL VOLUME
18 Cout

10 Wout

Win Woofer 17
3 LPF
LEVEL
16
15
I/O
14

SDA 20 13
2
I C D/A
12 SAP det.
CONV
SGL 21 11 STE det.

4 5 6 7 31 24 23 22 19

16 17 18 19 20 21 22 23 24 25 26 27

R-in C-in L-in SCL SDA W-out O-out L-out R-out

9V

From From From Q670 Q640 Q670 Q670

A/V Dolby A/V
Via QS101

Fig. 2-6 A.PRO block diagram

22
 4. PIP TUNER

Lable
Name
Lot No.
TUNER SAW VIF/SIF
SECTION FILTER CIRCUIT

RF AGC

1 15
AFT VIDEO AUDIO
OUTPUT OUTPUT OUTPUT

Fig. 2-7
Terminal No. Name
1 NC
4-1. Outline 2 32V
The PIP tuner (EL922L) consists of a tuner and an IF block 3 S-CLOCK
integrated into one unit. The tuner receives RF signals 4 S-DATA
induced on an antenna and develops an AFT output, video 5 NC
output, and audio output. 6 ADDRESS
The tuner has receive channels of 181 as in the tuner for the
7 5V
main screen and it is also controlled through the I2C-bus.
As the IC for the IF, a PLL complete sync detection plus 8 RF AGC
audio inter carrier system are employed. 9 9V
10 AUDIO
11 GND
12 AFT
13 NC
14 GND
15 VIDEO

Fig. 2-8 Tuner terminal layout

23
 SECTION III
CHANNEL SELECTION CIRCUIT

24
1. OUTLINE OF CHANNEL SELECTION
CIRCUIT SYSTEM
The channel selection circuit in the N5SS chassis employs
a bus system which performs a central control by connecting
a channel selection microcomputer to a control IC in each
circuit block through control lines called a bus. In the bus
system which controls each IC, the I2C bus system (two line
bus system) developed by Philips Co. Ltd. in the Netherlands
has been employed.
The ICs controlled by the I2C bus system are : IC for audio
signal processing (QN06), IC for V/C/D signal processing
(Q501), IC for A/V switching (QV01), IC for non volatile
memory (QA02), Main and sub U/V tuners (H001, HY01),
IC for deflection distortion correction (Q302), IC for PIP
signal processing (QY04), IC for DSP (QM01), IC for
closed caption control (Q701).
Differences from N4SS chassis are as follows;
1. On-screen function inside microcomputer is used.
Separate IC is not used for on-screen.
2. The microcomputer does not have the closed caption
function, but controls separate IC for closed caption.
3. The system uses two channels of I2C bus. One is only
for non-volatile memory.
2. OPERATION OF CHANNEL
SELECTION CIRCUIT
Toshiba made 8 bit microcomputer TLCS-870 series for TV
receiver, TMP87CS38N-3152 is employed for QA01.
With this microcomputer, each IC and circuit shown below
are controlled.
(1) CONTROL OF AUDIO SIGNAL PROCESS IC (QN06
Toshiba TA1217N)
• Adjustments for volume, treble, bass and balance
• Selection between surround mode and DSP mode,
and level adjustment
• Level adjustment of BAZOOKA system
• Audio muting during channel selection or no signal
reception.
(2) CONTROL OF VIDEO/CHROMA/DEF SIGNAL
PROCESS IC (Q501 Toshiba TA1222N)
• Adjustments for uni-color, brightness, tint, color
gain, sharpness and PIP uni-color
• Setting of adjustment memory values for sub-
brightness, sub-color and sub-tint, etc.
25
• Setting of memory values for video parameters
such as white balance (RGB cutoff, GB drive) and
gcorrection, etc.
• Setting of video parameters of video modes
(Standard, Movie, Memory)
(3) CONTROL OF A/V SWITCH IC (QV01 Toshiba
TA1219N)
• Preforms source switching for main screen and
sub screen
• Performs source switching for TV and three video
inputs
(4) CONTROL OF NON-VOLATILE MEMORY IC
(QA02 Microchip 24LC04BI/P)
• Memorizes data for video and audio signal
adjustment values, volume and woofer adjustment
values, external input status, etc.
• Memorizes adjustment data for white balance
(RGB cutoff, GB drive), sub-brightness, sub color,
sub tint, etc.
• Memorizes deflection distortion correction value
data adjusted for each unit.
(5) CONTROL OF U/V TUNER UNIT (H001 Matsushita
EL466L, HY01 Toshiba EL922L)
• A desired channel can be tuned by transferring a
channel selection frequency data (divided ratio
data) to the I2C bus type frequency synthesizer
equipped in the tuner, and by setting a band switch
data which selects the UHF or VHF band.
(6) CONTROL OF DEFLECTION DISTORTION
CORRECTION IC (Q302 Toshiba TA8859P)
• Sets adjustment memory value for vertical
amplitude, linearity, horizontal amplitude,
parabola, corner, trapezoid distortion.
(7) CONTROL OF PIP SIGNAL PROCESS IC (QY04
Toshiba TC9083F)
• Controls ON/OFF and position shift of PIP.
(8) CONTROL OF DIGITAL SOUND PROCESSOR IC
(QM04 Yamaha YSS238-D)
• Performs mode switching of DSP.
(9) CONTROL OF CLOSED CAPTION/EDS (QM01
Motorola XC144144P)
• Controls Closed Caption/EDS.
3. MICROCOMPUTER

Microcomputer TMP87CS38N-3152 has 60k byte of ROM IIC device controls through I2C bus. (Timing chart : See fig.
capacity and equipped with OSD function inside. 3-1)
The specification is as follow. • LED uses big current port for output only.
• Type name : TMP87CS38N-3152 • For clock oscillation, 8MHz ceramic oscillator is used.
• ROM : 60k byte • I2C has two channels. One is for EPROM only.
• RAM : 2k byte • Self diagnosis function which utilizes ACK function of
• Processing speed : 0.5m s (at 8MHz with Shortest I2C is equipped
command) • Function indication is added to service mode.
• Package : 42 pin shrink DIP • Remote control operation is equipped, and the control
• I2C-BUS : two channels by set no touch is possible. (Bus connector in the
• PWM : 14 bit x 1, 7 bit x 9 conventional bus chassis is deleted.)
• ADC : 8 bit x 6 (Successive comparison system, • Substantial self diagnosis function
Conversion time 20ms) (1) B/W composite video signal generating function
• OSD (micom inside, green crossbar added)
Character kinds : 256 (2) Generating function of audio signal equivalent
Character display : 24 characters x 12 lines to 1kHz (micom inside)
Character dot : 14 x 18 dots (3) Detecting function of power protection circuit
Character size : 3 kinds (Selected by line) operation
Character color : 8 colors (Selected by character) (4) Detecting function of abnormality in IIC bus
Display position : Horizontal 128 steps, Vertical line
256 steps (5) Functions of LED blink indication and OSD
This microcomputer performs functions of AD converter, indication
reception of U/V TV and OSD display in one chip. (6) Block diagnosis function which uses new VCD
and AV SW

SDA

SCL 1-7 9 1-7 9 1-7 8 9

8 8

START ADDRESS R/W Ack DATA Ack DATA Ack STOP

CONDITION CONDITION
Approx.180mS Some device may have no data,
or may have data with several
bytes continuing.

Fig. 3-1

26
4. MICROCOMPUTER TERMINAL FUNCTION

TMP87CS38N3152 (QA01)

GND 1 GND VDD 42 VDD

BAL 2 I P40 (PWM0) P57 I 41 ACP

REM OUT 3 O P41 (PWM1) P32 40 NC

MUTE 4 O P42 (PWM2) P57 39 GND

SP MUTE 5 O P43 (PWM3) SDA0 IO 38 SDA1

IIC-
BUS
NC 6 O P44 (PWM4) SCL0 O 37 SCL1

POWER 7 O P45 (PWM5) (TC3)P31 I 36 SYNC AV1

LED 8 O P46 (PWM6) (RXIN)P30 I 35 RMT IN

NC 9 O P47 (PWM7) P20 I 34 SW IN

NC 10 I P50 (PWM8/TC2) RESET I 33 RESET

SCL0 11 O P51 (SCL1) XOUT O 32 XOUT

IIC
-BUS
SDA0 12 IO P52 (SDA1) XIN I 31 XIN

SYNC VCD 13 I P53 (AINO/TC1) TEST I 30 TEST

NC 14 I P54 (AIN1) 0SC2 O 29 0SC1

AFT2 15 I P55 (AIN2) 0SC1 I 28 0SC2

AFT1 16 I P56 (AIN3) VD I 27 VSYNC

KEY-A 17 I P60 (AIN4) HD I 26 HSYNC

KEY-B 18 I P61 (AIN5) Y/BL O 25 Ys

SGV 19 O P62 B O 24 BOUT
SGA 20 O P63 G O 23 GOUT
GND 21 VSS R O 22 ROUT

Fig. 3-2

27
<< MICROCOMPUTER TERMINAL NAME AND OPERATION LOGIC >>
No. Terminal Name Function In/Out Logic Remarks
1 GND 0V
2 BAL INPUT BALANCE Out PWM out
3 REM OUT REMOTE CONTROL Out Remote control output
SIGNAL OUT
4 MUTE SOUND MUTE OUT Out Sound mute output
5 SP MUTE SPEAKER MUTE Out In muting = H
6 DEF POW Out
7 POWER POWER ON/OFF OUT Out Power control In ON=H
8 LED POWER LED OUTPUT Out Power LED on-control
LED lighting=L
9 POWER LNB Out 0V
10 LNB DET In 0V
11 SCL() IIC BUS CLOCK OUT Out IIC bus clock output 0
12 SDA() IIC BUS DATA IN/OUT In/Out IIC bus data input/output 0
13 SYNC VCD H SYNC INPUT In Main picture H. sync signal input
14
15 AFT2 IN In Sub tuner AFT S-curve input
16 AFT1 UV MAIN S-CURVE In Main tuner AFT S-curve
SIGNAL signal input
17 KEY A LOCAL KEY INPUT In Local key detection: 0 to 5V
18 KEY B LOCAL KEY INPUT In Local key detection: 0 to 5V
19 SGV TEST SIGNAL OUT Out Test signal output In normal=L 0V
20 SGA TEST AUDIO OUT Out Test audio output In normal=L 0V
21 VSS POWER GROUNDING — 0V: Gounding voltage 0V
22 R R Out At display on:Pulse
23 G G Out At dispaly on:Pulse
24 B B Out At dispaly on:Pulse
25 Y/BL BL Out At dispaly on:Pulse
26 HSYNC In HSYNC for OSD display Pulse
27 VSYNC In VSYNC for OSD display Pulse
28 OSC1 DISPLAY CLOCK Out 4.5MHz Pulse
29 OSC2 DISPLAY CLOCK In Pulse
30 TEST TEST MODE In GND fixed 0V
31 XIN SYSTEM CLOCK In System clock input 8MHz pulse
32 XOUT SYSTEM CLOCK Out System clock output 8MHz 8MHz pulse
33 RESET SYSTEM RESET In System reset input (In reset=L) 5V
34 SW IN
35 RMT IN REMOTE CONTROL IN In remote control pulse input=L In reception of
SIGNAL INPUT remote pulse
36 SYNC AV1 HSYNC INPUT In External H. sync signal input Pulse
37 SCL1 IIC BUS CLOCK OUT Out IIC bus clock output 1 Pulse
38 SDA1 IIC BUS DATA IN/OUT In/Out IIC bus data input/output 1 Pulse
39 GND 0V
40 NC
41 ACP NSYNC INPUT In AC pulse input
42 VDD POWER — 5V 5V

28
5. EEPROM (QA02)
EEPROM (Non volatile memory) has function which, in spite of power-off, memorizes the such condition as channel selecting
data, last memory status, user control and digital processor data. The capacity of EEPROM is 8k bits. Type name is 24LC04BI/
P or ST24C04CB6, and those are the same in pin allocation and function, and are exchangeable each other. This IC controls
through I2C bus. The power supply of EEPROM and MICOM is common. Pin function of EEPROM is shown in Figure 3-3.

EEPROM(QA02)

A0 1 8 Vcc + 5V
Device adress
A1 2 7 NC
GND
A2 3 6 SCL
I2C-BUS line
Vss 4 5 SDA

Fig. 3-3

6. ON SCREEN FUNCTION

ON SCREEN FUNCTION indicates data like channel, volume. Formerly, exclusive use of OSD IC was used, but in N5SS,
OSD function is involved in microcomputer. Pin function concerning on-screen is shown in figure 3-4. Oscillation clock of OSD
is approx. 4.5MHz. 9MHz which becomes twice in microcomputer is dot clock. For oscillation coil, TRF1160D (LA02) is used.

QA01

OSC2 O 29 OSC2 OSC OUT

OSC1 I 28 OSC1 OSC IN

VD I 27 VSYNC H. SYNC SIGNAL

HD I 26 HSYNC V. SYNC SIGNAL

Y/BL O 25 Ys/Ym HALF TONE SIGNAL

B O 24 BOUT

G O 23 GOUT COLOR SIGNAL

R O 22 ROUT
VG

Fig. 3-4

29
7. SYSTEM BLOCK DIAGRAM
QA01
TMP87CS38N-3152

QA02 SDA 1 38
SCL 1 37 H001
MEMORY
24LC04B1/P
MAIN U/V TUNER
SDA SCL RMT 35 REMOTE
EL446L
SENSOR
5 6 UNIT SDA SCL

11 SCL 0
12 SDA 0 HY01

SUB U/V TUNER

KEY-A 17 EL922L
KEY SWITCH
H. SYNC PULSE 26 HSYNC KEY-B 18 SDA SCL
VSYNC PULSE 27 VSYNC
RST 33
22 R POWER
VDD 42 Q501
VIDEO SIGNAL SUPPLY
PROCESS 23 G GND 1 CIRCUIT
CIRCUIT VCD
24 B VSS 21 TA1222
25 YS/TM POWER 7 SDA SCL
ACP 41 27 28
REMOTE CONTROL 3 RMT OUT
OUTPUT LED 8
H002
SOUND MUTE 4 MUTE XIN 31 8MHz
IF/MPX
SPEAKER MUTE 5 SP MUTE XOUT 32 CLOCK MVUS345
SDA SCL
Q701 OSCI 28 6.1MHz
21 20
OSCO 29 CLOCK
C/C, EDS
XC144144P SGV 19
DATA CLK SIGNAL
SGA 20 OUTPUT

MAIN SCREEN

SYNC-AV1 36 SYNC DET. QV01

AFT1 IN 16 AFT DET. AV SW

DPC UNIT TA1219N
SUB SCREEN SDA SCL
DATA CLK
SYCN-AV2 13 SYNC DET. 26 27
AFT2 IN 2 AFT DET.
QM01
QY04
DSP

SDA SCL
PIP CONTROL

DATA CLK
6 5

Fig. 3-5

30
8. LOCAL KEY DETECTION METHOD

Local key detection in the N5SS chassis is carried out by

using analog like method which detects
a voltage appears at local key input terminals (pins 17, 18) of
15 16
the microcomputer when a key is
pushed. With this method using two local key input terminals
S15-1 S16-1
( pins 17,18), key detection up to
maximum 14 keys will be carried out.

S15-2 S16-2
The circuit diagram shown left is the local key circuit. As can
be seen from the diagram, when
one of key among SA-01 to SA-08 is pressed, each of two
S15-3 S16-3 input terminal (pins 17, 18) developes
a voltage Vin corresponding to the key pressed. (The voltage
measurement and key identification
S15-4 S16-4 are carried out by an A/D converter inside the microcomputer
and the software.

S15-5 S16-5

S15-6 S16-6

S15-7 S16-7

Fig. 3-6. Local key assignment

Key No. Function Key No. Function

SA-02 POWER SA-01 DEMO START/STOP
SA-03 CH UP
SA-04 CH DN
SA-05 VOL UP
SA-06 VOL DN
SA-07 ANT/VIDEO, ADV
SA-08 MENU

Table 3-1. Local key assinment

31
9. REMOTE CONTROL CODE ASSIGNMENT

Custom codes are 40-BFH Custom codes are 40-BFH

Applicable Applicable
Code Function to remote Applicable Conti- Code Function to remote Applicable Conti-
to TV set nuty to TV set nuty
control control
00H 0 Channel 50H PIP STILL
01H 1 Channel 51H PIP ON/OFF
02H 2 Channel 52H Do not use. Old type core power ON
03H 3 Channel 53H PIP SWAP
04H 4 Channel 54H PIC SIZE
05H 5 Channel 55H DSP F/R
06H 6 Channel 56H WIDE/SCROLL
07H 6 Channel 57H CAPTION
08H 8 Channel 58H EXIT
09H 8 Channel 59H CYCLONE, SBS
0AH 100 Channel 5AH SER UP
0BH ANT 1/2 5BH OPTION
0CH RESET 5CH SUB WOOFER UP
0DH AUDIO 5DH SUB WOOFER DOWN
0EH PICTURE/FUNC 5EH
0FH TV/VIDEO 5FH
10H MUTE 80H MENU
11H CHANNEL SEARCH 81H EDS
12H POWER 82H ADV UP
13H MTS 83H ADV DWN
14H ADD/ERASE 84H
15H TIMER/CLOCK 85H
16H AUTO PROGRAM 86H
17H CHANNEL RETURN 87H
18H DSP/SUR (TV/CATV) 88H PIP CONTROL
19H CONTROL UP 89H
1AH VOLUME UP 8AH
1BH CHANNEL UP 8BH
1CH RECALL 8CH
1DH CONTROL DOWN 8DH
1EH VOLUME DOWN 8EH
1FH CHANNEL DOWN 8FH
40H PIP LOCATE 90H
41H PIP LOCATE 91H
42H PIP LOCATE 92H
43H PIP LOCATE 93H
44H CARVER 94H Do not use. Old type core power ON
45H SURROUND UP 95H
46H SURROUND DOWN 96H
47H VOCAL ZOOM 97H NOISE CLEAN
48H CHANNEL LOCK 98H
49H 99H
4AH PIP CHANNEL UP 9AH PIP VOLUME UP
4BH PIP CHANNEL DOWN 9BH
4CH PIP STILL/RELEASE 9CH PIP CONTROL
4DH PIP ZOOM, ZOOM SIZE 9DH
4EH PIP LOCATE 9EH PIP VOLUME DOWN
4FH PIP SOURCE 9FH

32
 Custom codes are 40-BFH Custom codes are 40-BFH
Applicable
Code Applicable Conti- Code Applicable Conti-
Function to remote Function
control to TV set nuty to TV set nuty

C0H A0H SUB-BRIGHT ADJUSTMENT

C1H A1H G. DRIVE ADJUSTMENT
C2H A2H B. DRIVE ADJUSTMENT
C3H A3H
C4H PIP LOCATE A4H CUTOFF DRIVE 40H INITIALIZING, HORIZONTAL ONE LINE
C5H PIP LOCATE A5H R. CUTOFF ADJUSTMENT
C6H PIP LOCATE A6H G. CUTOFF ADJUSTMENT
C7H PIP LOCATE A7H B. CUTOFF ADJUSTMENT
C8H PIP STROBE A8H MEMORY ALL AREA INITIALIZE
C9H PIP STROBE SPEED A9H PIP BRIGHT ADJUSTMENT
CAH PIP CHANNEL SEARCH AAH SUB CONTRAST ADJUSTMENT
CBH ABH HOR, VER PICTURE POSITON ADJUSTMENT
CCH ACH SUB COLOR ADJUSTMENT
CDH ADH SUB TINT ADJUSTMNET
CEH AEH ADJUSTMENT-UP
DFH AFH ADJUSTMENT-DOWN
D0H B0H HORIZONTAL ONE LINE: SERVICE
D1H B1H DSP ON/OFF
D2H Do not use. Old type core power ON B2H TEXT-1
D3H B3H TV/PIP VIDEO CHANGE-OVER
D4H B4H CAPTION-1
D5H B5H
D6H B6H
D7H PIP VIDEO ADJ. B7H TV/CABLE CHANGE-OVER IN SAME TIME ON MAN AND SUB
D8H STILL, FRAME ADVANCE B8H HOTEL SETTING MENU
D9H B9H DATA 4 TIMES SPEED UP
DAH SPEED BAH DATA 4 TIMES SPEED DOWN
DBH BBH CHANGE-OVER OF HOTEL/NORMAL
DCH ZOOM BCH PIP CENTER
DDH BDH M MODE
DEH BEH CAPTON OFF
DFH BFH ALL CHANNEL PRESET

33
 Custom codes are 40-BFH

Code Applicable Conti-

Function
to TV set nuty

E0H PINCUTION/EW CORER (PARA/CNR)

E1H VERTICAL S-CUVE CORRECTION/VERTICAL M-CURVE CORRECTION (VSC/FVC)

E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH HORIZONTAL WIDTH (WID/PARA)
EBH TRAPEZOIDE CORRECTION (TRAP)
ECH TEST TONE
EDH DOLBY
EEH 3 DIMENTIONAL Y/C SEPARATION
EFH DPC
E0H STANDARD (HEIGHT LINEARITY) (VLIN/HIT)
E1H WIDE (HEIGHT LINEARITY) (VLIN)
F2H SCROOL
F3H WIDE 1, 2, 3
F4H
F5H
F6H
F7H
F8H
F9H
FAH
FBH
FCH
FDH
FEH
FFH

34
10. ENTERING TO SERVICE MODE 12. SERVICE ADJUSTMENT
1. PROCEDURE 1. ADJUSTMENT MENU INDICATION ON/OFF :
(1) Press once MUTE key of remote hand unit to MENU key ( on TV set)
indicate MUTE on screen. 2. During display of adjustment menu, the followings are
(2) Press again MUTE key of remote hand unit to keep effective.
pressing until the next procedure. a) Selection of adjustment item :
(3) In the status of above (2), wait for disappearing of POS UP/DN key (on TV/remote unit)
indication on screen. b) Adjustment of each item :
(4) In the status of above (3), press MENU (Channel VOL UP/ DN key (on TV / remote unit)
setting) key on TV set. c) Direct selection of adjustment item
R CUTOFF : 1 POS (remote unit)
2. Service mode is not memorized as the last-memory. G CUTOFF : 2 POS (remote unit)
3. During service mode, indication S is displayed at upper B CUTOFF : 3 POS (remote unit)
right corner on screen. d) Data setting for PC unit adjustment
SUB CONTRAST : 4 POS (remote unit)
11. TEST SIGNAL SELECTION SUB COLOR : 5 POS (remote unit)
SUB TINT : 6 POS (remote unit)
1. In OFF state of test signal, SGA terminal (Pin 20) and e) Horizontal line ON/OFF : VIDEO (TV)
SGV terminal (Pin 21) are kept “L” condition. f) Test signal selection : VIDEO (remote unit)
2. The function of VIDEO test signal selection is cyclically * In service mode, serviceable items are limited.
changed with VIDEO key (remote unit).
3. Test audio signal ON / OFF : 8 POS (remote unit)
Test Signal No. Name of Pattern * Test audio signal : 1kHz
0 Signal OFF
1 All black signal + R single color (OSD) 4. Self check display : 9 POS (remote unit)
2 All black signal + G single color (OSD) * Cyclic display (including ON/OFF)
3 All black signal + B single color (OSD)
4 All black signal 5. Initialization of memory :
5 All white signal CALL (remote unit) + POS UP (TV)
6 W/B 6. Initialization of self check data :
7 Black cross bar CALL (remote unit) + POS DN (TV)
8 White cross bar 7. BUS OFF :
9 Black cross hatch CALL (remote unit) + VOL UP (TV)
10 White cross hatch
11 White cross dot
12 Black cross dot
13 H signal (bright area)
14 H signal (dark area)
15 Black cross + G

(3) SGA (audio test signal) output should be square

wave of 1kHz.

35
13. FAILURE DIAGNOSIS PROCEDURE

Model of N5SS chassis is equipped with self diagnosis function inside for trouble shooting.
1. CONTENTS TO BE CONFIRMED BY CUSTOMER

Contents of self diagnosis Display items and actual operation

A. DISPLAY OF FAILURE INFORMATION
IN NO PICTURE
(Condition of display)
1. When power protection circuit operates;
2. When I2C-BUS line is shorted;
Power indicator lamp blinks and picture does not come.
1. Power indicator red lamp blinks. (0.5 seconds interval)
2. Power indicator red lamp blinks. (1 seconds interval)
If these indication appears, repairing work is required.

2. CONTENTS TO BE CONFIRMED IN SERVICE WORK (Check in self diagnosis mode)

Contents of self diagnosis Display items and actual operation

Contents of self diagnosis Display items and actual operation
<Countermeasure in case that phenomenon
always arises.>
B. Detection of shortage in BUS line (Example of screen display)
C. Check of comunication status in BUS line
SELF CHECK
D.Check of signal line by sync signal detection
No. 2390XXXX Part code of QA01 E
E. Indication of part code of microcom.(QA01)
POWER : 000000 Number of operation of F
F. Number of operation of power protection circuit
power protection circuit
BUS LINE : OK Short check of bus line B
BUS CONT : OK Comunication check of C
busline
BLOCK : UV V1 V2 D
QV01, QV01S
Fig. 2-4

3. EXECUTING SELF DIAGNOSIS FUNCTION

[CAUTION]
(1) When executing block diagnosis, get the desired input mode (U/V BS VIDEO1,2,3) screen, and then enter the self diagnosis
mode.
(2) When diagnos other input mode, do again diagnosis operation.

(PROCEDURE)
(1) Set to service mode.
(2) Pressing “9” key on remote unit displays self diagnosis result on screen.
Every pressing changes mode as below.
SERVICE mode SELF DIAGNOSIS mode

(3) To exit from service mode, turn power off.

36
4. UNDERSTANDING SELF DIAGNOSIS INDICATION
In case that phenomenon always arises. See figure 3-4 .

Item Contents Instruction of results

BUS LINE Detection of bus line short
BUS CONT Communication state of bus line
BLOCK:BS The sync signal part in
UV1 each video signal supplied from
UV2 each block is detected.
V1 Then by checking the existence or
V2 non of sync part, the result of self
diagnosis is displayed on screen.
Besides, when “9” key on remote
unit is pressed,diagnosis operation
is first executed once.
Indication of OK for normal result, NG for abnormal
Indication of OK for normal result
Indication of failure place in abnormality
(Failure place to be indicated)
QA02 NG, H001 NG, Q501 NG, H002 NG
QV01 NG, Q302 NG, QY02 NG, HY01 NG
QD04 NG, QM01 NG, Q701 NG
Note 1. The indication of failure place is only one place
though failure places are plural. When repair of a
failure place finishes, the next failure place is indi
cated. (The order of priority of indication is left side.)
*Indication by color
• Normal block : Green
• Non diagnosis block : Cyan

<Clearing method of self diagnosis result>

In the error count state of screen, press “CHANNEL DOWN” button on TV set pressing “DISPLAY” button on
remote unit.

[CAUTION] White
All ways keep the following caution, in the state of Yellow
service mode screen. Cyan
Green
• Do not press “CHANNEL UP” button. This will cause
Magenta
initialization of memory IC. (Replacement of memory IC is Red
required. Blue
• Do not initialize self diagnosis result. This will change user
( COLOR BAR SIGNAL)
adjusting contents to factory setting value. ( Adjustment is
Color elements are positioned in sequence of high brightness.
required.)

<Method utilizing inner signal> (VIDEO INPUT 1 terminal should be open.)

(1) With service mode screen, press VIDEO button on remote unit. If inner video signal can be received, QV01 and after are normal.
(2) With service mode screen, press “8” button on remote unit. If sound of 1kHz can be heard, QV01 and after are normal.
* By utilizing signal of VIDEO input terminal, each circuit can be checked. (Composite video signal, audio signal)

37
14. TROUBLE SHOOTING CHART
(1) TV DOES NOT TURNED ON

TV does not turned on.

YES
Relay sound
NO
NG
Check of voltage at pin 7 of QA01
(DC 5V).
OK
Check power circuit.

NG
8MHz oscillation waveform
at pin 32 of QA01.
OK
Check OSC circuit.
Replace QA01.
NG
Pulse output at pins 37 and 38 of QA01.

OK
NG
Voltage check at pin 32 of QA01
(DC 5V)

Check reset circuit.

OK

Check relay driving circuit. Replace QA01.

38
(2) NO ACCEPTION OF KEY-IN

Key on TV

Voltage change at pins 17, 18 of NG

QA01 (5V to 0V).

OK
Check key-in circuit.

Replace QA01.

Remote unit key

Pulse input at pin 35 of QA01, NG

When remote unit key is pressed.

OK

Replace QA01 Check tuner power circuit.

(3) NO PICTURE (SNOW NOISE)

No picture

NG
Voltage at pins of +5V, and 32V.

OK

Check H001. Check tuner power circuit.

39
(4) MEMORY CIRCUIT CHECK

Memory circuit check

NG
Voltage check at pin 8 of QA02 (5V).

OK Check power circuit.

NG
Pulse input at pins 5 and 6 of QA02
in memorizing operation.

OK

Check QA01.

Replace QA02.

Note: Use replacement parts for QA02.

Adjust items of TV set adjustment.

(5) NO INDICATION ON SCREEN

No indication on screen.

NG
Check of character signal at pin 23
of QA01. (5VP-P )

OK
Check V/C/D circuit.

Input of OSC waveform at pin 29 of QA01 NG

with indication key pressed.

OK
Check OSC circuit.

Check of sync signal at pins 26, 27 of QA01.

OK
Check sync circuit.

Replace QA01.

40
 SECTION IV
AUDIO OUTPUT CIRCUIT

41
1. OUTLINE

Configuration of the audio circuit and signal flow are given

in Fig 4-1.

A/V PCB

VIF+MTS+S.PRO
MODULE ICV01 FOR PIP
IF MODULE
R 12 EQ 6 R L 29
MOTHER CHILD
TV TV R 31 AUDIO
L 14 ER 7 L

L 2 L PIP OUT
R L
VIDEO 1 11 L R 1 R (AUDIO)
VIDEO 1
13 R
R L
VIDEO 2 3 L VIDEO
VIDEO 2
9 R OUTPUT
TERMINAL VIF+MTS+A.PRO Q670
R L MODULE
VIDEO 3 15 L R
(FRONT INPUT) VIDEO 3 R out 25 2 12
17 R R
R 35 AS DSP 16 R L
L out 24 4 2
CIRCUIT
L 37 AR 18 L W
W out 22 1 11 L

PIP W
OUTPUT
R L
VARIABLE
AUDIO OUTPUT AI
TERMINAL
AJ

Fig. 4-1

42
2. AUDIO OUT IC
2-1. OUTLINE
In the model, CN32E90, the main amplifiers and woofer
output amplifiers use bipolar IC TA8256H and develop out
powers of 10W x 2+13W.

2-2. THORY OF OPERATION

2-2-1. Operatin of TA8256H
The TA8256H is a modified version of TA8128AH used in
the N4SS chassis as an audio ouput IC. In the TA8256H, one
channel is added and a total of 3 channels can be used, but
performance for each channel is the same as that of the
TA8218H. Fig. 4-2 shows a block diagram of the IC.

Vcc
25.5V
47mF

6 9
1mF RIPPLE FILTER Vcc
4k
L 4 OUTPUT-2 470mF
L AMP-2 8
30k
2.2W
RL (L)
350W 0.12mF
3 POW 10
PRE
GND GND
0.12mF
47mF 350W RL (R)
2.2W
(R)
1mF AMP-3 12
OUTPUT-3 470mF
R 2
R 4k
30k 5 (mute)

MUTING
(mute Tc)
7
30k
1mF 4k
W 1 OUTPUT-3 1000mF
W AMP-1 11
350W
(S) or (W) 2.2W
RL (W)
0.12mF
20kW

Fig. 4-2

43
 SECTION V
A/V SWITCHING CIRCUIT

44
1. OUTLINE

A/V switching circuit performs change-over of video and

audio signals from tuner and external input. The selecting
operation is controlled by microcomputer through IIC bus.

2. IN / OUT TERMINALS

INNER INPUT U/V Tuner (Main)

U/V Tuner (Sub) .................................. For sub picture (PIP)
EXTERNAL INPUT VIDEO1 With S-terminal
VIDEO2
VIDEO3 (Front) With S-terminal ........ Excepting CF35E50, CL37E56, CE35E15
VIDEO3 (Back) .................................. Only for CF35E50, CL37E56, CE35E15
OUTPUT VIDEO OUTPUT (V, L, R) .................... Excepting CN27E90
AUDIO ON SUB-PICTURE ................... Only for CN32E90, CN35E90, CN35E95

3. CIRCUIT OPERATION

This circuit consists of A/V SW IC; TA1218N (QV01), and

selects signals from U/V tuner (Main), U/V tuner (Sub),
E1, E2 and E3.

3-1 COMPOSITE VIDEO SIGNAL

The selected video signal is output to pin 38 of QV01, and
separated by comb filter into Y and C. The resulted signal
is input to pins 30 and 32 of QV01, and is output to pins 36
and 34 to be supplied to Q501 (V/C/D).
Video signal for sub picture is output to pin 42 of QV01, and
is supplied to PIP unit (ZY01).

3-2 S-VIDEO SIGNAL

When a cable is connected to S-VIDEO terminal, inner
switch of S-VIDEO terminal is shorted to ground to turn off
the transistor (QV05 for VIDEO1 input) for S-VIDEO
terminal detection. Then chroma input terminal (Pin 14 for
VIDEO1 input) of QV01 turns open. From pins 36 and 34
(Y/C output) of QV01, Y/C signal of selected source is
output.

45
AV SW CIRCUIT

TUNR/IMA TIF
L/R V out V Aout

EQ DSP
QV01 TA1218N
L/R in

18 C in
QA01
17 R in SYNC OUT 26 SYNC in
VIDEO 3
16 S in

15 L in PIP TV in 28

14 C in PIP L in 29 COMB
FILTER
13 R in Y in 30 Y out
VIDEO 1
12 S in PIP R in 31 V in

11 L in C in 32 C out

10 V in

9 R in C out 34 C in
VIDEO 2
R out 35 Q501
8 L in

7 V in Y out 36 Y in

6 R in L out 37

5 L in H out 38

2 PIP R out
PIP AUDIO PIP
OUT
1 PIP L out PIP V out 42 V in

MONITOR
OUT

Fig. 5-1

46
 SECTION VI
VIDEO PROCESSING CIRCUIT

47
1. OUTLINE
This circuit converts and amplifies video signal (Luminance
and chroma signals) separated into Y/C, to original color
signal, and is supplied to CRT Drive circuit.
2. SIGNAL FLOW
Signal flow chart is shown in fig. 6-2 Block diagram.
(1) Luminance signal is input to pin 15 of Q501, and enters
into delayline inside Q501 to be output to pin 4.
(2) Chroma signal is input to pin 13, and I/Q signal which
is demodulated in color, is output to pins 5 and 6, and
next supplied to pins 51 and 52.
(3) The signal is processed on luminance and chroma
48
signals, and is converted to original color signal (R,G,B)
by RGB matrix. Next the signal is superimposed with
OSD signal to be output to pins 41, 42 and 43, and is
supplied to CRT Drive circuit.
(4) The signal for Scan Modulation is processed with
differential in Q501 to be output to pin 48 Besides, at
terminal for adjustment TP501, luminance and chroma
signals are automatically output according to the selected
items of service mode.
3. CIRCUIT OPERATION
All processing operation of video signal are done inside
Q501. The outline of Q501 (TA1222N) is explained in the
next section. Here, major terminals excepting input/output
terminals of Q501 are described.
Terminals concerning Video / Chroma circuit of Q501 are explained here.

#1 CW OUTPUT 3.58MHz which is synchronized to burst signal is output, and is used for clock of comb filter.
#2 SCP OUTPUT The signal which is superimposed with burst gate pulse and blanking pulse is output. It is not
used in this time.
#3 SECAM CONTROL When receiving SECAM (Color system of East Europe) signal, it produces DC output. It is not
used in this time.
#4 Y1 OUTPUT Luminance signal of Y1 input (# 15) is output through delay line.
#5 Q OUTPUT Chroma signal of #13 is demodulated in IQ, and Q signal is output.
#6 I OUTPUT I signal of those of IQ demodulated is output.
#7 1H DL CONTROL Color demodulation control signal of PAL, SECAM system (European color system) is output.
It is not used in this time.
#8 XTAL 3 Crystal oscillator terminal. Not used.
#9 XTAL 2 Ditto
# 10 XTAL 1 3.58MHz crystal oscillation terminal.
# 11 APC FILTER Color sync. phase detecting terminal.
# 12 Vcc 1 5V source (chroma line) terminal
# 13 C INPUT Color signal input terminal
# 14 GND Grounding terminal of chroma circuit
# 15 Y1 INPUT Luminance signal input terminal
# 32 PIP Ys Input terminal for switching pulse signal of PIP signal
# 33 PIP B Input terminal of PIP RGB signal
# 34 PIP G Ditto
# 35 PIP R Ditto
# 36 OSD Ys Input terminal for switching pulse signal of OSD signal
# 37 OSD B Input terminal for OSD RGB signal
# 38 OSD G Ditto
# 39 OSD R Ditto
# 40 Vcc 2 +9V source terminal
# 41 B OUTPUT RGB output terminal
# 42 G OUTPUT Ditto
# 43 R OUTPUT Ditto
# 44 GND Ground terminal of Y, color difference, RGB circuits
# 45 ABL Input terminal for ABL control
# 46 Vcc 3 +9V source terminal
# 47 Ym Input terminal for half tone control pulse which is supplied from
microcomputer
# 48 VSM Output terminal of velocity modulation signal
# 49 APL DET Detects average level of video signal for correcting DC transmission
# 50 BLACK DET Detects black area in video signal for black expanding circuit
# 51 I INPUT Input signal for I signal of IQ demodulation signal
# 52 Q INPUT Input signal for Q signal of IQ demodulation signal
# 53 Y2 INPUT Input terminal for Y-picture control circuit
# 54 COL Terminal for peak hold of color limiter
# 55 DAC 1 Test point (TP501) output terminal
# 56 DAC 2 External circuit control terminal (Not used)

49
 0.6V(P)
TO COMB
CW OUTPUT DAC 2 (2bit)

56
COLOR IDENT. OUTPUT

1
DAC 1 (1bit)
SCP OUTPUT MONITOR OUTPUT

55
2
SECAM CONTROL COLOR LIMITER

54
3
1V(P-P)
Y1 OUTPUT Y2 INPUT

53
4

1V(P) 300mV
Q OUTPUT Q INPUT

52
5
I OUTPUT I INPUT

(P)
51
6
1H DL CONTROL BLACK PEAK HOLD

50
7
XTAL 3 APL DET.
4.43
or

49
N

8
XTAL 2 VSM OUTPUT

48
M

9
XTAL 1 Ym INPUT
3.58

10

47
POWER OFF INPUT
APC FILTER Vcc 3
11

46
Vcc 1 (+5V) ABL INPUT
12

45
300mV(P)

Y, COLOR DIFFERENCE,
CHROMA INPUT
13

RGB GND

44
CHROMA GND R OUTPUT
14

43
1V(P)

Y1 INPUT G OUTPUT

2.5V(P)(typ)
2.8V(P)(typ)
15

42
V. SEP. B OUTPUT
16

41
Vcc 2 (+9V)
1V(P)

SYNC INPUT
17

SYNC OUTPUT R ANALOG OSD INPUT 40

18

39

DEF GND

0.5V(P)(typ)
from OSD mCom
G ANALOG OSD INPUT
or R
pull

19

38

AFC 1 B ANALOG OSD INPUT

20

37

32 x FH Ys ANALOG OSD INPUT

21

36

DEF Vcc (+9V) R INPUT

22

35
+B

H. OUT G INPUT
23

34

from PIP/TEXT 0.5V (P)(typ)

BENDING CORRECT B INPUT

24

33

AFC PULSE INPUT

BLK INPUT Ys INPUT
25

32
7.5V
1.0V(DIR)
7.5V(AFC)

DIGITAL GND VP OUTPUT

26

31

8H

HD OUTPUT
SDA EXTERNAL BPP INPUT
27

30

1yb

SCL DAC GND

28

29
<SDA>
<SCL>

peak to peak.
V(P) denotes value of
<5V

Fig. 6-1 TA1222N VCD IC PIN LAYOUT CHART

50
 5 6 4 53 52 51 48
Q I Y Y I/Q VM VELOCITY
MODULATION

C COLOR COLOR SIGNAL

From A/V Board C 13 PROCESSING 43
DEMOD.
RGB RGB
42 CRT DRIVE
MATRIX SW
Y DELAY LUMINANCE
Y 15 SIGNAL
41
LINE
PROCESSING

51
Sync
17
SYNC/DEF
PROCESSING
OSD

R G B Ys Ym

23 31 55 39 38 37 36 47
Q501 V/C/D

Fig. 6-2 Block diagram of Video Processing circuit

TP501

H.OUT VP
Microcomputer OSD
or EDS or C.C
SECTION VII
V/C/D/IC

52
1. OUTLINE
This IC enables more precise picture setting than that of former IC (TA8845N) by means of large scale employment
of IIC bus, and reduces many peripheral components by containing filters inside.
The main features (comparing TA8845) are as follows.

2. LARGE SCALE EMPLOYMENT OF BUS CONTROL OF PARAMETER FOR PICTURE

CONTROLS
(Soft method of picture making)
(Former/TA8845N) TA1222N
* Black expanding start point External constant BUS control
* DC transmission correction quantity point External constant BUS control
* Black level correction quantity External constant BUS control
* Each ABCL characteristic External constant BUS control

3. EMPLOYMENT OF CONTAINING EACH VIDEO BAND FILTER INSIDE

(Employment of automatic adjustment circuit by Fsc to absorb deviation
/ Employment of deviation aborbing method by high S/N filter and mask triming using fixed CR)
(Former/TA8845N) TA1222N
* Y-DL Apa-con DL inside Inside
* Chroma TOF/BPF External Inside
*Velocity modulation processing circuit External Inside
* Fsc trap for chroma demodulation output External Inside

4. EMPLOYMENT OF CONTAINING EACH FILTER (FOR S/H) INSIDE

(Circuit operation by extremely low current
/ Employment of leak current cancel circuit
/ Employment of detection circuit which does not suffer from influence of stray capacity)
(Former/TA8845N) TA1222N
* Chroma ACC / killer filter External Inside
* Y / color difference clamp filter External Inside
* Filter for filter automatic adjustment External Inside
* AFC 2 filter External Inside

5. LOW COST OF IC
* Involving peripheral components inside ——> Down sizing of chip ——> Newly employment (NPN Tr area
ratio to former : -25%) of miniature process (PLAS-1 S process)
* Involving peripheral components inside——>Increasing of power consumption——>2 power supply system
(5V / 9V used)
* Involving peripheral components inside ——> Reducing of number of elements ——> Employment of new
circuit
(1) Reducing of gate (change of preset method) of register for IIC decoder
(2) Reducing of DAC elements (employment of rudder type DAC + temperature compensation circuit)
(3) Deletion of chroma CW, ACC (employment of 90 degree shift phase circuit with automatic adjustment)

53
VCD BLOCK DIAGRAM (TA1222N)

CORRECTION
BLK/AFC IN

BENDING
3'5" VCD
SYNC IN

Daf vCC

H. out
AFC1
17 20 21 25 24 19 22 23
GND (DEF) VCC (DEF)
H. V. PHASE DET PHASE DET H. PHASE H. DUTY
32 FM VCO H. BLK H. DRIVE
SYNC SEP <APC-1> <APC-2> SHIFT SW

H. H. Y.
V. Sep 16 V. SEP Y.P OUT 31 VER OUT
COUNT DOWN PARABOLA COUNT DOWN

V. SYNC
18 SYNC OUT
SYNC SEP OUT
27 SDA
SYNC CHIP DELAY D/A I2C BUS
Y IN 15 FDC TRAP SW REGISTER 26 GND
CLAMP LINE CONVERTER DECODER
19 SCL
BPF DELAY LINE DELAY LINE S W 4 Y1 OUT

CHROMA IN 13 SW TOK
29 GND
GND
GAMMA BLACK BLACK
GND 34 ACC AMP TOF SW Y. CLAMP 53 Y2 OUT
CORRECTION LEVEL COR. STRETON
VCC
9V 12
SUB B.C BLACK WHITE
(88) ACC DET A.P.L DET 30 BLACK PEAK
COLOR RESTORE PEAK DET PEAK DET HOLD
39 APL DET
P/N IDENT CHROMA SHARPNESS
APC FILTER 11 APC DET HPF TM AMP VM MUTE 28 VM OUT
BET BLK S DELAY LINE
R
T
X tal-1 CHROMA CW CHROMA SHARPNESS
10 T. NR AMP SUB CONT UNI COLOR
(3.58MHz) VCO MATRIX DEMOD. CONTROL
VCC 26
X tal-2 (PAL) 9 (98)
FILTER LPH 5 Q OUT
WPS HALF TONE CLAMP
AUTO ADJ FSC TRAP
X tal-3 (PAL) 8 6 Y OUT

I IN 51 33 B IN

IQ/UV FRESH IQ UV RGB

Q IN 52 SW CLAMP CONTRAST 34 G IN
CLAMP COLOR CONVERT BRIGHT

35 R IN
UNI COLOR DELAY YS SW
COLOR TINF 36 OSD Ys IN
TIME
37 OSD B IN
AXIS HALF
CLAMP CLAMP OSD AMP 38 OSD G IN
G-Y MATRIX TONE
39 OSD R IN
COLOR COLOR
COLOR LIMITER 54 CDE YS SW 22 Ys IN
PEAK DET GAMMA

DAC 2 55
HI BRIGHT RGB PEAK
SW ABCL AMP 25 ABL IN
COLOR MATRIX ACL DET
DAC 2 56

SECAM CONTROL 3 SECAM COLOR

DAC 1/2 DRIVE CLAMP BLK
(FOR SECAM) CONTROL SYS IDENT

1H DL S.C.P HD OUT POWER OFF IN

CW OUT CUT OFF RGB OUT
CONTROL OUT EXT EFP IN YM SW
VCC (98) GND
1 7 2 30 47 46 44 41 42 43
EXPAND MATRIX
1H DL CONTROL
COLOR IDENT.

B OUT

R OUT
G OUT
YM IN
HD OUT/BLACK
(SAND CASTLE)
CW OUT/

(FOR PAL)

SCP OUT

54
SECTION VIII
PIP MODULE

55
PMUS 02H (SN:23148232)

B-Y OFFSET
R-Y OFFSET

TINT

RY54 RY55 RY50

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

PIN I/O NAME PIN I/O NAME

4V
1 0 YS 9 I 5V
0V

2 - NC 10 I GND
350µS

3 I GND 11 I VD 4.2V
0V
4.8V
4 O R OUT 4.1V 12 I HD 1µS
10µS 4.2V
4.8V 3.0V 6V
5 O G OUT 4.1V 13 I/O SCL Or
-0.9V 0V
4.8V
6 O B OUT 4.1V 14 I/O SCL B CHASSIS C CHASSIS

7 I GND 15 - NC
4.8V
8 I PIP VIDEO 2.8V

56
 PMUS02H
<BLOCK DIAGRAM OF PIP MODULE>

RY55 RY54

PIP VIDEO R OUT

8 36 VIDEO B-Y 14 51 BI BO 67 19 B-Y R OUT23 4
IN OUT IN G OUT
R-Y 13 49 RI RO 65 18 R-Y G OUT24 5
OUT IN B OUT
Y-OUT 12 SLICE 47 YI YO 64 16 YIN B OUT25 6

WAVE FORM
HD 10 78 HDCN HDPN18
57

MODULATION
76 VDCN VDPN16
VD 11
QY03 QY01
QY01
TC9083F mPC1832GT
mPC 1832GT
(PIP PROCESSOR) (PIP V/C/D)
(PIP V/C/D)

VD
11

HD
12
 SECTION IX
SYNC SEPARATION, H-AFC,
H-OSCILLATOR CIRCUITS

58
1. SYNC SEPARATION CIRCUIT

The sync separation circuit separates a sync signal from a

video signal and feeds it to an H and V deflection circuits.
The separation circuit consists of an amplitude separation (H
and V sync separation circuit) and a frequency separation
circuit (V sync separation circuit) which performs the
separation by using a frequency difference between H and V.
In the N5SS chassis, all these sync separation circuits are
contained in a V/C/D IC (TA1222N).
Fig. 9-1 shows a block diagram of the sync separation circuit.

Sync H sync siganl

input
Q501
Composite H. V SYNC
video 17 SEPARATION
signal CIRCUIT

V SYNC WAVEFORM
V sync signal
SEPARATION SHAPEING
(Reset pulse)
CIRCUIT CIRCUIT

Fig. 9-1 Sync separation circuit block diagram

1-1. Theory of Operation

1-1-1. Auto slicer type synchronous separation circuit
When a synchronizing signal is separated, synchronous
separation is made from the beginning with constant voltage
in the conventional synchronous separation circuit. The auto
slider type circuit employed in this time makes synchronous
separation at a constant rate against the synchronizing signal
amplitude. (See Fig. 9-2)
In this method, even if an abnormal signal with small
amplitude is applied, stable synchronizing performance can
be obtained without separating pedestal.

Pedestal Level
D
B
B

A
Sync Separation Level A:B=C:D
b: Small Amplitude Sync. Signal
a: Corect Sync. Signal

Fig. 9-2 Synchronous separation by auto slider system

59
1-1-2. V Sync Separation Circuit
To separate a V sync signal from the composite sync signal
consisting of V and H sync signals mixed, two stages of
integration circuits are provided inside the IC. The circuit
consists of a differential circuit and a Miller integration
circuit, and has following functions.
(1) Removes H sync signal component.
(2) Maintain stable V sync performance for a tape recorded
with a copy guard.
(3) Stabilized V sync performance under special field
conditions (poor field, ghost, sync depressed, adjacent
channel best).
The V sync signal separated in this stage is processed in a
waveform shape circuit and then used as a reset pulse in the
V division circuit as stated later.
2. H AFC (Automatic Frequency Control)
CIRCUIT
A sync system which performs synchronization with each
waveform of the sync signal as performed in a sync system
in the V circuit is called a direct type sync system. However,
if the synchronization for the H oscillator is carried out with
this method, the H oscillator synchronizes with external
noises and the H synchronization will be disturbed. To
prevent this, an output of the H oscillator is compared with
a reference H sync signal to detect deviations of frequency
and phase. The H oscillator is automatically controlled with
the detected output averaged. This circuit is called an AFC
circuit.
In the N4SS chassis, a conventional AFC circuit is not
employed but a new double AFC circuit built-in the TA1222N
is used. Fig. 9-3 shows the AFC circuit and the block diagram
of the circuit.
SYNC SEPARATION PHASE DETECTION
CIRCUIT CIRCUIT
H COUNT DOWN
AFC I LOOP
Fig. 9-3 H AFC circuit block diagram
60
First, phases of a 32 fH counted-down signal and a H sync
signal contained in broadcasting signal are compared in the
AFCI loop and the loop develops an H pulse signal for the
AFCII loop. That is, when a phase deference 01 exists in
comparison of the phase of fH signal developed by counting
down the 32 fH signal and the phase of H sync signal of the
broadcasting signal, an error signal corresponding to the
phase different is detected and a correction voltage ???1
corresponding to the error output is generated. With this
correction voltage, the 32 fH oscillator circuit is controlled.
The correction (control) voltage for the oscillator varies in
direction of positive or negative corresponding to phase lead
or lag of the fH pulse (developed by counting down) from the
H sync signal. As the H oscillator (32 x fH), a voltage
controlled oscillator (VCO), oscillation frequency and phase
of which can be controlled with the control voltage is used.
Next, an H pulse signal is created from the fH signal counted
down, and the pulse is used instead of the H sync signal in the
AFCII circuit. The AFCII circuit differs in the loop of the
count down circuit and H output circuit.
The AFCII circuit compares phase of a H BLK pulse created
by waveform shaping a AFC pulse from the FBT and a phase
of the H pulse, and detects an error component corresponding
to the phase difference 02 (if exist) and develops a
correction voltage V2 corresponding to the error, thereby
controlling the phase of Q501 H out.
The H output control voltage varies in a positive or negative
direction corresponding to the phase lead or lag of the H BLK
pulse from that of the H pulse. The phase of H out is varied
with the control voltage to make synchronization with the H
pulse phase.
The purpose of the double AFC circuit employed this time is
to improve horizontal jitter under signal reception in a poor
electrical field. The jitter in the poor field strength and
32 x fH
VCO
AFC II LOOP
H DRIVE
PHASE DETECTION
H OUTPUT
(DIVIDING) CIRCUIT
CIRCUIT
FBT PULSE
(AFC PULSE)
distortion due to phase difference are incompatible. That
is,to improve the jitter under poor field strength, response
speed must be slowed by lowering the AFC sensitivity. On
the other hand, to improve distortion due to the phase
difference, the response must be increased by increasing the
AFC sensitivity.
H Vcc
In a conventional AFC circuit, setting of the sensitivity is
carried out at one part only, so an compromise point for both
characteristics must be found. However, with the double
AFC circuit employed this time, for the jitter the AFCI loop
works best with decreasing the sensitivity and for the phase
distortion the AFCII loop works with increasing the 2VP-P
SYNC
sensitivity. IN
17 20 21

3. H OSCILLATOR CIRCUIT SYNC H AFC I 32 x fH

SEPARATION CIRCUIT VCO
CIRCUIT
3-1. Outline
A 503 kHz (32 x fH) voltage controlled type oscillator with
a ceramic oscillation element is used to generate a clock H COUNT
DOWN
pulse and the clock is counted down, thereby obviating the
need of adjustments for both the H and V deflection process
circuit. H AFC II
CIRCUIT
3-2. Theory of Operation
TA1222N
(1) The H sync signal used as a reference signal enters from
the sync separation circuit to the AFCI circuit. At the
same time, the fH pulse created by counting down the
32 x fH pulse generated in the ceramic oscillator enters Fig. 9-4
the H AFCI circuit. Phase difference between these two
signals enters an integration circuit (low pas filter)
connected to pin 4 and converted into a DC voltage
(AFC voltage).

61
(2) The AFC voltage controls frequency (32 x fH) of the
oscillator (VCO).
Fig. 9-5 shows the control characteristics of the VCO.
(3) The H output is obtained by dividing the 32 x fH (503 High
kHz) of the oscillator with flip-flops. Fig. 9-6 shows the
block diagram of this count down circuit.
(4) The V output is created by dividing the 32 x fH
oscillator output into 1/8, and then by counting the 4 x
fH pulse with a vertical counter which is reset with a V
reset pulse (V sync output signal stated under sync Low
separation).
(5) That is, the V output is not created by simply counting
down the H by performing V synchronization with a V
Low High
reset pulse entering within a window provided for V AFC voltage (V)
synchronization --- called direct type sync system, thus,
the circuit can work for non standard signals.
Fig. 9-5

32fH 4fH fH
32 x fH VCO X 1/8 X 1/4 H OUTPUT

V sync Reset
signal V WAVEFORM pulse V
SHAPE V OUTPUT
COUNTER
CIRCUIT

Fig. 9-6 Block diagram of H, V count down circuits

62
 SECTION X
VERTICAL OUTPUT CIRCUIT

63
1. OUTLINE

As can be seen from the block diagram, the sync circuit and
the V trigger circuit are contained in Q501 (TA1222N), and
the sawtooth generation circuit and amplifier (V drive circuit)
contained in Q302 (TA8859AP). The output circuit and
pump-up circuit circuits are included in Q301 (TA8427K).
D309
C322 +9V

R309 C308

+27V D301
15 3 C313
R329 6
7
R303
3
4 Q301
Q501 14 Q302 6 L301 R336
C321 2
31 C307
1 5
R320 R307 L462
R301
13 8 R306
Q312 Q311
C314
C306
R313
R330
R344
C305 +27V
C319 R304 R305

Fig. 10-1 Block diagram of V deflection circuit

1-1. Theory of Operation
The purpose of the V output circuit is to provide a sawtooth
wave signal with good linearity in V period to the deflection
yoke.
When a switch S is opened, an electric charge charged up to a
reference voltage VP discharges in an constant current rate, and
a reference sawtooth voltage generates at point a. This voltage
is applied to (+) input (non-inverted input) of an differential
amplifier, A. As the amplification factor of A is sufficiently
high, a deflection current flows so that the voltage V2 at point
C becomes equal to the voltage at point a.

Vp S: Switch
Differential
amplifier
L
a
C2
c
R1 C2 R2 V2
V1
R3

Fig. 10-2

64
2. V OUTPUT CIRCUIT

2-1. Actual Circuit

D309
C322 +9V

R309 C308

+27V D301
15 3 C313
R329 6
7
R303
3
4 Q301
Q501 14 Q302 6 L301 R336
C321 2
31 C307
1 5
R320 R307 L462
R301
13 8 R306
Q312 Q311
C314
C306
R313
R330
R344
C305 +27V
C319 R304 R305

Fig. 10- 3

2-2. Sawtooth Waveform Generation

2-2-1. Circuit Operation
The sawtooth waveform generation circuit consists of as
shown in Fig. 10-4. When a trigger pulse enters pin 13, it is
differentiated in the waveform shape circuit and only the
falling part is detected by the trigger detection circuit, to the
waveform generation circuit is not susceptible to variations
of input pulse width.
The pulse generation circuit also works to fix the V ramp
voltage at a reference voltage when the trigger pulse enters,
so it can prevent the sawtooth wave start voltage from
variations by horizontal components, thus improving
interlacing characteristics.

WAVEFORM TRIGGER PULSE

13 V. LAMP AGC
5Vp SHAPE DET. GAIN

DC=0V
14 15 16

R329 C321 C322 C323

Fig. 10-4

65
2-3. V Output

2-3-1. Circuit Operation
The V output circuit consists of a V driver circuit Q302,
Pump-up circuit and output circuit Q301, and external circuit
components.
(1) Q2 amplifies its input fed from pin 4 of Q301, Q3, Q4
output stage connected in a SEPP amplifies the current
and supplies a sawtooth waveform current to a deflection
yoke. Q3 turns on for first half of the scanning period
and allows a positive current to flow into the deflection
yoke (Q3 1DY C306 R305 GND), and Q4
turns on for last half of the scanning period and allows
a negative current to flow into the deflection yoke
(R305 C306 DY Q4). These operations are
shown in Fig. 10-5.

+27V
D301 C308 50V
D308 V3
27V
Q301
6 3
GND
D309 R309 V7
Q3
7 27V

GND
BIAS V2
CIRCUIT
Q2 2 50V

4 Q4 DY

C306 GND

R305 Q3 ON

GND
1
Q4 ON

Fig. 10-5 V output circuit

(2) In Fig. 10-6 (a), the power Vcc is expressed as a fixed
level, and the positive and negative current flowing into
the deflection yoke is a current (d) = current (b) + (c) in
Fig. 10-6, and the emitter voltage of Q3 and Q4 is
expressed as (e).
(3) Q3 collector loss is i1 x Vce1 and the value is equal to
multiplication of Fig. 10-6 (b) and slanted section of
Fig. 10-6 (e), and Q4 collector loss is equal to
multiplication of Fig. 10-6 (c) and dotted section of Fig.
10-6 (e). Power Vcc

GND (b) Q3 Collector current i1

Q3
GND (c) Q4 Collector current i2
i1 Vce 1

Q4
GND (d) Deflection yoke current i1+i2
Q2
i2
Vp
Vcc (e)
1/2 Vcc
GND
(a) Basic circuit
Fig. 10-6 Output stage operation waveform
66
(4) To decrease the collector loss of Q3, the power supply (6) Since pin 7 of a transistor switch inside Q301 is connected
voltage is decreased during scanning period as shown to the ground for the scanning period, the power supply
in Fig. 10-7, and VCE1 decreases and the collector loss (pin 3) of the output stage shows a voltage of (VCC-
of Q3 also decreases. VF), and C308 is charged up to a voltage of (VCC-VF-
-VR) for this period.
Q3 Collector loss decreases (7) First half of flyback period
by amount of this area Current flows into L462 D1 C308 D308 VCC
(+27V) GND R305 C306 L462 in this order,
Power supply
for flyback period (Vp) and the voltage across these is:
Power supply VP=VCC+VF+(VCC-VF-VR)+VF about 50V is
for scanning period applied to pin 3. In this case, D301 is cut off.
(Vcc)
(8) Last half of flyback period
Current flows into VCC switch D309 C308
Scanning period
Q301 (pin 3) Q3 L462 C306 R305 in this order,
and a voltage of
VP=VCC-VCE (sat)-VF+(VCC-VF-VR)-VCE (sat),
about 40V is applied to pin 3.
Flyback period
(9) In this way, a power supply voltage of about 27V is
Fig. 10-7 Output stage power supply voltage applied to the output stage for the scanning period and
about 50V for flyback period.

(5) In this way, the circuit which switches power supply

circuit during scanning period and flyback period is
called a pump-up circuit. The purpose of the pump-up
circuit is to return the deflection yoke current rapidly
for a short period (within the flyback period) by applying
a high voltage for the flyback period. The basic operation
is shown in Fig. 10-8.

D301 C308 D301 C308

D308
Q301 Q301
6 3 6 3
D309 R309 D309 R309

Switch Switch VR

Q3 7 Q3 7

D1 D1
First half

L462 L462
2 2
Q4 Q4
C306 C306

R305 R305

Last half

(a) Scanning period (b) Flyback period

Fig. 10-8

67
2-4. V Linearity Characteristic Correction

2-4-1. S-character Correction

(Up-and Down-ward Extension Correction)
A parabola component developed across C306 is integrated
by R306 and C305, and the voltage is applied to pin 6 of
Q302 to perform S-character correction.

2-4-2. Up-and Down-ward Linearity Balance

A voltage developed at pin 2 of Q301 is divided with
resistors R307 and R303, and the voltage is applied to pin 6
of Q301 to improve the linearity balance characteristic.
Moreover, the S-character correction, up- and down-ward
balance correction, and M-character correction are also
performed through the bus control.

68
 SECTION XI
HORIZONTAL DEFLECTION CIRCUIT

69
1. OUTLINE

The H deflection circuit works to deflect a beam from left to

right by flowing a sawtooth waveform of 15.734 kHz into the
DY H deflection coil.

2. HORIZONTAL DRIVE CIRCUIT

The H drive circuit works to start the H output circuit by

applying HVCC (Q501 DEF power source) to pin 22 of
Q501 (TA1222N) and a bias to the H drive transistor Q402
at the main power on.

2-1. Theory of Operation

(1) When the power switch is on, the main power supply of
125V starts to rise. At the same time, AF power supply
25V also rises.
(2) With 25V line risen, Q430 base voltage which is created
by dividing the audio power with R433 and D430 also
rises. Then, the transistor Q430 turns on and the HVCC
is applied from the audio power line through R432 and
D431 to pin 22 of Q501.

R432 Q430 D431

Q501

R433
D430 BB81

81 81 22 H Vcc
BB80 L400

SIGNAL C431 C430 D490

Fig. 11-1 H drive circuit block diagram

70
3. BASIC OPERATION OF HORIZONTAL
DRIVE
turn off the transistor, a sufficiently high, reverse voltage
A sufficient current must flow into base of the horizontal
must be applied to the base.
output transistor to rapidly make it into a saturated (ON)
(3) When the transistor is on (collector current is maximum)
condition or a cut off (OFF) condition. For this purpose, a
condition with the sufficiently high forward voltage
drive amplifier is provided between the oscillator circuit and
applied to the base, the transistor can not be turned off
the output circuit to amplify and to waveshape the pulse
immediately, if a reverse base bias is applied to the base
voltage.
because minority carriers storaged in the base can not
be reduced to zero instantly. That is, a reverse current
3-1. Theory of Operation
flows through an external circuit and gradually reduces
(1) The horizontal drive circuit works as a so called switching
to zero. The time lag required for the base current to
circuit which applies a pulse voltage to the output
disappear is called a storage time and falling time.
transistor base and makes the transistor on when the
(4) To shorten the storage time and the falling time, a
voltage swings in forward direction and off in reverse
sufficiently high reverse bias voltage must be applied to
direction.
allow a heavy reverse current to flow. This operation
(2) To turn on the output transistor completely and to make
also stabilizes operation of the horizontal output
the internal impedance low, a sufficiently high, forward
transistor.
drive voltage must be applied to the base and heavy base
current ib must be flown. On the contrary, to completely

On period OFF period

0 t Input waveform (b)

+
Forward
ib current
0 t Base current (c)
Reverse
current
V -
Falling
(a) time

Storage
time

Fig. 11-2

71
3-2. Drive System 3-2-2. OFF drive system
3-2-1. ON drive system When the drive transistor is on, the horizontal output transistor
When the drive transistor is on, the horizontal output transistor is off.
also turns on.
Merit:
Merit: • Energy balance between on and off periods of the drive
• The base current can be precisely controlled without circuit is better, and the circuit can be simplified.
being affected by variation of pulse width which is • Reverse base current of the horizontal output transistor
caused by the horizontal oscillator circuit and the drive can be controlled easily.
circuit.
Demerit:
Demerit: • Base-emitter forward current flowing into the horizontal
• It is difficult to flow a reverse bias current to the horizontal output transistor is susceptible to on-period variation of
output transistor to eliminate its storage carrier for transient the drive transistor.
period of on to off period for the horizontal output
transistor.

H output H output

H driver H driver

H OSC H OSC

ON +B ON ON +B ON
(OFF) (OFF) (OFF) (OFF)

Fig. 11-3 Fig. 11-4

72
3-3. Circuit Description

In the N5SS chassis, the off drive system is employed.

(1) When Q1 inside Q501 is turned on, Q402 base is
forward biased through 9 V pin 22 of Q501 (H.
VCC) pin 23 of Q501 (H. Out) R411/R410 resistor
divider, and then, Q402 collector current flows through
125V R416 T401. In this case, the H output
transistor Q404 turns on with the base-emitter reverse
biased because of the off drive system employed.
(2) On the contrary, when Q1 inside IC501 is off (pin 8 is
0V), base-emitter bias of Q402 becomes 0V and Q402
turns off, and a collector pulse as shown in Fig. 11-5
develops at the collector.
The voltage is stepped down and Q404 is forward
biased with this voltage, thus turning on Q404.
(3) In this way, by stepping down the voltage developed at
primary winding of the drive transformer and by
applying it to Q404, a sufficient base current flows into
Q404 base, thereby switching the Q404.

Q501

H. Vcc
22 T401
H drive
transistor

D490 C431 C417 1 3

R415
Q1 Q404
R411
23 H output
2 4 transistor
R410
C43

Q402
H drive
transistor + V1
R416 V2

0V
C416

9V +125V

VCP
0V

Q402 Q402
OFF ON

Fig. 11-5

73
4. HORIZONTAL OUTPUT CIRCUIT

The horizontal output circuit applies a 15.734 kHz sawtooth

wave current to the deflection coil with mutual action of the
horizontal output transistor and the damper diode, and deflects
the electron beam from left to right in horizontal direction.

10 HV

5
2 T461
FBT
S-charactor
3 capacitor

Q404 L462
H output 1 8 Deflection yoke
(With damper diode) (H coil)
IC501 T401
H drive C440
transformer
R415
H. out C444
TP-33
Q402 D461 C442 R441
H drive
BB31
C463
Q1 23 33
R411 C417 C423 L442
C467
R410
L441
L461
C413

+
C416 C464 H
R416
Resonat + M-charactor linearity
capacitor correction coil
To DPC output

SIGNAL DEF/POWER PCB

125V
Diode modulator circuit

Fig. 11-6

74
4-1. Theory of Operation
Description of the basic circuit
4-1-1. Operation of Basic Circuit
1. t1~t2:
(1) To perform the horizontal scanning, a 15.734 kHz
A positive pulse is applied to base of the output transistor
sawtooth wave current must be flown into the horizontal
from the drive circuit, and a forward base current is flowing.
deflection coil. Theoretically speaking, this operation
The output transistor is turned on in sufficient saturation
can be made with the circuit shown in Fig. 11-7 a and
area. As a result, the collector voltage is almost equal to the
b.
ground voltage and the deflection current increases from
(2) As the switching operation of the circuit can be replaced
zero to a value in proportionally. (The current reaches
with switching operation of a transistor and a diode, the
maximum at t2, and a right half of picture is scanned up to
basic circuit of the horizontal output can be expressed
this period.)
by the circuit shown in Fig. 11-7 a. That is, the transistor
can be turned on or off by applying a pulse across the
2. t2:
base emitter. A forward switching current flows for on-
The base drive voltage rapidly changes to negative at t2 and
period, and a reverse switching current flows through
the base current becomes zero. The output transistor turns
the diode for off-period. This switching is automatically
off, collector current reduces to zero, and the deflection
carried out. The diode used for this purpose is called a
current stops to increase.
damper diode.
3. t2~t3:
The drive voltage turns off at t2, but the deflection current
can not reduce to zero immediately because of inherent
nature of the coil and continues to flow, gradually decreasing
by charging the resonant capacitor C0. At the same time, the
capacitor voltage or the collector voltage is gradually
increases, and reaches maximum voltage when the deflection
a H output basic circuit current reaches zero at t3. Under this condition, all electro-
magnetic energy in the deflection coil at t2 is transferred to
H output the resonant capacitor in a form of electrostatic energy.
transistor
D Co L

Deflection
4. t3~t4:
Damper Resonant yoke Since the charged energy in the resonant capacitor discharges
diode capacitor through the deflection coil, the deflection current increases
in reverse direction, and voltage at the capacitor gradually
Vcc reduces. That is, the electrostatic energy in the resonant
capacitor is converted into a electromagnetic energy in this
b H output equivalent circuit process.

5. t4:
SW1 SW2 Co L When the discharge is completed, the voltage reduces to
zero, and the deflection current reaches maximum value in
reverse direction. The t2~t4 is the horizontal flyback period,
and the electron beam is returned from right end to the left
end on the screen by the deflection current stated above. The
Vcc operation for this period is equivalent to a half cycle of the
resonant phenomenon with L and C0, and the flyback period
is determined by L and C0.
Fig. 11-7

75
6. t4~t6: t1 t2 t3 t4 t5 t6
For this period. C0 is charged with the deflection current
A TR 0
having opposite polarity to that of the deflection current base voltage
stated in "3.", and when the resonant capacitor voltage
exceeds VCC, the damper diode D conducts. The deflection
current decreases along to an exponential function B TR 0
(approximately linear) curve and reaches zero at t6. Here, base current
operation returns to the state described under "1.", and the
C TR
one period of the horizontal scanning completes. For this collector
current 0
period a left half of the screen is scanned.
In this way, in the horizontal deflection scanning, a current D D 0
flowing through the damper diode scans the left half of the damper
current (SW2)
screen; the current developed by the horizontal output
transistor scans the right half of the screen; and for the E Switch
flyback period, both the damper diode and the output transistor current 0
(TR, SW1)
are cut off and the oscillation current of the circuit is used.
Using the oscillation current improves efficiency of the F Resonant
circuit. That is, about a half of deflection current (one fourth capacitor
current (Co) 0
in terms of power) is sufficient for the horizontal output
transistor.

G Deflection
current (Lo) 0

H TR
collector
voltage 0

Fig. 11-8

76
4-1-2. Linearity Correction (LIN)
(1) S-curve Correction (S Capacitor)
t2 t1 t2 t1
Pictures are expanded at left and right ends of the screen even
if a sawtooth current with good linearity flows in the deflection q2 q1 t2 = t1 q2 q1 t2 > t1
coil when deflection angle of a picture tube increases. This q 2 < q1 q2 = q 1
is because projected image sizes on the screen are different
at screen center area and the circumference area as shown in
Fig. 11-9. To suppress this expansion at the screen
circumference, it is necessary to set the deflection angle @
to a large value (rapidly deflecting the electron beam) at the
screen center area, and to set the deflection angle @ to a small
value (scanning the electron beam slowly) at the (a) S-character correction (b)
circumference area as shown in Fig. 11-9.
In the horizontal output circuit shown in Fig. 11-10, capacitor
CS connected in series with the deflection coil LH is to block
Fig. 11-9
DC current. By properly selecting the value of CS and by
generating a parabolic voltage developed by integrating the
deflection coild current across the S capacitor, and by varying Cs
the deflection yoke voltage with the voltage, the scanning
speed is decreased at beginning and end of the scanning, and
TR
increased at center area of the screen. The S curve correction D Co
LH
is carried out in this way, thereby obtaining pictures with
good linearity.
Deflection coil

Vcc

(a) H output circuit

(b) Sawtooth wave current

(c) Voltage across LH

Fast deflection

Slow deflection

(d) Synthesized current

Fig. 11-10

77
 total are obtained.

(2) Left-right Asymmetrical Correction (LIN coil)

4-1-3. Horizontal Linearity, M-character Correction
In the circuit shown in Fig. 11-11 a, the deflection coil
Circuit
current iH does not flow straight as shown by a dotted line in
Since deflection angle increases with size of picture tube
the figure b if the linearity coil does not exist, by flows as
increases, a M character trend which compresses a picture
shown by the solid line because of effect of the diode for a
image at beginning and end of the scanning will occur. A M
first scanning (screen left side) and effect of resistance of the
character linearity correction circuit is provided in the N5SS
deflection coil for later half period of scanning (screen right
as shown in Fig. 11-12. The M character linearity correction
side). That is, the deflection current becomes a sawtooth
is carried out by connecting a series resonant circuit in
current with bad linearity, resulting in reproducing of
parallel with the S capacitor and flowing a resonant current
asymmetrical pictures at left and right sides of the screen (left
side expanded, right side compressed).
When a horizontal linearity oil L1 with a current characteristic
as shown in figure c is used, left side picture will be
compressed and right side picture will be expanded because
the inductance is high at the left side on the screen and low
at the right side. The left-right asymmetrical correction is
carried out in this way, and pictures with good linearity in

(a)

FBT
TR LH LH
D Co Deflection
coil TR
D Co
LI

iH Li Vcc L
Cs Cs
S-character C
capacitor
(b) Deflection coil current

Deflection coil current

(iH)

Resistance of LH
(b) Sawtooth wave current
0 Characteristic of D
(Left) (Right)

(c) Linearity coil characteristic

Linearity coil characteristic

Inductance
(mH)
Fast Slow Fast Slow Fast

(c) Synthesized current

(Left) (Right)
Current (A)
Fig. 11-12
Fig. 11-11 Linearity coil

78
which has two times the H oscillator frequency.

5. HIGH VOLTAGE GENERATION

CIRCUIT

The high voltage generation circuit develops an anode voltage

for the picture tube, focus, screen, CRT heater, video output
(210V) and so on by stepping up the pulse voltage developed
for flyback period of the horizontal output circuit with the
FBT, and supplies the power to various circuit.

AFC CRT
10
blanking anode

Heater 9
C303
4
Auxiliary +27V
winding
D302 7
C310
R327
6
C460 Focus
D460 R469
-27.5V 5
D406
+210V 3

C446
Primary +125V 2
winding
C448
1
D404 ABL
Screen
T401

C463 H deflection coil

L462

L441 R441
1000VP-P
0
C442
1H
(15.75KHz)

Fig. 11-13

79
5-1. Theory of Operation

5-1-1. +210V
For the flyback period, pulses are stacked up to DC +125V
with FBT, and the voltage is rectified by D406 and filtered +115V
by C446.

5-1-2. +27V 0
Pin 4 of the FBT is grounded and the shaded area of negative
pulse developed for opposite period of the flyback period is
Fig. 11-14
rectified, thus developing better regulation power supply.

5-1-3. -27V
As a power for the DPC circuit, a negative pulse signal is 10 0
rectified by D460 and filtered with C460, thus developing
4
the -27V.
7 0
5-1-4. High voltage
Singular rectification system which uses a harmonics non- For +27V
8
resonant type FBT is employed and a better high voltage
regulation is obtained, so amplitude variation of pictures 2
0
becomes low.
1

Fig. 11-15

F G
Pulse
E

Picture
tube anode E
F
Primary Picture
tube capacitor
D EH
D Stacked
C C pulse of
4 block
EO
B B
Auxiliary A
A

1H
ABL 15.735KHz

Fig. 11-16

80
5-2. Operation Theory of the Harmonic Non-Resonant System and Tuned Waveforms

The high voltage coil is of film multi-layer winding type and

the coils are isolated into seven blocks. Each block is
connected through a diode.
The basic operation is described in the case of 4 blocks
construction for simplification. Positive or negative pulse
determined by stray capacitance of each coil develops at
terminal points ( , , , , , G F , G ) of each coil

as shown in Fig. 11-16, and these pulses are stacked as

shown, thus developing the high voltage.
Moreover, a capacitance between the internal and external
coatings of the picture tube works as a smoothing capacitor.
Focus voltage is obtained at point EO.
The FBT is turned to a harmonic of 15 times the fundamental

Flyback
pulse 11ms
Reference 1 1
= = 45KHz
wave 22ms 22x10
20ms
45 KHz

Becomes 45 KHz x 15 = 675KHz

Harmonics this is determined by coil inductance capacitance and
63.5ms 15 times stray of FBT.
AC
675 KHz
0

AC
0 Tuned
waveform
(In case of 3X) (In case of 15X)
Hight
voltage E E

Focus Picture tube current

current

In case of 15 times the harmonics as compared with

3 times the harmonics, average conduction peiod of
the high voltage diode is wider.
As a result, high voltage variations are suppressed.
AC
0

Fig. 11-17 Tuned waveforms

81
frequency, and the turned waveform is shown in Fig. 11-17.

6. X-RAY PROTECTION CIRCUIT

1. Outline
In case picture tube using high voltage, when high voltage
rises abnormally due to components failure and circuit
malfunction, there is possible danger that X-RAY leakage
increases to affect human body. To prevent it, X-RAY
protection circuit is equipped.

2. Operation
Figure 10-18 shows the circuit diagram. Supposing high
voltage rises abnormally due to some reason, pulse at pin 9
of T461 also rises, and detection voltage Eb rectified by
D471 and C471 in X-RAY protection circuit rises. When Eb
rises, emitter voltage of Tr10 divided by R25 and R26 in
protector module becomes higher than [zener voltage (6.2V)
of ZD6 + Tr10 VBE ]. This causes Tr10 turns on to supply
base current to Tr9. Then Tr9 turns on. By this Tr6 and Tr6
turn on to make ON/OFF pulse at pin 7of QA01 in low level,
QB30 and Q843 turns off, then relay SR81 turns off. Tr6 and
Tr7 are in thyristor-connection, and 5V of power holds
protection operation until main power switch is turned off.
During circuit operation, power LED near main power
switch blinks in red. Caution : To restart TV set, repair failure

5V
15
12V
MICOM
R9
QA01#7
R10
R25 R472 T461
Tr10 ED
Tr7 Tr9 13 9
RB30 D471
R21 R26
RELAY R20
Tr6
SR81 R22 C471
D3
R12 ZD6
16 Tr5 C1
Q843 QB30

R11

12
+ C474

Figure 11-18 X-RAY protection circuit

82
first.

7. OVER CURRENT PROTECTION

CIRCUIT

1. Outline
If main power (125V) current increases abnormally due to
components failure, there is possible danger of the secondary
damage like failure getting involved in other part failure, and
abnormal heating. To prevent this, over current protection
circuit is equipped, which detects current of main B line to
turn off power relay in abnormal situation.

2. Operation
Fig. 11-19 shows over current protection circuit. When the
current of main B line increases abnormally due to the
shortage in load of main B line, voltage drop arises across
R470. By this voltage drop, when base-emitter voltage of Tr
8 in protector module (Z801) becomes appprox. 0.7V or
more, Tr 8 turns on, and the voltage by divided ratio of R15
and R16 is applied to cathode of ZD4. When this voltage
becomes higher than zener voltage of ZD4, ZD4 turns on to
supply base current to base of Tr 6 via R14. This causes Tr
5 ON and voltage at pin 16 of Z801 becomes Low. Therefore,
QB30 and Q843 turns off to set SR81 OFF. Tr 6 and Tr 7 in
Z801 are in thyristor- connection, and power 5V-1 supplied
at pin 15 keeps protection operation for standby power until
main power switch is turned off. During circuit operation,
power LED near main power switch blinks in red. Caution :

R470 F470
MAIN B To T461

R479 R472
5V
C472
15 2 1

MICON
R9
QA01#7

ZD4
R830 R16
R10
Tr7
RELAY Tr8
SR81
R14 R15

16 Tr6
Q843 Q830
R12 C1

Tr5
Z801
R11 PROTECTOR MODULE
Z801
PROTECTION MODULE
17

Fig. 11-19 Over current protection circuit

83
To restart TV set, repair failure first. the reverse operation will occur.

8. KINK CORRECTION CIRCUIT 2. Circuit Description

1. Outline
In the N5SS chassis, a kink correction circuit is employed to
correct a kink generating when receiving a black and white
pattern.
In the black and white pattern cross hatch shown in Fig. 11-
20, when the picture changes from black to white during field
scan period, a current Is flows rapidly in secondary of the
FBT and a current IP flows in reverse direction during scan
period (due to transformer coupling) in the primary winding.
This current works to increase the voltage across S character
correction capacitor CS. As a result, the deflection current
decreases by I1 as shown in Fig. 11-21 and the raster moves
toward left, thus causing the kink as shown in Fig. 11-22. On
the contrary, when the picture changes from black to white,
To correct the kink damping circuit is added between the
main B power line and the S character capacitor as shown in
Fig. 11-23.
In Fig. 11-24, a capacitor C441 is charged with a DC current
iB through Q442 connected to MAIN B during the flyback
period. When the voltage across C441 and S character
correction capacitor increases during the scan period, the
diode D442 conducts and reduces the voltage across C442 to
the original voltage level, thereby suppressing shift of the
raster.
Kink Correction
Circuit T461

Q404
C444 C440 L642 D442 R442

C442 C441

+
Cs lp ls L461
- D461 SIDE DPC C448
C467 C464
FBT

Fig. 11-20
Fig. 11-23

T461

L462
D442
l1
Vcs
R442
C442
C441 C448
Vcs MAIN
Fig. 11-21 iB B

Fig. 11-24
Kink in the cross bar
pattern

Fig. 11-22

84
 SECTION XII
DEFLECTION DISTORTION
CORRECTION CIRCUIT
(Side DPC Circuit)

85
1. DEFLECTION DISTORTION
CORRECTION IC (TA8859P)
(3) V S-character correction
1-1. Outline
(4) V picture position (neutral voltage setting)
The deflection distortion correction IC (TA8859AP), in
(5) V M-character correction
combination with a V/C/D IC (TA8859AP) which has a V
(6) V EHT correction
pulse output, performs correction for various deflection
(7) H amplitude
distortions and V output through the I2C bus control. All the
(8) L and R pin-cushion distortion correction I (entire area)
I2C bus controls are carried out by a microcomputer and can
(9) L and R pin-cushion distortion correction II (corner
be controlled with the remote control.
portions at top and bottom)
(10) H trapezoid distortion correction
1-2. Functions and Features
(11) H EHT correction
The IC has functions of V RAMP voltage generation, V
(12) V AGC time constant switching
amplitude automatic switching (50/60 Hz), V linearity
correction, V amplification, EHT correction, side pincushion
1-3. Block Diagram
correction, I2C bus interface, etc. and controls following
Fig. 12-1 shows a block diagram of the basic circuit.
items through the I2C bus lines.
(1) V amplitude
(2) V linearity

+12V

14 15 16 5 3

Waveform Trigger Puise V. AGC Time

V. Trigger-in 13 V. Rame AGC
Shape Det Gen. Constant SW

Control Through
H. Trapezoid Distortion Bus
Correction
V. M-Character V. Linearity V. S-Character
Correction Correction Correction
L-R Pincushion
Distortion Correction I
(Bus Control Signal)
SDA SCL
L-R Pincushion
Distortion Correction II
V. Amplitude
10 (Top & Bottom Comer Section)
Adj.

9 Logic
V. Screen V. EHT H.EHT H.EHT
12 Position Correction Input Corrction

H. Amplitude 2 EW-Drive
Adj.

8 6 1 4
V Drive V. Feedback EHT INPUT EW Feedback

Fig. 12-1

86
2. SIDE DPC

2-1. Outline and the output circuit.

Since the deflection coil used in 29 and 34" type of N5SS
chassis is not a DPC free type left and right pin-cushion
distortion must be corrected with a circuit.
If the distortion is not corrected, pin-cushion distortion as
shown in Fig. 12-2 (a) will occur.
To correct this distortion, a H deflection current must be
modulated in a form of parabola for V sync period.
The compensation circuit using a diode modulator system
which has a large amount of compensation ability is used in
N4SS chassis.
The correction circuit in N5SS chassis is of a negative type
and the diode modulator develops a negative voltage.
Accordingly, a negative power supply is used in the amplifier
The circuit can be controlled through the I2C bus. That is, the
parabola waveform and DC voltage obtained by controlling
E/W output (pin 2) of Q302 (TA8859P) through the bus is
shifted in their levels by zener diodes (D464, D465, D466)
to use them as a negative power source. The voltage is added
to the amplifier and the output circuit (Q462, Q460) and
modulates the voltage at CD11 in the diode modulator
circuit. Thus developed parabola voltage is a negative voltage
and the sum with the main B voltage (VB) is applied across
the S character capacitor. This voltage works as a power
supply for the H deflection yoke and the H deflection current
is modulated as shown in Fig. 12-2 (b), thus correcting the
left and right pin-cushion distortion.

V. Sync
H. Sync

(a) Left and right pin-cushion distortion (b) H deflection current

Fig. 12-2

9V AMP output circuit Diode mdulator circuit

Q501 Q302
V/C/DIC E/W IC H. out
R465 FBT
TA1222N TA8859P
H. DY
-B
PARABORA R341
3 13 VOLTAGE S character
GEN. R343 capacitor
D464 D466
Q462 L461
Bus 9 WAVEFORM
control D465
10 PROCESS C464
(From +VB
microcomputer) 4
Q460
2 Q461

Fig. 12-3 Diode modulator type side DPC circuit

87
3. DIODE MODULATOR CIRCUIT
high voltage of FBT also develops a constant voltage.
Fig. 12-4 shows a basic circuit of the diode modulator used
When the negative pulse developed at the point B is integrated
in the N5SS.
with Lm and Csm, its average value appears at Csm as a
A key point in the N5SS chassis shown in Fig. 12-4 is to
negative voltage.
develop a negative pulse at point B.
By modulating this voltage to have the parabolic curve with
In this circuit, a current loop of the resonant circuit for
Q460, a waveform of Vm is obtained as shown in Fig. 12-6.
flyback period is shown by an arrow, and the energy stored
As a result, the voltage Vs which is the sum of the power
in LDY is transferred to resonant capacitors Cr, Crm in
supply voltage VB and the Vm is applied across the S-curve
passing through Cr, Crm, Cs when the scanning completes.
capacitor Cs. The Vs becomes as a power source for the
As a result, a positive, horizontal pulse as shown in Fig. 12-
deflection yoke, and the waveform modulated in the parabolic
5 (a) will appear at Cr, and the current flows into Crm with
form, as shown in Fig. 12-2 (b), is applied to the horizontal
the direction as shown. Then a pulse as shown in Fig. 12-5 (b)
deflection yoke and corrects the left-right pin-cushion
develops at the point B.
distortion.
On the other hand, since constant amplitude pulses across Cr,
as shown in Fig. 12-5, are applied to the primary winding, the

A
FBT

LDY
DD Cr
H
OUT VB
Cs Vs

a) Waveform at point A
B Lm
DM Q460 Vm
Crm Csm
b) Waveform at point B

Fig. 12-4 Fig. 12-5

VB

VS

0
Vm

Fig. 12-6

88
4. ACTUAL CIRCUIT

In the actual circuit, the resonant capacitor is split into two as IP1 IP2 FBT

shown in Fig. 12-7. One, C440, is inserted between the C1

collector of the H. OUT transistor and ground and another IH
H. LDY IP
C444 inserted between the collector and emitter. In Fig. 16- OUT
7, C440 is expressed as C1 and C444 as C2, and the resonant IY1
IY CS
current path for the flyback period is shown by arrows. VS

In a conventional circuit, when brightness of a picture tube C2

varies, high voltage current varies and the high voltage also VB

varies. As a result, horizontal amplitude also varies. Lm

However, in this circuit, the horizontal amplitude variation C3
IP2 Vm
can be suppressed to near zero if the high voltage current IY1 Csm
varies with variation of the high voltage.
When the scanning period completes, the energy stored in
the deflection yoke LDY is transferred to the resonant
capacitor in a form of current Iy. In this case, the current is
split into two; Iy1 passing through C1, C3 and Iy2 passing
through C2. In the same way, the energy stored in the Fig. 12-7
primary winding of the FBT is transferred to the resonant
capacitor in the form of Ip. In this case, the current (path) is
also split into two; Ip1 passing through C1 and Ip2 passing
through C2, C3. Concequently, the current differences
between Iy1 and Ip2 (Iy1-Ip2) passes through C3.
When the high voltage current IH reduces with a dark
picture, the current Ip in the primary circuit decreases, so Ip1
VB
and Ip2 also decrease. However, a current flowing into (Iy1-
Ip2) increases as Ip2 decreases. As a result, the pulse
developing at the point B increases and the voltage Vm at
Csm also increases as shown in Fig. 12-8. That is, when a VS
dark picture appears, the voltage across S-curve capacitor Cs
increases as shown in Fig. 12-8, the high voltage rises, and
the horizontal amplitude is going to decrease. But, as Vs
increases, the deflection yoke current increases and this 0
Vm
works to increase the horizontal amplitude. Accordingly, if
the brightness of picture changes, the horizontal amplitude is
maintained at a constant value. This is one of the fine features
the circuit has.
Fig. 12-8

89
4-1. Basic Operation and Current Path
4-1-1. Later Half Scanning Period
When the power is turned on, the power supply voltage VB
is applied to Cs and Csm, and the Cs acts as a power source
for a later half of the scanning period for which the H. OUT
transistor is turned on, and the deflection current Iy flows in
the path as shown below
4-1-2. First Half Scanning Period
When the base drive current decreases and the H. OUT
transistor is turned off, each energy stored in LDY, Lm, Lp
of FTB is transferred to C1, C2 and C3, respectively, and the
resonant current becomes zero at a center of the flyback
period. Then, VA and VB pulses show a maximum amplitude.

VA
VA
FBT FBT

LDY LDY lP

IY lP IP1 IY
H.OUT C1 C2
+ IY2
Cs IP2 Cs

VB
VB VB VB
IM LM IM LM
IDC
DM IDC
CSM
+ CSM

Fig. 12-9 Fig. 12-11

Voltage & current waveform in H period.

IY 0

IY 0

VA 0

IM 0
VA IDC
0

IM 0
IDC VB 0

VB 0 C1: IY1+IP1
C1
C2: IY2+IP2
C2 0

Fig. 12-10
C3: I P2-IY1-IM
C3 0

Fig. 12-12

90
4-1-3. Later Half of Flyback Period
All energy in the coil has been transferred to the resonant
capacitors at the center of the flyback period, and the voltage
shows the maximum value. However, during next half of the
flyback period, the energy of the resonat capacitor is
discharged as a reverse current through respective coil.
When the discharge has been completed, VA and VB becomes
zero, and the deflection current in reverse direction becomes
the maximum.
4-1-4. First Half of Scanning Period
When the flyback period completes, the damper diode DD
and the modulation diode DM turn on, and the Iy and Im
proportionally decrease from the maximum value to zero.
The H. OUT transistor is turned on just preceding at the
center of the scanning period, and repeats the steps 4-1-1
through 4-1-4 stated above.

VA VA
L.O.P.T
FBT
LDY LDY
IP2 IY
IP1 IP
C1 C2 DD IY
CS CS
IY2
IY1

VB VB VB
C3 VB
IM LM IM LM
DM
IDC IM

CSM CSM

Fig. 12-13 Fig. 12-15

Voltage & current waveform in H period.

Iy 0
IY 0

VA 0
VA
0
IM 0
IDC IM 0
IDC

VB 0
VB 0

C1: I Y1+IP1
C1
C2: I Y2+IP2
C2 0
Fig. 12-16

C3: I P2-Iy1-IM.
C3 0

Fig. 12-14
91
 SECTION XIII
CLOSED CAPTION/EDS CIRCUIT

92
1. OUTLINE

CC / EDS circuit extracts data of CC (Closed Caption) and

EDS (Extended Data Services) from input video signal,
and decode them to generate display signal. Major feature of
CC/EDS circuit of TG1-C chassis is as follow.
(1) Employing 1 chip decoder of stand alone type
(2) Acceptable of field 2 data ( CAPTION 3, 4 TEXT 1,
2 EDS) as well as field 1 data ( CAPTION 1, 2 TEXT
1, 2)
(3) Display of text mode extends from 8 rows to 15 rows.
(4) Extended character display of 64 kinds standing for
Spanish and the like.
(5) Representing Background attributes (8 colors +
transparent)

2. DATA TRANSMISSION FORMAT

CC/EDS data is transmitted being superimposed on line 21,

field 1 (21H) and field 2 (284H). Waveform of line 21
is shown in fig. 13-1. Line 21 signal is composed of data of
7 cycle clock-run-in, start bit and 16 bit (8bits x 2 bytes).

10_50±0.5ms 4.15±0.1ms 33.764ms

12_910ms
0.12ms

P P
b1 b3 b5 b7
A b1 b3 b5 A b7
10.076ms b2 b4 b6 R b2 b4 b6 R
I I
T T 20ms
Y Y

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Fig. 13-1 Line 21 waveform

93
3. DISPLAY FORMAT

Character display area of caption mode and text mode

consists of 32 characters x 15 rows as shown in fig. 13-2.
On front and back of each row, 1 character blank area is
respectively added. In caption mode, up to 8 rows among
15 rows can be displayed at the same time. Characters in text
mode are displayed in black box of 34 characters x
15 rows. EDS display format is shown in fig. 13-3. The item
can be displayed only when data of the item is transmitted.

SCREEN

LINE 43
ROW1

LINE 237 ROW15

1 CHARACTER BLANK AREA 32 CHARACTERS 1 CHARACTER BLANK AREA

Fig. 13-2 Caption / Text display area

(Green) Network Name Call Letters (Green)

(White, Slant, Unerline) Program Name
(Cyan) Prog. Length Prog. Type Time In Show (Cyan)
(Cyan)

(Yellow)

Program Description (4rows)

(Character background: black)

Fig. 13-3 EDS display format

94
4. CIRCUIT OPERATION

Block diagram of CC / EDS circuit is shown in figure 13-4,

and block diagram of QM01 is shown in figure 13-5.
Video signal which is input to pin 9 of UM01 is changed to
1 Vp-p signal which is band-limited to 600kHz by the
input circuit, and it is supplied to pin 7 of QM01. Inside
QA01, line 21 signal is extracted from input video signal,
and is recovered on clock and data. Recovered data is
decoded by command processor and converted to display
signal of R, G, B, Ys in Output Logic section. The display
signal is output at pins 18, 2, 3 and 17 in the CMOS level
of positive polarity. The display output and OSD are
switched by QR01 in UM01, and the selected signal is sent
to
V/C/D IC. When the display of CC/EDS and OSD are
superimposed, OSD is the first priority. H. sync signal with
negative CMOS level is input to pin 5 of QM01. This signal
becomes the standard signal of PLL circuit in IC.
Loop filter for PLL circuit is connected to pin 9. QM01 is
controlled by I2C bus connected to pins 14 and 15.

95
 UM01 EDS/CC/RGB SW.

QM01 CC/EDS DECODER

UV01 A/V MODULE Q501 V/C/D

Video
in HD
V-AV EH 9 ATT LPF 7 VIDEO HIN 5 INVERTER 11 30 HD OUT

VD
VIN 13 12 31 VP OUT

QA01 uCOM QR01 RGB SWITCH

Q89- I2 C BUFFER
BOX 17 2 1A

96
SCK
SCL1 37 2 SCL1 SCL2 6 13 15 SCK R 18 5 2A
SDA
SDA1 38 3 SDA1 SDA2 5 14 14 SDA G 2 3 3A
Ys OUT
B 3 14 4A 1Y 4 6 36 OSD YS
R OUT
2Y 7 1 37 OSD R
G OUT
1 A/B 3Y 0 5 38 OSD G
B OUT
4Y 12 2 39 OSD B
OSD-YS 18 3 1B
OSD-R
R 22 19 6 2B
OSD-G
G 23 20 10 3B
B 24 OSD-B
21 13 4B

Fig. 13-4 CC /EDS circuit block diagram

 +5V

12

VDD

Sllced Data Data MOD

Data Sllcer Data Recovery &
XFR BUF
DLCK
COMP Video 7
V Clamp Data CLK
Recovery

8 Display
Sllce Level SYNC Sllcer RAM
Fig. 13-5 QM01 block diagram

CSYNC

Timing Logic Command Processor

COMP SYNC
and CHAR
ROM
97

Vertical CTR Decoder Control

And Control

13
VIN
Horizontal R
Counter Output 18
G
Logic 2
DOT CLK B
3
Box

SMS

SDO
SEN

SCK

SDA
17

Phase/
Loop VCO
Freq
Filter
DET

PFD Loop 6 4 15 14 16
FIL Vss AVSS
HIN 5 9 1 11
LPF
 SECTION XIV
POWER CIRCUIT

98
1. OUTLINE

Block diagram of power circuit is shown in fig. 14-1. Power

circuit consists of stand-by power supply (power
transformer) which supplies power to microcomputer, and
main power supply which supplies power to H. OUT,
AUDIO OUT and signal process circuits. Power for V. OUT,
VIDEO OUT and the like is supplied from flyback
transformer of H. deflection circuit. Power (+12V from
converter transformer) for signal process circuit are supplied
from 9V-2, 9V-1, 5V-2 and 5V-3 lines by 3 terminal regulator
and 4 terminal regulator with switch which are equipped
in latter stage. The characteristics of this system are that
main supply newly employs current resonant type which is
smaller and more highly effective than conventional type of
RCC switching type, and employs protector module (Z801)
which includes protection circuit and error amp. for secondary
output detection in one package.

T461

+200V
+27V
+27V
R370 4132
AD BE
Q370
T840 OVER VOLTAGE
F801 T801 +12V PROTECTOR
POWER
TRANS Q840 +5V-1 MICOM
TPW PERIPHERALS (Q462) -27V
1459AZ D840

Q420 9V-1 (TUNER, IMA, E/W, VCD)

L901 R808 T862 +26V Q832 9V-2 (COMB, DSP)

CON-
F860 AUDIO OUT Q830 5V-2 (TUNER, COMB, VCD)
SR81 VERTER AND H.V
CC
R861 TRANS.
D801 Q831 (POP, RGBSW)
+12V
Q801 TPW R470 F470 +B(+125V)
VOLTAGE REGU. 3335A8 VELOCITY
OVER VOLTAGE R101 MOD.
R479
PROTECT R472
Q843 1 2 R472
SW R883 Z801 16 HEATER
PHOTO +32V (H001 PROTECTOR C471 D471
COUPLER HY01. HF01) HIC1013 14
QB30
SW TLP621 (GRL) 3 16
QA01 (25)

Fig. 14-1 Power block diagram

99
2. RECTIFYING CIRCUIT AND STANDBY
POWER SUPPLY
diode and performs rectification and smoothing together
Rectifying circuit is a circuit to generate dc from ac 120V.
with C810. R801 is a resistor to regulate inrush current
D899 is a varistor to absorb surge (ex. lightning) arose
and to suppress rush current in switch-on. T840 is standby
on ac line. When surge arises, the circuit let surge by-pass via
power transformer. D840 and C840 performs rectifying
route shown in figure 13-2 to protect the following
and smoothing to make approx. 12V for relay driving, and
circuit. C801 and T801 are a filter circuit to suppress
Q840 regulator makes +5V to supply to microcomputer
abnormal radiation. Degaussing circuit using thermistor is
and also to output the reset signal of microcomputer.
equipped at after SR81 relay. R811 is a damping resistor to
remove light regulator noise. D801 is a bridge rectifier

L901

R811

Rectified
F801 D899 C801 output
D801
THERMISTOR C810
R810

Surge T801
+3V-1
QB30 MICOM
Q863
POWER

SR81
Q840
1 5 +5V (to MICOM)
C840
2 4 Reset
3
C842
T840 D340
C843

Fig. 14-2 Rectifying circuit and standby power supply

3. MAIN SUPPLY CIRCUIT

This circuit is a current resonant switching power circuit

using hybrid IC Q801 (STR-Z3201). The current resonant
power supply realizes small, highly effective and low noise
power. Output of main supply are for H. deflection circuit
(+125V), for audio output circuit( +25V) and for signal
processing circuit (Low B, +12V). The supply (Low B,
+12V)
for signal processing circuit is equipped with 3 terminal
regulator and 4 terminal regulator with switch in the following
stage, to supply 9V-1, 9V-2, 5V-2 and 5V-3 to signal
processing circuit.
Audio output supply and signal processing circuit supply
lines are equipped with protecting fuses F899 (for audio
output line), F890 (for signal processing circuit line) which
breaks in circuit failure like short of load. And F860
breaks to protect the circuit in the failure of primary circuit
(break of Q801).

100
4. OUTLINE OF CURRENT RESONANT
TYPE SUPPLY
Basic configuration of current resonant type power supply
used in CN32E90 is shown on figure 14-3. Basic operation
is as follow. Primary winding of converter trans and resonant
capacitor are connected in series to consist of LC series
resonant circuit. And this is drived by push-pull of two power
MOS FET’s. Converter transformer operates in forward
mode. Just when primary switching device turns ON,
converter trans produces the secondary output.
Automatic voltage control operation is done in such way that
+B voltage is detected by error amp. to be fed back to
the primary OSC circuit via photo coupler, then controls
frequency.

D
O R
S I +B
C V
E

ERROR
AMP
PHOTO
COUPLER

Fig. 14-3. Basic diagram

5. FUNDAMENTAL THEORY

Voltage generating on L of LC series resonant circuit has

characteristic which varies with frequency peaking at resonant
point f= 1/ (2p LC ) [Hz] as shown in figure 14-4. The
circuit utilizes this characteristic to control output
voltage. Actual operation is done at higher frequency than
resonant point. By this operation, variable range of voltage VL (v)
across L ranges from maximum voltage of resonant point to
power line voltage.

VL

e
Frequency
Resonant point
1
f=
2p LC

Fig. 14-4. LC series resonating circuit Fig. 14-5. Characteristic

101
6. ACTUAL CIRCUIT

Two MOS FET’s, driver which drives FET’s and frequency control IC are combined inside HIC (Q801 ).
Converter transformer T862 is designed to have loose coupling between the primary and the secondary, and to have
some extent of leakage inductance. This is the reason why L and C (leakage inductance and resonant capacitor) are
resonated during period that rectifying circuit (diode) connected to the secondary winding conducts. Rectifying
circuit of the secondary winding uses double wave rectifier considering current balance of switching device, because
converter transformer is driven in push-pull. The function of STR-Z3201 is explained below. Fig. 14-6 shows
block diagram and figure 14-7 shows waveforms at main terminals.

<<FUNCTION OF HIC>>
(1) Output switching element
Uses two power MOS FET’s, and operates in push-pull. Voltage across the switching element does not increase more than
power line voltage basically, and therefore, element of low rating voltage (enduring 200V) is used.
(2) Driving circuit
Drives output switching element. MOS FET is specially used for driving element of high side, and to drive this, bootstrap
circuit is equipped.
(3) Dead time
To avoid that two switching element turns ON at the same time in push-pull operation, dead time is arranged.
(4) CT terminal (Pin 5) About basic oscillation
Variable frequency oscillator is equipped inside frequency control IC, charge and discharge of the capacitor C862
connected to this terminal decide oscillation frequency and dead time. This oscillator generates triangle wave signal with
low level of 2.5V(TYP) and with high level of 4V(TYP). Charging time of oscillator becomes output-on period, and
discharging time becomes dead time.
(5) RT terminal (Pin 5) About lowest oscillation frequency
Lowest oscillation frequency is decided by capacitor C862 connected to pin 4 and resistor R867 connected to this terminal.
(6) CONT terminal (Pin 6) About frequency control
Current flowing out of this terminal varies charging current of oscillating capacitor C862. Therefore, flowing of CONT
terminal current corresponding to feedback quantity from photo coupler (Q862) varies charging time of C862 and controls
oscillation frequency. Maximum oscillation frequency is decided by R864 connected to CONT terminal.
(7) Css terminal (Pin 8) About soft start
Capacitor (C866) and resistor (R863) for soft start are connected to make TV start at high frequency in the time of power
on and gradually make frequency lower. This function suppresses rush current in POWER MOS FET output and provides
stable starting of TV.
(8) CD terminal (Pin 9)
Latch circuit detects abnormal operation to hold the status of operation seizing, and if following condition as a result of
detecting abnormal operation comes, the latch circuit begins to start.
*In operation of over voltage protection (OVP) circuit
*In operation of thermal shock detection (TSD) circuit
*In operation of over current protection (OCP) circuit
*In going down and no recovery of Main +B output voltage
Until latch function begins to operate, the charging time of capacitor C869 connected to CD terminal (Pin 9) is utilized
to produce delay time. To release the latch function after operating once, turn off power and turn on again.
(9) OC terminal (Pin 12) About over current protection (OCP) function
This is to detect current in LC series resonant circuit, and to suppress over current to stop operation.
(10) Over voltage protection (OVP) circuit
This is to make latch circuit operate when voltage at Vcc terminal (Pin 10) exceeds 22V (TYP).
(11) Thermal shock detection (TSD) circuit
This is to make latch circuit operate when temperature inside IC exceeds 150°C.

102
<< BLOCK DIAGRAM AND PIN FUNCTION >>

Vcc VB HO G(H)

10 16 3 2

TSD OVP START 1 VIN

R1
CD 9 DELAY LATCH REF Logic

15 OUT

OSC R2
OC 12 OC CONTROL OSC

14 COM

R4 R3
8 6 5 7 4 11 13

Css CONT CT RT GND LO G(L)

Fig. 14-6. STR-Z3201 block diagram

Pin No. Symbol Function

1 VIN Half bridge power input
2 G(H) High side MOS FET gate
3 HO High side gate drive output
4 GND Control section ground
5 CT Capacitor connection terminal for oscillation
6 CONT Oscillator control terminal
7 RT Resistor connecting terminal for oscillation
8 Css Capacitor connecting terminal for soft start
9 CD Capacitor connecting terminal for delay latch, ON-OFF terminal
10 Vcc Control section power terminal
11 LO Low side gate drive output
12 OC Over current detecting terminal
13 G(L) Low side MOS FET gate
14 COM Half bridge ground
15 OUT Half bridge output
16 VB High side gate drive power input

Table 14-1. STR-Z3201 pin function

103
 DATE TIME

=4V

CT PIN VOLTAGE
=2.5V

OSC OUT SIGNAL

(PIN11) ON OFF
LOW SIDE
GATE VOLTAGE

(PIN2)
HIGH SIDE OFF ON
GATE VOLTAGE

(PIN 15) =VIN

PUSH-PULL PIN VOLTAGE
OUT VOLTAGE (PIN 1)

OV

(PIN 15)
PUSH-PULL
OUT CURRENT
OA

Fig. 14-7 Waveform at each pin

104
7. OTHER POWER CIRCUIT

Power supply circuits excepting main and standby supply

circuits are explained here. Power supplied from T461
(Flyback transformer) of H. deflection circuit is shown in
figure 13-8. Flyback transformer supplies 200V for video
output from pin 3, 27V for V. out circuit from pin 6, and -27V
for side DPC circuit from 5 pin respectively.
Resistors (R327, R462) inserted in each line are protecting
resistor which fuses in abnormal situation like load short.

-27V
AFC FBT
BLANKING 10 ANODE

HEATER 9
R642
5
C461 D460 4
FOCUS

C3\7
7
R327
+27V 6
C310 D302
D406
200V 3
SCREEN

+B 2
C448
Q404 1 8 ABL
Collector

Fig. 14-8. Other power circuit

105
8. PROTECTOR MODULE (Z801)
line, Tr8 turns on to supply base current into Tr6 through
CN32E90 employs protector module which combines in one
ZD4. In case of X-RAY protection circuit, when high voltage
package protection circuits for X-RAY protection and over
increases abnormally, Tr10 and Tr9 turns on to supply base
current protection, and error amplifier for +B voltage
current into Tr6 through D3, then this causes Tr6 and Tr5
detection. This is for the purpose of small size and
turn on to make power signal from microcomputer in low
standardization of protection circuit, and what were discrete
level. Besides, by the positive feedback that turning on of
circuits in conventional chassis are arranged into module.
Tr6 causes Tr7 turn on to make base current flow to Tr6, as
Equivalent circuit is shown in figure 14-9. A section is error
long as 5V is supplied to pin15, Tr5, Tr6 and Tr7 continues
amplifier for +B voltage detection, B section is over current
to be on to keep safety. Therefore the operation is not
protection circuit and C section is X-RAY protection circuit.
released by remote control, but continues until AC cord is
D section forces power signal from microcomputer to set in
pulled and inserted. When this module operates, red blinking
low level by the signal from protection circuits, and to turn
of power LED shows the operation of protection circuit.
OFF the power relay and keep it. Actually in case of over
current protection circuit, when over current flows in +B

R470
+25V over voltage
+B
POWER protection
Q862 +27V over current
X-RAY
protection
R472 R479
C470
R890
C474 +25V
5V-1
5 3 16 15 6 2 1 14 12 13 11

R25 R23
Tr9 Tr10

A R9 R19
R16 D1 R20
R2
ZD4
R10 Tr8
Tr7 D3
B
D R14 R15
Tr1 R21 R22
C
Tr6
R12
R3 C1 R26
Tr5 R11
ZD1

7 17
Pins 4, 8, 9,10: No connection

Pin14: Gate terminal

Protection circuit begins to operate with
1.5V or more of this termianl voltage.

Fig. 14-9 Protector module equivalent circuit

106
TROUBLESHOOTING CHART OF POWER CIRCUIT
No raster

17 23
9
YES
Fuse F801 breaks Check/Repair AC circuit Replace F801

No 18 24
10 Is the following
YES YES
point short? Replace
Fuse F860 breaks #1-#14, #1-#15, Q801, F860
#14-#15 of Q801
No
No 25

Replace F860

26
19
Instantly turns ON and 11
then turns OFF immediately OK NG Check/Repair
Check relay SR81 Voltage across C810 D801, R810
C810

1 20
12 27 31
NG
NG NG
Check/Repair Check voltage across Does pin 15 of Q801
Voltage across C868 Check/Repair
T840, D840 C840 operate in switching?
C868, D864,
28 R871, D876,
2 OK R861
13
No Check/Replace
Check/Repair OK Instantly switching Q801, C870, T862
Voltage at pins 4 and then stops
T840 or 5V-1
and 5 5V? immediately
using circuit 30

14 YES Check/Repair Q801, C862, Q862

3 No Z801, D883, D884, R864
Check QA01 Is base voltage of 21 32
(pin 7), QB30 Q843 high level? (4.3V) NG
Voltage across C889 Check/Repair F899, D885,
YES D886, audio power line
4 15 OK
Power LED Check/Repair Q843, SR81 22 33
blinks in red. NG
Voltage across C897 Check/Repair F890, D891, D892

OK
34
YES 16
5 NG
Is voltage at pin 22 (H-Vcc)
Voltage across C884 Check/Repair Q801, D883, of Q501 9V?
jumps instantly to D884, Z801, R883, R884,
140V or more Q862, R864
35 OK

No
6 Check peripherals of start
circuit Q430 and audio Vcc
Z801 makes over current protection circuit,
X-RAY protection circuit and +27V over
voltage protection circuit operate
36 37

NG
7 Check R920 and
Check deflection Does heater light?
circuit CRT Drive board

OK
38

Check peripherals of
Q501 and video out circuit
107
(No RASTER)
8
No RASTER

1
4 10
NG Red lights
Check/Replace Is the status of power
Check F470
F470, Q404 LED?
OK Red blinks
5
Is voltage at pin 22 (H-Vcc)
NG of Q501 9V?

2 OK
21
Check peripherals of 13
LED
start circuit Q430
Short R370 and turn Red blinks Check peripherals of V.out
and audio Vcc
power on again circuit Q301 and +27V line
(See note below.)

3 6 22
15
NG LED
Check R920 Check H. out circuit;
Does heater light? Open R472 and turn Red blinks
CRT Drive board C440, C444 and X-RAY
power on again
(See note below.) protection circuit
OK (including Z801)
7
Red blinks
Check peripherals of 17 23
Q501 and video out
circuit Short R470 and turn F470 blinks
power on again Check main B line and
H. out circuit (Q404, 4T461)
(See note below.)

Red blinks
19

Check protector module

Z801 and power circuit

Note: Do not take time, check within short time.

108
SECTION XV
DSP CIRCUIT

109
1. ORIGINS OF DOLBY SURROUND
Dolby Stereo movies and Dolby Surround video and television
programs include an additional sonic dimension over
conventional stereo productions. They are made using a Dolby
MP (Motion Picture) Matrix encoder, which combines four
channels of audio into a standard two-channel format, suitable
for recording or transmitting the same as regular stereo programs.
To recapture the dimensional properties brought by the
additional channels, a Dolby Surround decoder is used. In
the theatre, a professional decoder is part of the Dolby Stereo
cinema processor used to play 35 mm stereo optical prints.
The decoder recovers the left, center, and right signals for
playback over three front speakers, and extracts the surround
signal for distribution over an array of speakers wrapped
around the sides and back of the theater. (These same
speakers may also be driven from four of the six discrete
tracks on 70 mm Dolby Stereo magnetic prints, but in this
case no decoder is needed.)
Home viewing of movies on video has become extremely
popular, and with the advent of stereo VCR's, stereo television
and digital video discs, the audio side of the video presentation
has improved considerably, inviting the use of full-range
sound reproduction. The ability to deliver high quality audio
in these formats made it easy to bring MP Matrix-encoded
soundtracks into the home as well, thus establishing the
foundation for Dolby Surround.
2. THE DOLBY MP MATRIX
One of the original goals of the MP Matrix was to enable
Dolby Stereo soundtracks to be successfully played in theaters
equiped for mono or two-channel stereo sound. This allows
movies to be distributed in a single optical format, and
furtheremore results in complete compativility with home
video media without requiring separate soundtrack mixes.
Since the three front channels of the MP Matrix are assembled
in virtually the same way as a conventional stereo mix --- left
into left, center equally into left and right, and right into
right-playing a Dolby Stereo soundtrack over two speakers
reproduces the entire encoded soundtrack. There is but one
exception: the surround signal, though audible, is not
reproduced in its proper spatial perspective. When the first
home decoder was developed in 1982, its goal was to restore
this lone missing dimension.
Before we discuss decoders, it is necessary to see how the MP
Matrix encoder works. Referring to the conceptual diagram
in Fig. 15-1, the encoder accepts four separate input signals;
left, center, right, and surround (L, C, R, S), and creates two
final outputs, left-total and right-total (Lt and Rt).
The L and R inputs go straight to the Lt and Rt outputs without
modification, and the C input is divided equally to Lt and Rt
with a 3 dB level reduction (to maintain constant acoustic
power). The S input is also divided equally between Lt and Rt,
but it first undergoes three additional processing steps:
a. Frequency bandlimiting from 100 Hz to 7 kHz.
b. Encoding with a modified from of Dolby B-type noise
reduction.
c. Plus and minus 90-degree phase shifting is applied to
create a 180-degree phase differential between the
components feeding Lt and Rt.
It is clear there is no loss of separation between the left and right
signals; they remain completely independent. Not so obvious
is that there is also no theoretical loss of separation between the
center and surround signals. Since the surround signal is
recovered by taking the difference between Lt and Rt, the
identical center channel components in Lt and Rt will exactly
cancel each other in the surround output. Likewise, since the
center channel is derived from the sum of Lt and Rt, the equal
and opposite surround channel components will cancel each
other in the center output.
The ability for this cancellation technique to maintain high
separation between center and surround signals requires the
amplitude and phase characteristics of the two transmission
channels to be as close as possible. For instance, if the center

Left + + Lt
+ +

DOLBY NR +90 DEG

Center -3dB Surround -3dB B.P.F
ENCORDER -90 DEG

+ +
Right + + Rt

Fig. 15-1 Conceptual Dolby Stereo/Dolby Surround encoder

110
channel components in Lt are not identical to the ones in Rt
as a result of a channel balance error, center information will
come out of the surround channel in the form of unwanted
crosstalk.
3. THE DOLBY SURROUND DECODER
This leads us to the original Dolby Surround decoder. The
block diagram in Fig.1 5-2 shows how the decoder works.
Except for level and channel balance corrections, the Lt
input signal passes unmodified and becomes the left output.
The Rt input signal likewise becomes the right output. Lt and
Rt also carry the center signal, so it will be heard as a
"phantom" image between the left and right speakers, and
sounds mixed anywhere across the stereo soundstage will be
presented in their proper perspective. The center speaker is
thus shown as optional since it is not needed to reproduce the
center signal.
The L-R stage in the decoder will detect the surround signal
by taking the difference of Lt and Rt, then passing it through
a 7 kHz low-pass filter, a delay line, and complementary
Dolby noise reduction. The surround signal will also be
reproduced by the left and right speakers, but it will be heard
out-of-phase which will diffuse the image.
Since the heart of the decoding process is a simple L-R
difference amplifier, it is referred to generically as a "passive"
decoder. This is to distinguish it from decoders using active
processes to enhance separation which are known as "active"
decoders.
4. DSP CIRCUIT
A surround component (L-R) is extracted from L, R audio
signals coming through the AV SW in the matrix circuit as
shown in Fig. 15-3. The surround component enters the DSP
circuit through the LPF.
The signal is A/D converted, delayed by an arbitrary time of
0~100 msec (every 3.2 msec) by digital process and then D/
A converted and outputs from the DSP IC. The DSP IC
develops two outputs; (LO) for FRONT (LO) and (RO) for
REAR and each output is controlled by the microcomputer
for each surround mode. The output signal (LO) for FRONT
is added and subtracted with the input signal in a matrix
circuit and output from the front speaker in passing through
the audio processor and main amplifiers.
At the same time, the output signal (RO) for REAR is fe?? to
the Dolby NR circuit, but switched to "Dolby surround"
mode, and then output from the rear speaker in passing
through audio processors and rear main amplifiers.
In this case, the DSP stands for not only a simple digital
surround processor but also a digital surround field processor.
That is, it works to give a simple surround effect but to give
effect as if the listener can feel reality suitable for the
programs. For example, it aims to give the listeners a reality
matching to each program they are enjoying in their home
listening room so that they can obtain reality of big concert
hall or feel as if they are watching a move at a reserved seat
in a movie theater.

INPUTS OUTPUTS
L L
Left
Lt R R MASTER
INPUT Right
LEVEL C LEVEL
BALANCE CONTROL Center
CONTROL CONTROL
C
Surround
Rt L+R
Optical passive center siganal S

S ANTI- MODIFIED
L+R ALIAS B-TYPE NR
FILTER DECODER

7 kHz
AUDIO LOW PASS
DELAY SET
DELAY FILTER

Fig. 15-2 Passive surround decoder block diagram

111
 QD02
From QD08 QD01 DSP Q670
A/V SW Input Balance Input Buffer Front Addition Circuit Front amp
12 14 L 5 7 L L+S
L L
IN 10 8 8 Speaker
R R
R R
R L 10 R-S
9
6 5
7 3 1 3 1 L+R
MATRIX Sycrone
LPF LPF (Super woofer)
(L-R CIRCUIT) (L-R)
QD01 QD01 QD02

4 QD03 DSP IC YM7128 B

VC
TO

A/D DIGITAL DELAY Audio

Processor

112
(H002)

Buffer
VL 7
CONT LO 3 1 5
D/A LPF LO
BUS 7
QD04

Fig. 15-3 Block diagram of DSP circuit

CONVERT QD05 QD05

From Micro
computer VR Buffer DQ06
RO 3 7 3
D/A LPF
8
QD06 1 Q640
Dolby NR
Rear Amp
6
9 14 L-R +S
L
12
Speaker
QD07 DQ02 R
As shown in Fig.1 5-4, a sound emitted in a sound field can
be classified as a direct sound which directly reaches ears of
a listener, and reflected sound which comes after collision
with a wall as shown by dotted line or comes after several
times of collision as shown by double dotted lines. The
listeners are determining that they are listing in what type of
location by perceiving time difference and volume level
Direct Sound
Initial Reflection
Sound
Reverberation
Sound
Fig. 5-4
113
difference between the direct sound and the reflected sound.
For more detail, this situation can be expressed with the
direct sound, initial reflection sound coming after one time
of reflection, and trains of reverberation sound in later period
as shown in Fig. 15-5.
The DSP circuit develops these initial reflection sound and
the reverberation sound artificially and add them to the
original sounds, thereby creating rhe effect that allows the
listeners in the home listening room to feel as if they are
listening in an original location.
The DSP IC YM7128B has eight separate output taps and
their delay time and the output levels can be specified
separately, so, various sound fields can be selected by
varying the initial reflection sound. Moreover, the IC has an
internal feedback loop which controls the delay time and the
output level in considering the later time reverberation
sound.
Direct Sound
Sound Level Initial Reflection Sound
Reverberation Sound
Time
Fig. 5-5

5. DSP (Digital Surround Processor) IC
Input signal entered into analog input pin 4 of DSP IC QD03
(YM7128B) is converted to 14 bit digital signal with the
sampling frequency 23.6 kHz by A/D converter of 14 bit
floating system, and enters digital delay circuit through
digital attenuator VM and doubler.
The digital delay circuit has nine output taps, and the delay
time of each tap can be controlled independently, also each
tap position can be switched by T0 to T8 register.
In a minute, the T0 output passes through the primary FIR
(Finite Impulse Response) type low pass filter, and reduction
processing is performed by VC, then it feed-backed to the
delay input after it is added to the doubler described above.
The output of eight taps T1 to T8 is added after performing
reduction processing by GL1~GL8, GR1~GR8, and reduction
processing is performed by the digital attenuator VL or VR,
and an analog output is created by D/A converter after
passing through digital filter, comes out from pin 7 or 8.
The digital attenuated value, delay time and the coefficient
of FIR type low pass filter are set by writing the data on the
register.
This process is performed by loading three data from sub
microcomputer to microcomputer interface.
This unit has four modes as surround mode. The setting
values are described in Table 15-1.

Table 15-1 DSP control factor

Mode OFF DOLBY THEATER STADIUM NIGHT CLUB CONCERT UNIT

Control SURROUND HALL HALL
-VM (IN) -¥ P-0 P0 P0 P0 P0 dB
VL (LO) -¥ P0~ -¥ P0~ -¥ P0~ --¥ P0~ --¥
VR (RO) P0 P0 P0 P0 P0
VC (Echo) -¥ -¥ M-6 M-10 M-8
GL1 P-4 M-2 M-2 P-2
2 M-6 -¥ P-4 P-10
3 P-12 P-6 P-16
4 P-12 M-10 -¥
5 -¥ -¥
6
7
8
GR1 P0
2 -¥ P0
3 P-18
4 -¥
5 P-2 P-6 P-4
6 M-2 M-6 P-8
7 P-8 M-10 P-8
8 P-10 P-12 P-14
T0 (Delay) 0 0 0 100.0 19.4 51.6 msec
1 19.4 12.9 93.6 12.9 71.0
2 0 38.7 100.0 19.4 83.9
3 71.0 100.0 22.6 100.0
4 87.1 0 29.0 0
5 29.0 6.5 64.5
6 45.2 9.7 80.7
7 83.9 25.3 90.4
8 100.0 35.5 100.0
C0 (Filter) 0 0.71875 0.59375 0.875 —
1 0.28125 0.40625 0.125 —

114
 XD01

CD27 RD32 CD29

CD28
D01
QD03 RD33
11 12 16
XO XI /IC Vss
C1 1

CV REFERENCE VC TIMING GENERATION LD01

D
5 VOLTAGE AVDD
CD22 GENERATION 2 +B (5V)
C2
RD26
From VM T0
AIN CD21 CD20
Input LPF 4 A/D DIGITAL DELAY
CONVERTER T8 T7 T6 T5 T4 T3 T2T1
CD15
GL1
CH GL2
3
GL3
Fig. 15-6

CD23
115

GL4 VL LO
D/A 7 To LPF Output
/TI GL5 2fs CONVERTER
6 GL6 (For FRONT ch)
DC26
GL7
GL8

GL1
GL2
GL3
GL4 VR RO
D/A To LPF Output
GL5 2fs 8
MICROCOMPUTER CONVERTER (For REAR ch)
INTERFACE GL6 DC25
GL7

DIN AO SCI GL8

VSS AVSS
VDD
15 14 13 10 9

From Bus convert

(ICD04)
6. SURROUND CIRCUIT 7. INPUT BALANCE CIRCUIT

The surround circuit used in this model has the modes shown
in Table 15-2 of the modes, description will be given for 5
mode. The description will be made according to items
shown below.
Fig. 15-8 shows the input balance circuit.
The input balance circuit is to adjust gain of Lch and Rch so
that (L-R) component in the matrix circuit becomes zero.
Adjustment by the input balance volume control on the
remote hand unit.

[dB] Lch Rch

0
Surround Mode Assumed sound field Front Rear
CONCERT HALL Concert hall O O Response

THEATER Movie theater O O

NIGHT CLUB Disco, Night club O O
STADIUM Baseball stadium O O
Dolby Surround Dolby surround soft X O
OFF Off X X
-8
Min Center
Table 15-2
Control

Fig. 15-7

+9V
A/V SW QD08

L OUT + 1
2 L
CD04 Leh
3
1m50V 4 Input buffer
CD09
RD23 5 22m16V
6
15K
7
8

CD05 9
RD24 10
56K 22m 11
4V 12
Reh
R OUT R 13
Input buffer
14
CD06
1m50V

Input balance control

Fig. 15-8

116
8. MATRIX CIRCUIT 9. FILTER CIRCUIT (ANTI-ALIAS
Fig.15-9 shows the matrix circuit. FILTER)
The matrix circuit is to create a surround signal of (L-R) from Fig. 15-10 shows the filter circuit.
the Lch and Rch signals. According, if a monaural signal The filter circuit is to cut frequencies higher than 7 kHz in
enters, L-R=0, showing no surround effect exists. considering processing capacity of the DSP circuit (delay)
connected to next stage, and two stages of the filters are
employed in this unit.

QD01
CD02
Buffer
1m50V (NP)
12
Lch IN 14
13 Lch OUT

RD13
CD02 39K
39K CD15
QD01
39K
5
REF 7
Surround OUT
6 (L-R)
CD03
39K

CD16
RD14 33K
CD03 9 39K
1m50V (NP) 8
10 Rch OUT
Rch IN
QD01
Buffer

Fig. 15-9

RD17 RD18 RD19

10K 10K 10K QD01 RD20 RD21 RD22
3 10K 10K 10K QD02
3
2
2

CD11 CD12 CD10 CD13 CD14 CD16

M2700P M6800P 390P M2700P M6800P 390P

Fig. 15-10

117
10. DSP CIRCUIT (DELAY)
Fig.1 5-11 shows the DSP circuit.
The DSP circuit delays the surround signal entered by a time
of digital delay determined for each mode and then outputs
the signal. The DSP circuit is controlled with 3 line-bus data
from the sub-microcomputer. The DSP circuit develops two
type of outputs; one for front addition and the other for rear
output. Details of the outputs are shown in Table 15-2.

Bus data

16 15 14 13 12 11 10 9
DIN AD SCI XI XO
DSP
QD
YM7128B
Ycc CH IN CY Lo Ro
1 2 3 4 5 6 7 8

LPF

Rear OUT

Surround IN
LPF
(L-R)

Front OUT

Fig. 15-11

118
11. 7 kHz LOW PASS FILTER
The DSP outputs are received at inputs of high impedance
voltage followers and then fed to 7 kHz LPFs. Since L and
R components of the DSP output are processed in time
sharing by the D/A converter, the LO and RO outputs must
be received at the high impedance input circuits. The LPFs
which receives the signals consist of OP amplifiers.

CD39
M5600P
QD03
CD32
1m50V QD05 RD30 RD29 RD28 QD05
DSP 3 10K 10K 10K
LO 7 1 5
2 7 Front
6
CD26 (Addition circuit)
RD31 CD31 CD30
33P 1M 820P
M3300P

REF

CD17
RD34 M6800P
1M
QD06 RD47 RD46 RD45
5 QD06
DSP 7 10K 10K 10K
8 3
RO 6 1
CD34 2 Rear
1m50V (Dolby NR circuit)
CD25 CD19 CD18
33P M2700P 390P

Fig. 15-12

119
12. DOLBY NR CIRCUIT
Fig. 15-13 shows the Dolby NR circuit.
The Dolby NR circuit used in this unit is a modified B type
for Dolby surround and the operation characteristics are
shown in Fig. 15-14. RD61
47K

CD43 CD44 CD45

M4700P M0.027 M5600P

RD60
47K
RD66 RD65
18K 150
16 15 14 13 12 11 10 9
Dolby QD02
12
N.R 14
QD07 Rear OUT
TA7629P REF
13 CD46
4.7m16V
1 2 3 4 5 6 7 8 (NP)

RD48
5.6K
Rear IN CD38 RD25 RD27
CD35 1m50V 47K 33K
RD49 10m16V
2.2K

ENCODE
Fig. 15-13
[dB]

Response

f [Hz]

DECODE (Dolby NR)

[dB]

Response

f [Hz]

Fig. 15-14
120
13. DSP FRONT ADDITION CIRCUIT
Fig. 15-15 shows the front addition circuit for the surround
signal. In the DSP operation of this model, the surround
signal is added to the front channel to provide the surround
effect if rear speakers are not used.
In practice, the front addition surround signal output from
the DSP circuit is added to Lch with the phase non-inverted
and to Rch with the phase inverted.

RD01
20K QD02
5
Lch IN 7
Lch OUT Lch OUT

RD06
RD09 RD04 27K
16K 15K
Surround
REF
(L-R)
RD10
15K RD08
24K

RD07 9
RD05 15K 8
16K Rch OUT Rch OUT
Rch IN
10 QD02

Fig. 15-15

121
14. BUS CONVERTER 15. NEUTRAL BIAS
The bus converter receives I2C-bus data sent from the main To develop a neutral bias voltage for the OP amplifier, +B
microcomputer and converts them into DSP control data. (12V) is divided with resistors.
The data are transferred to the data input of the DSP.

To DSP (QD03)

+B

RD42 RD43 RD44 RD12

1K 1K 1K 1K
REF

RD11 CD01
1K 100m16V
5 6 7 8
GND
DIN

SCI
AD

QD04
Fig. 15-17
RESET

SDA
SCL
Vcc

+5V
4 3 2 1

RD39 RD38
100 100

ICD03
16 pin
From main
microcomputer

Fig. 15-16

122
 16. AUDIO OUTPUT AMPLIFIER (For Rear SP)

The audio amplifier develops 5.0W two circuit.

Vcc
C646 C650
100m25V 1000m35V

4 7
R640 C647 C641
6.8K 1000P 2.2m50V Ripple Filter Vcc
C652 R660
Rear INPUT 2 470m35V 1.5W(5W)
6
R641
1.8K R685
2.2W
SURROUND
1 SPEAKER
C645 C655 TERMINAL
R647 0.12m
22K 47m25V
3 Pre GND PW-GND 5
Mute

C649 Q641 Q640 TA8213K

2.2m50V 2SC2878A

R644
100K

Fig. 15-18

123
17. TROUBLESHOOTING CHART

No sound.

NG
Is power supplied +5V, +12V lines? Check Power supply circuit.

OK

NG
Are input signals applied to 13 , 14 terminals? Check A/V SW output.

OK

NG
Are inputs applied to pins 14 , 8 of QD01? Check Input Buffer (QD01).

OK

NG
Do output pins L 10 , R 11 develop outputs? Check DSP front addition circuit (QD02).

OK

Check Sound volume control circuit (H002) and Front

power amplifier circuit (Q670).

No rear sound.

NG Rear sound is not developed as Adaptive

Is rear sound component contained in the matrix circuit is actuated.
input signal? Use an effective source.

OK

NG Check L-R matrix circuit (QD01) and

Is input applied to pin 4 of QD03? Anti-alias Filter (QD01 & 02).

OK

NG
Do pin 7 and 8 of QD03 develop outputs? Check DSP (QD03) and DSP control data.

OK

NG
Does Sout 6 develop the output? Check LPF (QD06) and Dolby NR
circuit (QD07 & 02).

OK

Check Sound volume control circuit (H002) and Rear

power amplifier circuit (Q640).

124
 SECTION XVI
FAILURE DIAGNOSIS PROCEDURES

125
1. H STARTING CIRCUIT FAILURE DIAGNOSIS PROCEDURES

No raster.

Check main power Check X-Ray circuit,

voltage. (125V?) protection circuit.

Check voltage
To "Start circuit diagnosis".
at pin 32 of 0501.

Check wafeform
at pin 23 of IC501.

Check and repair

H drive circuit, Check and repair C403
H output circuit, D490, Q501 (TA1222N)
FBT circuit, etc.

Start circuit diagnosis

Start circuit diagnosis.

NG NG
Check D431 Check voltage of Check and repair
cathode voltage. Audio + B line. power supply circuit.

OK OK

Check and repair R432, Q430,

D431 and D430.

NG Check and repair C430, C431,

Check voltage
at pin 22 of Q501. D490 and L400.

OK
OK

Check and repair

Q501 (TA1222N).

126
2. DEFLECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES

No vertical scanning

Horizontal one line.

NG Check, repair and replace

Check +27V power supply. C310, D302, Q301, R327.

OK

More than 20V Check and repair L462

Check voltage at Normal: R313, R304, R305, R306,
+ leed of C306 15V R307 in vertical ourput circuit.

Check pin 13 input of Check pin 31 output of

Q302 with Q501 with
synchronous scope. NG synchronous scope. OK
Check and repair Q302.
5Vp 5Vp

OK

Check pin 15 of Q302

with synchronous scope. NG
Check DEF + Vcc pin 22
of Q501 is 9.0V. V/C + Vcc,
1.5V pin 40 and 46 of Q501 is 9.0V.

OK

Check output circuit. Replace Q501.

NG Check and repair 910V

Check pin 3 of
Q302 is +9V. D420, Q421, Q420 and R424.

OK

Replace Q302

127
3. LEFT-RIGHT PIN-CUSHION DISTORTION CORRECTION CIRCUIT

Left-Right pin-cushion
distortion correction is
not carried out.

Check voltage across C460 -27V:NG Check and repair R469

on DPC circuit. (-27V) output circuit.

-27V OK

Check waveform Parabola waveform

Check and repair around Q461.
at Q461 collector. is not observed

Parabora OK
waveform

Check waveform Parabola waveform Check and repair D464, D465,

at Q462 collector. is not observed D466, R343, R341, R465.

Parabora OK
waveform

Check waveforms at Q462 Parabola waveform Check and repair around

emitter Q460 collector. is not observed Q460, Q462

Parabora OK
waveform

Check, replace or repair

C467, C464, D461, L461

128
4. X-RAY PROTECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES

X-ray protection circuit does

not work (When X - R
terminals are connected).

NG Check and repair D471, R472.

Check voltage at D471
Check and repair around pin
cathode. (20 - 22V?)
9 of FBT.
OK

Check and repair Z801.

129
5. PROTECTION CIRCUIT DIAGNOSIS PROCEDURE

Operation of protection circuit

for Thyrister D862. (SR81
Relay turns on but immediately
turns off.)

Power on with D870 Check over-current protection circuit,

opened. (Do not turn on H output and repair D870, Q870,
for a long period.) SR81 turns on for a short time R870 - R873, R876, R881.
but immediately turns off.

Check over-voltage protection circuit

With SW turned on, Higher than 130V. (125V) and D846, D878, Q801, Q841,
check 125V line voltage
Q845, Q862 and repair.
with oscilloscope.
Check broken pattern in feedback loop.
Less than 130V

Check over voltage protection circuit

With SW turned on,
check 24.5V line voltage
with oscilloscope.
Less than 35V
Higher than 35V.
(24,5V) (125V rectification line opened,
or 24.5V line leaded light.)
Check rectification line (T862 -C889),
Q610, pattern connectors connected to
Q610, and repair.

With SW turned on, Higher than 24.1V. Check X-ray protection circuit, H output
check voltage across C471 circuit, X-ray protection detector circuit,
with oscilloscope. and repair.

Less than 24.1V

Check C867, D862, D878,

Q863, R874, R875, R877,
and repair.

• 125V line becomes over voltage, thyristor D862 comes in to failure, and when Q863 does not turn on, D888 is short-circuited
and intermittent oscillation occurs. To protect the circuit a double protection system is employed.
• When the overvoltage protection circuit is working. never turn on the power with the protection circuit disabled.
High voltage will be stepped up and secondary breakdown may occur.

130
6. VIDEO CIRCUIT DIAGNOSIS PROCEDURES

Failure Phenomena Reference Item

No picture OSD and picture do not appear. (A)
OSD is OK, picture does not appear. (B)
OSD is OK, picture does not appear. (A/V circuit is defective.) (C)
Picture of only VHF/UHF of main screen does not appear. (D)
Picture of only VHF/UHF of sub screen does not appear. (E)
No color After Q501, no color (F)
A/V, comb, etc. (G)

* Diagnosis of video signal through VIDEO input is done by inner video signal SGV as well.
In this time, do not connect any cable to VIDEO 1.

131
(A) OSD AND PICTURE DO NOT APPEAR

NG
Check R920 (heater resistor) and
Check that heater or CRT lights.
power/def circuit.

OK

Power supply of CRT Drive board. NG

Check power/def circuit.
9V, 200V

OK

NG
Check waveform of TP-47R, G, B. Check CRT and power/def
circuit.

OK

NG
Check Q907, Q910 and blanking
Check waveform of TP-46R, G, B.
circuit. (pow/def board)

OK

Check Q501 power. NG

Pins 22, 40, 46---------- 9V Check power line and power/
Pin 12---------------------- 5V def circuit.

OK

NG Check I2C bus line and

Check waveform of I2C bus line.
QA01 (MICOM).

OK

Check Q501 and peripherals. Check QA01 and periheral circuit.

132
(B) OSD IS OK, PICTURE DOES NOT APPEAR

Check waveform at pin 53 (Y2 input) OK OK

Check I2C bus line waveform Check Q501.
of Q510. Approx. 0.7VP-P at pins 27, 28 of Q501.

NG NG

Check waveform at pin 4 (Y1 output) OK

of Q510. Approx 0.7VP-P Check C203. Check I2C bus line
and QA01.

NG

OK
Check waveform at pin 15 (Y1 output)
of Q501. Approx 1VP-P Check Q501.

NG

Check waveform of comb Y output. NG NG

Check waveform of comb Y input. Check A/V circuit.
2VP-P 2VP-P Go to (C).

OK OK

Check A/V circuit. Go to (C).

NG
Check waveform of comb Y input.
0.4 VP-P (3.58MHz) Check Q501.

OK

Check Comb Board.

133
(B) OSD IS OK, PICTURE DOES NOT APPEAR (A/V CIRCUIT IS DEFECTIVE)

OK
Check waveform at pin 36 (Y-AV)
Check Q501. Go to (B).
or QV01. 2VP-P

NG

OK
Check waveform at pin 30 (Y-Comb) or QV01. Check QV01.

NG

OK
Check waveform at pin 38 (V-AV) or QV01. Check Comb filter. Go to (B).

NG

Check input waveform. 1VP-P

Video1 Pin 12 of QV01 OK
Video2 Pin 10 of QV01 Check QV01.
Video3 Pin 16 of QV01

NG

Go to (D), (E)

134
(D) PICTURE OF ONLY VHF/UHF OF MAIN SCREEN

Picture of only VHF/UHF of main screen

does not appear

OK Check waveform OK
Check waveform at pin 7 Replace QV01
of H002. at pin 7 of QV01.

NG NG
Check/Replace QV40, QV41,
QV42, QV43.

NG
Check power voltage at pin 4 Check power circuit
of H002. 9V

OK

Check waveform at pin 2 OK

Replace H002
of H002.

NG

Check power voltage of H001.

Pin3 9V NG
Pin8 5V Check power circuit
Pin9 32V

OK

Replace H001.

135
(E) PICTURE ONLY VHF/UHF OF SUB SCREEN DOES NOT APPEAR(B) OSD IS
OK, PICTURE DOES NOT APPEAR

Picture of only VHF/UHF of main screen

does not appear

OK OK
Check waveform at pin 15 Replace QV01.
Check waveform
of HY01.
at pin 28 of QV01.

NG

NG
Check CV09,
RV12.
Check power voltage of HY01.
Pin9 9V
Pin7 5V
Pin2 32V
NG
Check power circuit.

OK

Replace HY01.

136
(F) NO COLOR (AFTER Q501)

Check waveform at pin 13 of Q501. NG

Burst: 0.3 to 0.6 VP-P Check Q503 and A/V circuit.

OK

Check power supply of Q501. NG

Pin 1=5V, Pins 22, 40, 46=9V Check power/def circuit.

OK

Check waveform at pins 5, 6 of Q501. NG Check Q501 and pins 10, 11

Color bar: approx. 0.6VP-P peripherals.

OK

Check waveform at pins 51, 52 of Q501. NG

Check C514, C515.
Color bar: approx. 0.6VP-P

OK

NG Check I2C bus line, and check bus

Check waveform of I2C bus line. data, micom memory, etc.

OK

NG
Check Q501.

137
(G) NO COLOR (A/V, COMB)

Check waveform of video output. OK

Check waveform at pin 32 of QV01.
(or check monitor picture.) Burst: 0.3 to 0.6 VP-P

OK NG

NG

Check waveform at pin 34 of QV01. Check comb filter.

Check input waveform as noted below. NG

VIDEO 1 pin 14 of QV01 Check QV01.
VIDEO 2 pin 10 of QV01
VIDEO 3 pin 18 of QV01 OK

Check Q501.

NG
OK

Check U/V tuner,

Check QV01.
IMA module, etc.

138