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Table Of Contents

3.4ALU - Arithmetic Logic Unit
3.6Instruction Execution Timing
3.10RAMP and Extended Indirect Registers
3.11Accessing 16-bit Registers
3.11.1Accessing 24- and 32-bit Registers
3.12Configuration Change Protection
3.14Register Descriptions
4.3Flash Program Memory
4.10Data Memory and Bus Arbitration
4.14I/O Memory Protection
4.15Register Description – NVM Controller
4.16Register Descriptions – Fuses and Lock bits
4.17Register Description – Production Signature Row
4.18Register Description – General Purpose I/O Memory
4.19Register Description – External Memory
4.20Register Descriptions – MCU Control
4.20.8AWEXLOCK – Advanced Waveform Extension Lock register
4.21Register Summary – NVM Controller
4.22Register Summary - Fuses and Lock Bits
4.23Register Summary - Production Signature Row
4.24Register Summary – General Purpose I/O Registers
4.25Register Summary – MCU Control
4.26Interrupt Vector Summary – NVM Controller
5.DMAC - Direct Memory Access Controller
5.6Priority Between Channels
5.13Register Description – DMA Controller
5.14Register Description – DMA Channel
5.14.5TRFCNTL – Channel Block Transfer Count register Low
5.15Register Summary – DMA Controller
5.16Register Summary – DMA Channel
5.17Interrupt vector summary
6.4Event Routing Network
6.8Register Description
7.System Clock and Clock Options
7.5System Clock Selection and Prescalers
7.6PLL with 1x-31x Multiplication Factor
7.8External Clock Source Failure Monitor
7.9Register Description – Clock
7.10Register Description – Oscillator
7.10.5RC32KCAL – 32kHz Oscillator Calibration register
7.11Register Description – DFLL32M/DFLL2M
7.12Register Summary – Clock
7.13Register Summary – Oscillator
7.14Register Summary – DFLL32M/DFLL2M
7.15Oscillator failure interrupt vector summary
8.Power Management and Sleep Modes
8.5Minimizing Power Consumption
8.5.6On-chip Debug System
8.6Register Description – Sleep
8.7Register Description – Power Reduction
8.8Register Summary – Sleep
8.9Register Summary – Power reduction
11.6Configuration Protection and Lock
12.Interrupts and Programmable Multilevel Interrupt Controller
12.7Interrupt Vector Locations
13.3I/O Pin Use and Configuration
13.5Input Sense Configuration
13.19Interrupt Vector Summary – Ports
14.TC0/1 – 16-bit Timer/Counter Type 0 and 1
14.4Clock and Event Sources
14.11Timer/Counter Commands
15.AWeX – Advanced Waveform Extension
16.Hi-Res – High-Resolution Extension
17.RTC – Real-Time Counter
17.5Interrupt Vector Summary
18.RTC32 – 32-bit Real-Time Counter
18.5Interrupt Vector Summary
19.TWI – Two-Wire Interface
19.3General TWI Bus Concepts
19.7Enabling External Driver Interface
19.8Register Description – TWI
19.9Register Description – TWI Master
19.10Register Description – TWI Slave
19.11Register Summary – TWI
19.12Register Summary – TWI Master
19.13Register Summary – TWI Slave
19.14Interrupt Vector Summary
20.SPI – Serial Peripheral Interface
20.9Interrupt Vector Summary
21.4.1Parity Bit Calculation
21.6Data Transmission - The USART Transmitter
21.7Data Reception - The USART Receiver
21.8Asynchronous Data Reception
21.9Fractional Baud Rate Generation
21.10USART in Master SPI Mode
21.12Multiprocessor Communication Mode
21.12.1Using Multiprocessor Communication Mode
21.13IRCOM Mode of Operation
21.17Interrupt Vector Summary
22.IRCOM – IR Communication Module
23.AES and DES Crypto Engines
23.5Register Description – AES
23.6Register Summary – AES
23.7Interrupt Vector Summary
24.EBI – External Bus Interface
24.6SRAM LPC Configuration
24.8I/O Pin and Pin-out Configuration
24.9Register Description – EBI
24.10Register Description – EBI Chip Select
24.11Register Summary – EBI
24.12Register Summary – EBI Chip Select
25.ADC – Analog-to-Digital Converter
25.5Voltage Reference Selection
25.9ADC Clock and Conversion Timing
25.9.5Single Conversions on Two ADC Channels, CH1 with Gain
25.16Register Description – ADC
25.17Register Description – ADC Channel
25.18Register Summary – ADC
25.19Register Summary – ADC channel
25.20Interrupt Vector Summary
26.DAC – Digital to Analog Converter
26.3Voltage Reference Selection
27.AC – Analog Comparator
27.8Propagation Delay vs. Power Consumption
27.11Interrupt Vector Summary
28.IEEE 1149.1 JTAG Boundary Scan Interface
28.3TAP - Test Access Port
29.Program and Debug Interface
29.6Register Description – PDI Instruction and Addressing Registers
29.7Register Description – PDI Control and Status Registers
30.5NVM Controller Busy Status
30.6Flash and EEPROM Page Buffers
30.7Flash and EEPROM Programming Sequences
30.9Preventing NVM Corruption
30.11Self-programming and Boot Loader Support
31.Peripheral Module Address Map
33.Appendix A: EBI Timing Diagrams
33.8SRAM 3- Port ALE1 no CS
33.9SRAM 4- Port NOALE no CS
33.10LPC 2- Port ALE12 no CS
34.Datasheet Revision History
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ATxmega a Manual

ATxmega a Manual

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Published by Wilfred Castelino

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Published by: Wilfred Castelino on Feb 02, 2014
Copyright:Attribution Non-commercial


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