11.

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Implementation of IEEE 802.11a WLAN Baseband Processor
Je-Hoon Lee, Young-Il Lim, and Kyoung-Rok Cho, Member, IEEE
AbstractThis paper presented an implementation of a baseband processor compliant with the IEEE 802.11a standard. Some innovative techniques were proposed to improve performance. For verification and analysis of the design, we used a platform-based SoC design environment. The system consisted of a test-bed for the proposed baseband processor chip and the SoC platform implemented IEEE 802.11a MAC.

When a carrier frequency offset occurs, orthogonality between subcarriers is ruined, resulting in ICI (inter-carrier interference) between subchannels. The carrier frequency offset estimation can be obtained after the argument operation by autocorrelation of the received training signal. Eq. 1 shows the method of obtaining autocorrelation. Eq. 2 shows error estimation using the results of Eq. 1 [2].
* R ( v ) = yn yn + v = e n =0 v 1 j 2 v N

I. INTRODUCTION The IEEE 802.11a standard provides a broadband communication system using OFDM, with data rates ranging up to 54Mb/s using 20MHz channel bandwidth [1]. The basic principle of OFDM is to divide high-rate data streams so that they can be transmitted in parallel over multiplexed orthogonal subcarriers. We implemented a baseband processor for the IEEE 802.11a standard. This is configured as shown in Fig.1. We employed the platform-based SoC (system on chip) design methodology. MAC is implemented on the platformbased SoC tool, Probase and the baseband processor is integrated in a chip. The transmitter is comprised of a codec, a modulator and IFFT blocks. The receiver is comprised of a synchronization block, a FFT, an equalizer, a demodulator and a Viterbi decoder in the codec. The baseband processor consists of a codec based on the Viterbi decoding algorithm and the modem including an IFFT/FFT, synchronization block and equalizer.

yn = Re[ R(v)] + j Im[ R(v)]

2 n =0

v 1

(1) (2)

IM [ R(v)] N ( R(v)) N = tan 1 RE[ R(v)] 2v 2v

N is the number of subcarrier, v represents the number of sampling used for the autocorrelation function. () represent s an argument operation. The tan-1 circuit is used to estimate a frequency offset through the argument operation. The proposed tan-1 circuit consists of a divider, tan-1 ROM, and phase detector. The divider performs a division operation with the real and imaginary terms obtained from autocorrelation. The tan-1 ROM determines the phase 0 to /2 using a quotient from the divider. The phase detector determines the corresponding quadrant and produces the phase between ~ using the real and imaginary term as input for tan-1. We use the symmetrical feature of the tangent function. The tan-1 ROM has the values between 0 and /2, and is expanded to a range from to , based on the symmetrical feature of the tangent function. To obtain these values, re-operation is required with the sign bit of Re[R(v)] and Im[R(v)], which are the inputs for the tan-1 circuit. Eq. (3) shows the re-operation to obtain the phase detection.
= arctan Q, ReS = 0 and ImS = 0

Fig. 1. Architecture of an IEEE 802.11a WLAN baseband processor

arctan Q, ReS = 1 and ImS = 0 arctan Q , ReS = 1 and ImS = 1

arctan Q, ReS = 0 and ImS = 1

(3)

II. THE PROPOSED ALGORITHIM The following techniques are proposed to fulfill the requirements. First, a carrier offset estimator uses the new tan1 circuit based on a ROM table. Second, we adapt the new IFFT/FFT design to reduce quantization error. Finally we present a modified hard decision for the Viterbi decoder with an error prediction enhancing performance for burst error.
This research was supported by the Program for the Training of Graduate Students in Regional Innovation which was conducted by the Ministry of Commerce Industry and Energy of the Korean Government. Mr. J. H. Lee

participated in this work is supported by the Second Phase of the Brain Korea 21 Project at Chungbuk National University.

The proposed tan-1 operator has better resolution and reduces circuit size using the periodicity of the tangent function, and storing the value in the ROM for the first quadrant only. The proposed circuit shows a pull-in range of 625kHz under 5dB AWGN, and is useful when using the IEEE 802.11a WLAN standard. Second, the transmitter converts the sub-carrier expressed in the frequency domain to an OFDM symbol in the time domain using IFFT, and FFT performs reverse functions. We designed the 64-point IFFT/FFT, based on a Radix-22 algorithm in the single-path delay feedback (SDF) architecture.

1-4244-0763-X/07/$20.00 2007 IEEE

IFFT and FFT share the circuit for symmetric architecture. In designing a FFT, it is one of the most important matters to choose the algorithm in other to determine the size of hardware. But the performance of the IFFT/FFT processor improves if the number of processing bit at each stage and the twiddle coefficients are optimized according to given input signals. Although it uses the same algorithm as Eq. 4, it is called the expanding coefficient.

Ci =

max value of (i-1)th the stage max value of i th the stage

(4) (5)

1 1 1 W '1 (n) = [W11 (n) C1C2 ],W ' 2 (n) = [W2 (n) C3C4 ]

obtained from the MAC of the receiver. The SoC platform consists of the ARM board, that is, Probase and iProve. Probase is responsible for implementing the IEEE 802.11a MAC function and the transactor between the host PC and the baseband processor chip. iProve is responsible for implementing a FIR filter, ADC, and DAC. A FIR filter is to implement the virtual channel employing a conventional Rayleigh fading and Rician fading. ADC and DAC are used to test whether the timing synchronization is correct or not. This test-bed is used to test the function of the baseband processor. We input image data into the baseband processor of the receiver shown in Fig. 2. A comparison result between the transmitter and the receiver is shown in Fig. 3.

This paper acquires the new twiddle coefficients through multiplying the expanding coefficient Ci to the original twiddle coefficient as Eq. 5. Here, W is a new twiddle coefficient, C1C2 are expanding coefficients and W is the original. As a result, the proposed architecture saves 3 bits for the data, to keep the same resolution, compared with the conventional method. Finally, the proposed Viterbi decoder corrects random error efficiently. The conventional Viterbi decoder suffers from the burst error under the fading channel. If it can estimate this interval, the efficiency of error correction can be improved by modifying the following Viterbi decoding algorithm [3]. The proposed Viterbi decoding method estimates the burst error area using the value of the path metric. In the constant interval, when a burst error occurs, the minimum value of path metric significantly increases. We can estimate the error area by using this increasing minimum value. By decreasing the probability to choose the path estimated from the conventional Viterbi decoder during the burst error interval, the proposed Viterbi decoder can increase the possibility of making a correct decision for the data received after this burst error interval. The difference between the input and the decision for each data does not exceed 2 because the hard decision will be generated as either 0 or 1. If the probability is cut in half, the value of the path metric is significantly changed at the boundary between the burst error interval and guard interval. Eq. 6 shows the value for the variation in the path metric.

Fig. 2. IEEE 802.11a baseband processor simulation environment

Fig. 3. Image comparison between the transmitter and the receiver

IV. CONCLUSION This paper presents an implementation of the baseband processor, which is fully compliant with the IEEE 802.11a standard. Some techniques are proposed to fulfill the mandatory requirements in the standard. The baseband processor is integrated in a single chip. The chip is fabricated using MagnaChip 0.25m CMOS technology, and occupied a size of 5mm5mm. This chip is successfully verified by various channel environment including AWGN, multi-path Rayleigh fading, and multi-path Rician fading. REFERENCE
[1] [2] [3] IEEE standard for a wireless LAN medium access control and physical layer specification: High-speed physical layer in the 5GHz band, Dec. 1999. J. J. van de Beek, M. Sandell, and P. O. Borjesson, ML estimation of time and frequency offset in OFDM system, IEEE Trans. On Communication, Vol. 45, No. 7, pp. 1800-1805, July 1997. S. He and M. Torkelson, Design and implementation of a 1024-point pipeline FFT processor, IEEE Proc. Custom Integrated Circuit Conference, pp. 131-134. May 1998.

R max max log 2 N

(6)

max is the maximum change ratio of the path metric and N is the state number of the decoder. The proposed decoder maintain the same performance as the conventional decoders in AWGN channels. It shows the performance improving 15% in terms of the burst error of multi-path fading channels. III. PERFORMANCE ANALYSIS The simulation environment for the baseband processor consists of the host PC, SoC platform, and the baseband processor as shown in Fig.2. The host PC is responsible for generating a video stream that will be transferred to the MAC of the transmitter and for playing back the video stream