COM 353 Microprocessors

Lecture 2

Prof. Dr. Halk Gmkaya

haluk.gumuskaya@gediz.edu.tr haluk@gumuskaya.com http://www.gumuskaya.com

Introduction to Memory Basics and Memory System Design

Computer Engineering Department

Sunday, November 04, 2012

Microprocessor Based System: Collection of Addressable Registers

We

Topics for Memory Basics

A simple memory block
Memory design with D flip flops Problems with the design

can view the entire microprocessor-based system system microprocessor, ROM, RWM, and I/O ports as a collection of addressable registers. Registers in the microprocessor are internal registers, Those exist in the ROM, RWM (RAM), and I/O ports are external registers. we will start from basic Register concepts and Memory Devices

Building larger memories Mapping memory

Full mapping Partial mapping

Techniques to connect to a bus

Using multiplexers Using open collector outputs Using tri-state buffers

Alignment of data Interleaved memories

Synchronized access organization Independent access organization Number of banks

So

Building a memory block

Memory Devices
Before attempting to interface memory to the microprocessor, it is essential to understand the operation of memory components. In this lecture, we explain functions of the 2 common types of memory: Random Access Memory (RAM) (SRAM, DRAM, NV-DRAM) Read-Only Memory (ROM) (PROM, EPROM, EEPROM, Flash EPROM, mask ROM)

OBJECTIVES
this lecture enables to:

Define the terms capacity, organization, and speed as used in semiconductor memories. Calculate the chip capacity and organization of semiconductor memory chips. Compare and contrast the variations of ROM
PROM, EPROM, EEPROM, Flash EPROM, mask ROM.

Compare and contrast the variations of RAM

SRAM, DRAM, NV-DRAM.

Design address decoding methods for memory chips. Design a memory system for an 8085 based systems in terms of RAM and ROM allocation.
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Lecture Outline
1. Memory Basics
2. Memory Design with D Flip Flops 3. Random Access Memory 4. DRAM 5. Read Only Memory 6. Memory Decoding 7. Memory System Design for Microprocessors 8. Designing Larger Memories

Memories
To store a single bit, we can use
Flip Flops or Latches

Larger memories can be built by

Using a 2D array of these 1-bit devices
Horizontal expansion to increase word size Vertical expansion to increase number of words

Dynamic RAMs use a tiny capacitor to store a bit Design concepts are mostly independent of the actual technique used to store a bit of data

Flip-Flop 1-bit Register Semiconductor Memories

In all computer design, semiconductor memories are used as primary storage for code & data.
Connected directly to the CPU, they asked first by the CPU for information (code and data).
Referred to as primary memory.
D SET CLK CLR Q Q

Qn+1 = Dn D: Senkron veri girii CLK: Saat girii Q: k Q: kn tersi SET: Asenkron 1'leme girii CLR: Asenkron 0'lama girii

Primary memory must respond fast to the CPU.

Only semiconductor memories can do that
Among the most widely used are ROM and RAM.

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Clock Pulse

Flip-Flop and Latch Triggering Symbols

ndeki Kenar

Takip eden Kenar

D CLK

D CLK

D CLK

D CLK

0 (a) t

ndeki Kenar (b)

Takip eden Kenar

(a)

(b)

(c)

(d)

(a) Positive clock pulse, (b) negative clock pulse.

(a) Positive edge triggered, (b) negative edge triggered, (c) positive level triggered, (d) negative level triggered

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m-bit Register
1. Memory Basics
Giri Veri Yolu CLK Dm-1 D CLK CLK Dm-2 D CLK D0 D

Lecture Outline
2. Memory Design with D Flip Flops
3. Random Access Memory 4. DRAM 5. Read Only Memory 6. Memory Decoding
k Veri Yolu Q

Memory Design with D Flip Flops

An example
4x3 memory design Uses 12 D flip flops in a 2D array Uses a 2-to-4 decoder to select a row (i.e. a word) Multiplexers are used to gate the appropriate output A single WRITE (WR) is used to serve as a write and read signal
zero is used to indicate write operation one is used for read operation

Two address lines are needed to select one of four words of 3 bits each
15 16

Q Qm-1

Q Qm-2

7. Memory System Design for Microprocessors 8. Designing Larger Memories

Q0

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14

Memory Design with D Flip Flops (contd)

Common Bus Problem Memory Design with D Flip Flops (contd)

Problems with the design
Requires separate data in and out lines
Cannot use the bidirectional data bus
Q1 Giri k Giri Q2 k Vcc

(a) Logic diagram of a standard TTL inverter with totem pole output and its internal structure (b). (c) logic diagram of improper connection.

Cannot use this design as a building block to design larger memories

To do this, we need a chip select input

(a)
Vcc

(b)
Vcc

(d) short circuit of two inverters with outputs connected;

We need techniques to connect multiple devices to a bus

17

Uygun olmayan balant

A B

ON A OFF

OFF Q1 B ON
Q2

(c)

(d)

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Techniques to Connect to a Bus

Three techniques
Use multiplexers
Example We used multiplexers in the last memory design We cannot use MUXs to support bidirectional buses

Techniques to Connect to a Bus (contd)

Open collector technique

Use open collector outputs

Special devices that facilitate connection of several outputs together

Use tri-state buffers

Most commonly used devices

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Techniques to Connect to a Bus (contd)

Open collector register chip

Techniques to Connect to a Bus (contd)

Tri-State Buffers

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Tri-State Buffer

m-bit Register having 3-state outputs

Giri Veri Yolu CLK

Dm-1 D CLK CLK

Dm-2 D CLK

D0 D

E Y = X, E = 1 ise (a)

E Y = X, E = 0 ise (b)

E Y = X, E = 1 ise (c)

E Y = X, E = 0 ise (d)

Q Qm-1 E

Q Qm-2

Q Q0 3-durumlu k Veri Yolu

3-state buffers with noninverting (a), (b) and inverting (c), (d) outputs.

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Techniques to Connect to a Bus (contd)

Two example tri-state buffer chips

Techniques to Connect to a Bus (contd)

8-bit tri-state register

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26

8-bit (octal) Registers having 3-state outputs Building a Memory Block with 3-state Buffers

D 8-bit D

D 8-bit 8-bit D

8-bit
7

Q OE

Q OE

A 4 X 3 memory design using D flip-flops

CLK

CLK

Giri k Kontrol Kontrol (a)

Giri k Kontrol Kontrol (b)

27

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Building a Memory Block (contd)

Block diagram representation of a 4x3 memory

Building Larger Memories: 2 x 16-bit Register File

2 X 16 memory module using 74373 chips

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Memory

Organization

Memory Address Bits and Memory Capacity

Each memory IC chip contains 2x locations, where x is the number of chip address pins.
Each location contains y bits, where y is the number of data pins on the chip.

Memory chips are organized into a number of locations within the IC.
Each can hold 1, 4, 8, or even 16 bits.
Depending on internal design.

The number of bits each location can hold is always equal to the number of data pins on the chip. The number of locations in a memory chip depends on the number of address pins.
Always 2x, where x is the number of address pins.

The entire chip contains 2x x y bits, where x is the number of address pins and y the number of data pins.
The 2x x y is referred to as the organization of the memory chip, with x expressed as the number of address pins, and y the number of data pins.

210 = 1024 = 1K. (Kilo = 1000. 1 Kilobyte)

Note that in common speech, 1K is 1000, but in computer terminology it is 1024. See Table 10-1.
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Memory Capacities and Number of Bits Required for Addressing

1. Memory Basics
Memory Capacity 1K 2K 4K 8K 16K 32K 64K 128K 256K 512K 1M 16M 1G 4G 1T Number of Words 1024 2048 4096 8192 16384 32768 65536 2 64K 4 64K 8 64K 1024 1024 (16 64K) 16 1M 1024 1024 1024 4 1G 1024 1024 1024 1024 Bits 10-bit 11-bit 12-bit 13-bit 14-bit 15-bit 16-bit 17-bit 18-bit 19-bit 20-bit 24-bit 30-bit 32-bit 40-bit
33 34

2. Memory Design with D Flip Flops

3. Random Access Memory

4. DRAM 5. Read Only Memory 6. Memory Decoding 7. Memory System Design for Microprocessors 8. Designing Larger Memories

RAM: Random Access Memory RAM memory is called volatile memory since cutting off the power to the IC will mean the loss of data.
Sometimes referred to as RWM (Read & Write Memory).

SRAM Storage cells in static RAM memory are made of flip-flops & do not require refreshing to keep data. Each cell requires at least 6 transistors to build.
Each cell holds only 1 bit of data.
Recently 4-transistor cells have been made, still too many.

There are three types of RAM:

Static RAM (SRAM) Dynamic RAM (DRAM) NV-RAM (nonvolatile RAM)

4-transistor cells, plus use of CMOS technology has given led to a high-capacity SRAM.
Still far below DRAM capacity.

Table in the next slide shows some examples of SRAM.

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36

Static R/W Memory (RAM)

SRAM Examples Memory 2115A 2147H 51C67 2114A 6168 6116 6264 62128 62256 Capacity 1K 1 4K 1 16K 1 1K 4 4K 4 2K 8 8K 8 16K 8 32K 8 Pin Number 16 18 20 18 20 24 28 28 28 Control Lines CS, WE CS, WE CS, WE CS, WE CS, WE CS, WE, OE CS, WE, OE CS, WE, OE CS, WE, OE I/O Type Separate Separate Separate Common Common Common Common Common Common

A Simple SRAM Example:

6116 Pinouts

6116 has a capacity of 2K bits.

As indicated in the part number.

A0A10 are address inputs

Where 11 address lines gives 211 = 2K

I/O0I/O7 are for data I/O

8-bit data lines give 2K x 8 organization.

WE (write enable) is for writing data into SRAM. (active low) OE (output enable) is for reading data out of SRAM. (active low)
6116 2K x 8 SRAM
37

n-1

Adres n CS RD WR CS OE WE

Veri m

m-1

CS (chip select) is used to select the memory chip. (active low)

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SRAM 6116 diagram The functional block diagram for the 6116 SRAM

SRAM data write steps

1. Provide an address to pins A0A10. 2. Activate the CS pin. 3. Make WE = 0 while RD = 1. 4. Provide the data to pins I/O0I/O7. 5. Make CS = 1 and data will be written into SRAM on the positive edge of the CS signal.

6116 Functional Diagram

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Memory Write Timing for SRAM

6116 Functional Diagram

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SRAM data read steps

1. Provide the addresses to pins A0A10, the start of the access time (tAA). 2. Activate the CS pin. 3. While WE = 1, a high-to-low pulse on the OE pin will read the data out of the chip.

Memory Speed: Access Time A most important characteristic of a memory chip is the speed at which data can be accessed from it.
To access the data, the address is presented to the address pins, and after a certain amount of time has elapsed, the data shows up at the data pins.
The shorter this elapsed time, the better, (and more expensive) the memory chip.

The speed of the memory chip is commonly referred to as its access time.
Varies from a few nanoseconds to hundreds of nanoseconds.
Memory Read Timing for SRAM 6116 Functional Diagram
41 42

SRAM 6116 Access & Read Time

Access time, tAA, is measured as time elapsed from the moment an address is provided to the address pins to the moment data is available at the pins. Speed for the 6116 chip can vary from 100 ns to 15 ns.

SRAM 6116 Access & Read time

Read cycle time, tRC, is defined as the minimum amount of time required to read one byte of data, that is, from the moment the address of the byte is applied, to the moment the next read operation can begin.

100 ns - 15 ns
Memory Read Timing for SRAM Memory Read Timing for SRAM

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SRAM 6116 Access & Read Time

In SRAM for which tAA = 100 ns, tRC is also 100 ns, which implies the contents of consecutive addresses can be read with each taking no more than 100 ns, hence, in SRAM and ROM: tAA = tRC. 100 ns

Read and Write Timing Diagrams

Okuma evrimi Adres

Read Cycle
CS Veri k Geerli Veri

tA

Yazma evrimi Adres

CS WE Veri Girii Veri Deiebilir

Write Cycle
tw

100 ns
Memory Read Timing for SRAM

Veri Kararl

Veri Deiebilir

45 46

DRAM: Dynamic RAM

1. Memory Basics
2. Memory Design with D Flip Flops 3. Random Access Memory

In 1970, Intel Corporation introduced the first dynamic RAM.

Density (capacity) was 1024 bits.
It used a capacitor to store each bit.

4. DRAM
5. Read Only Memory 6. Memory Decoding 7. Memory Decoding 8. Memory System Design for Microprocessors 9. Designing Larger Memories

After the 1K-bit (1024) chip came the 4K-bit in 1973.

Advancing steadily, until the 256M DRAM chip in the 1990s.

Using a capacitor to store data reduces the total number of transistors needed to build the cell.
Use of capacitors as storage cells in DRAM results in a much smaller memory cell size.
They require constant refreshing due to leakage.

48 47

DRAM Advantages/Disadvantages and Terms Major advantages:

high density (capacity), cheaper cost lower power consumption per bit.

DRAM Packaging Issues It is difficult to pack large numbers of cells into single DRAM chips, with normal numbers of address pins.
A 64K-bit chip (64K x 1) must have 16 address lines and one data line, requiring 16 pins to send in the address.
In addition to VCC power, ground & read/write control pins.

Disadvantages:
It must be refreshed periodically, as the capacitor cell loses its charge. While it is being refreshed, the data cannot be accessed.

Multiplexing/demultiplexing reduces the number of pins.

Addresses are split & each half is sent through the same pins.

When referring to IC memory chips, capacity is always assumed to be in bits.

A 1G chip means a 1-gigabit chip and a 256M chip means a 256M-bit chip.
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Internally, the DRAM structure is divided into a square of rows and columns.
The first half of the address is called the row. The second half is called the column.
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DRAM Packaging Issues In a 64K x 1 organization, the first half of the address is sent through pins A0A7.
Internal latches grab the first half.
Using RAS (row address strobe)

DRAM Packaging Issues There must be a 2-by-1 multiplexer outside the DRAM chip, which has its own internal demultiplexer.
To access a bit of data from, both row & column address must be provided.

The second address half is sent through the same pins

Activating CAS (column address strobe), latches the second half.

The WE (write enable) pin is for read and write actions.

8 address pins, plus RAS & CAS make a total of 10 pins

Instead of 16, without multiplexing.
256K 1 DRAM
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256K 1 DRAM
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DRAM, SRAM, ROM Organizations Organizations for SRAMs & ROMs are always x 8.
DRAM can have x 1, x 4, x 8, or x 16 organizations.

NV-RAM: Nonvolatile RAM Nonvolatile RAM allows the CPU to read & write to it & when power is turned off, contents are not lost. NV-RAM chip internal components:
1. Extremely power-efficient (low power consumption) SRAM cells, built out of CMOS. 2. Internal lithium battery as a backup energy source. 3. Intelligent control circuitry.
To monitor the VCC pin, and automatically switch to the lithium battery on for loss of external power.

In some memory chips (notably SRAM), the data pins are called I/O.
In some DRAMs, there are separate pins Din and Dout.
DRAMs with x1 organization are widely used for parity bit.

NV-RAM is used to save x86 PC system setup.

Commonly referred to as CMOS RAM.

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ROM Read-Only Memory

1. Memory Basics 2. Memory Design with D Flip Flops 3. Random Access Memory 4. DRAM

ROM is a type of memory that does not lose its contents when the power is turned off.
Also called nonvolatile memory.

5. Read Only Memory

6. Memory Decoding 7. Memory System Design for Microprocessors 8. Designing Larger Memories

There are different types of read-only memory:

PROM, EPROM, EEPROM, Flash ROM, and mask ROM.

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PROM programmable ROM or OTP ROM PROM refers to the kind of ROM that the user can burn information into.
A user-programmable memory.

EPROM: Erasable Programmable ROM EPROM was invented to allow changes in the contents of PROM after it is burned.
One can program/erase the memory chip many times.

The programming process is called burning, using special equipment. (A ROM burner or programmer) For every bit of the PROM, there exists a fuse.
PROM is programmed by blowing the fuses. If information burned into PROM is wrong, it must be discarded, as the internal fuses are blown permanently. For this reason, PROM is also referred to as OTP. (one-time programmable)
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All EPROM chips have a window, to shine ultraviolet (UV) radiation to erase the chip's contents.
EPROM is also referred to as UV-erasable EPROM or simply UV-EPROM. Erasing EPROM contents can take up to 20 minutes. It cannot be programmed while in the system board (motherboard).
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Useful during prototyping of a microprocessorbased projects.

EPROM (Erasable Programmable Read Only Memory )

5V 5V 5V 6 V 12.5 V

An EPROM Chip: 2764

Programlama Darbesi Yazlacak Veri 8

Vcc Vpp PGM A13 - A0 14 D7 - D0

Dar Okunan Veri 8 14

Vcc Vpp PGM A13 - A0 D7 - D 0

27128 16K x 8 CE OE (a)

27128 16K x 8 CE OE (b)

CS RD

0V 5V

Note the A0A12 address pins and O0O7 (output) for D0D7 data pins.
OE (out enable) is for the read signal.
I/O Type Common Common Common Common Common Common 60

EPROM Examples Memory 2716 2732A 2764A 27128A 27256 27512 Capacity 2K 8 4K 8 8K 8 16K 8 32K 8 64K 8 Pin Number 24 24 28 28 28 28 Control Lines CE, OE CE, OE CE, OE CE, OE CE, OE CE, OE

Fig. 10-1 UV-EPROM Chip

A Simple EPROM Programmer

EPROM Programming Steps 1. Erase the contents.

Remove it from its system board socket, and use EPROM erasure equipment to expose it to UV radiation.

2. Program the chip.

To burn code & data into EPROM, the ROM burner uses 12.5 volts or higher, (called VPP), depending on type.
EEPROM with VPP of 57 V is available, but it is more expensive.

3. Replace the chip in its socket.

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Fig. 10-1 UV-EPROM Chip

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Flash Memory Since the early 1990s, Flash ROM has become a popular user-programmable memory chip.
The process of erasure of the entire contents takes only a few seconds. (In a flash, hence the name) Electrical erasure lends the nickname Flash EEPROM.
To avoid confusion, it is commonly called Flash ROM.

Flash Memory Because Flash ROM can be programmed while in its system board socket, it is widely used to upgrade PC BIOS ROM, or Cisco router operating systems.
Some designers believe that Flash memory will replace the hard disk as a mass storage medium.

When Flash memory's contents are erased the entire device is erased.
In contrast to EEPROM, where one sections or bytes. Some Flash memories recently available are divided into blocks, and erasure can be done by block.
No byte erasure option is yet available.
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The program/erase cycle is 500,000 for Flash and EEPROM; 2000 for UV-EPROM; infinite for RAM & disks.
Program/erase cycle is the number of times a chip can be erased and programmed before it becomes unusable.

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Memory Identification

Memory Identification Capacity of the memory chip is indicated in the part number, with access time given with a zero dropped.
27128-20 refers to UV-EPROM that has a capacity of 128K bits and access time of 200 nanoseconds.

See the entire table on page 259 of your textbook.

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See the entire table on page 259 of your textbook.

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Memory Identification In part numbers, C refers to CMOS technology.

27xx is for UV-E PROM 28xx for EEPROM.

Mask ROM Mask ROM refers to a kind of ROM whose contents are programmed by the IC manufacturer.
Not a user-programmable ROM. The terminology mask is used in IC fabrication.

Mask ROM is used when needed volume is high & it is absolutely certain the contents will not change.
Since the process is costly.

The cost is significantly cheaper than other kinds of ROM, but if an error in the data is found, the entire batch must be discarded.
See the entire table on page 259 of your textbook.
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Simple Logic Gate as Address Decoder

1. Memory Basics 2. Memory Design with D Flip Flops 3. Random Access Memory 4. DRAM 5. Read Only Memory

Current system designs use CPLDs. (complex programmable logic devices)

Memory & address decoding circuitry are integrated into one programmable chip. A task which can be performed with common logic gates.
NAND and 74LS138 chips act as decoders.

6. Memory Decoding
7. Memory System Design for Microprocessors 8. Designing Larger Memories

70 69

Simple Logic Gate as Address Decoder In connecting a memory chip to the CPU, the data bus is connected directly to the data pins of the memory.
Control signals MEMR & MEMW are connected to the OE & WR pins.

MEMORY ADDRESS DECODING simple logic gate as address decoder On the address buses, the lower bits of the address go directly to memory chip address pins.
The upper ones activate the CS pin of the memory chip.
CS pin, with RD/WR allows data flow in/out of the chip.

No data can be written into or read from the memory chip unless CS is activated.

CS input is active-low and can be activated using simple logic gates, such as NAND and inverters.
For every block of memory, we need a NAND gate.
See Figs. 10-9 & 10-10 on page 266.
Fig. 10-8 Using Simple Logic Gate as Decoder
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MEMORY ADDRESS DECODING simple logic gate as address decoder Example 10-6 shows the address range calculation for Fig. 10-10 on page 266.
Note the output of the NAND gate is active-low.
The CS pin is also active-low .

Using the 74LS138 as Decoder In the absence of CPLD or FPGA as address decoders, the 74LS138 chip is an excellent choice.
Three inputs: A, B & C, generate eight active-low outputs: Y0Y7.

74LS138 Decoder
73 74

The 3-to-8 Line Decoder (74LS138)

MEMORY ADDRESS DECODING using the 74LS138 as decoder The need for NAND and inverter gates is eliminated when using 74SL138.
Three inputs: A, B & C, generate eight active-low outputs: Y0Y7.

Each Y output connects to the CS of a memory chip, allowing control of 8 memory blocks by a single 74LS138.

Note that all three Enables (G2A, G2B, and G1) must be active, e.g. low, low and high, respectively. Each output of the decoder can be attached directly to CS or CE pin of an EPROM or RAM chip.

74LS138 Decoder
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MEMORY ADDRESS DECODING using the 74LS138 as decoder To enable 74SL138: G2A = 0, G2B = 0, G1 = 1.
G2A & G2B are grounded; G1 = 1 selects this 74LS138.
Three inputs: A, B & C, generate eight active-low outputs: Y0Y7.

1. Memory Basics 2. Memory Design with D Flip Flops 3. Random Access Memory 4. DRAM

Each Y output connects to the CS of a memory chip, allowing control of 8 memory blocks by a single 74LS138. Inputs G2A, G2B & G1, can be used for address or control signal selection

5. Read Only Memory 6. Memory Decoding

7. Memory System Design for Microprocessors

8. Designing Larger Memories

74LS138 Decoder
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Memory System Design

Memory Address Decoding

The processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip. In order to splice a memory device into the address space of the processor, decoding is necessary. For example, the 8088 issues 20-bit addresses for a total of 1MB of memory address space. However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins. A decoder can be used to decode the additional 9 address pins and allow the EPROM to be placed in any 2KB section of the 1MB address space.

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To design a memory system for a microprocessor based system: The lengths of memory bus and address bus of the microprocessor used. The starting address of microprocessor reset where the program execution starts. The control lines that the microprocessor uses in memory access. ..

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Data Transfer Between Registers

Kaynak Saklayclar
D CLK W RDW WRM Q

Timing Diagram for Two Successive Data Transfers

Birinci evrim
A Okuma Adresi
1 1 0 1 0 0 1 1 0 1 0 0 1

Hedef Saklayclar
D CLK M Q

kinci evrim

D CLK X

Q WRN

D CLK WDX

D CLK Y

1-bit tekynl Veri Yolu

B
Q

D CLK WRO

Use of three-state buffers to share data bus lines

Yazma Adresi B

RDY

D CLK Z

Q WRP

D CLK RDZ P

RD

0 1

WR

0 1

2x4 Decoder A 1 A
0

2x4 Decoder RDW RDX RDY RDZ Sadece bir k aktif dk B B

1 0

1B 1A 1G

1Y0 1Y1 1Y2 1Y3

2B 2A 2G

2Y0 2Y1 2Y2 2Y3

WRM WRN WRO WRP

WRP

0 1

Veri yolundaki 1-bit verinin tutturulma anlar

RD

WR

WRO

0 1 0

Adres A A
1

Seilen Saklayc W X Y Z

Adres B B
1

Yksek empedans

Seilen Saklayc M N O P

VER

0 0 1 1

0 1 0 1

0 0 1 1

0 1 0 1

1 veya 0

(Y)

(P)

(X)

(O)

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Memory System Design Steps

1. Estimate the amount of ROM and RWM required for the application. 2. Determine the address boundaries of each type of memory. Draw an initial memory map. 3. Select the memory devices to be used. 4. Determine the arrangement of memory devices necessary to provide the required word length and number of words. Draw the detailed memory map. 5. Design the address decoding logic. 6. Determine the buffering required, if any. 7. Determine the required speed of the memory devices.
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Basic 4 Data Transfers of a Microprocessor

Intel control signals for basic microprocessor data transfers: RD: Read (active low) WR: Write (active low) IO / M: Input Output / Memory
Data transfers between a microprocessor and memory and I/O devices Data Transfer I M I M I IO I IO RD 0 1 0 1 WR 1 0 1 0 IO/M 0 0 1 1 Cycle MEMR MEMW IOR IOW Comment Memory read Memory write I/O read I/O write

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A Memory Design Example for 8085 Microprocessor

A Simple Memory System Design Example

4K8 EPROM ve 2K8 RWM EPROM starts from 0000h, after EPROM RWM starts.
A15 A 12 A11 A8 A7 A4 A3 A0

8085 signals which will be used in the memory system design: 16-bit Address Bus, A15-A0, 8-bit Data Bus, D7-D0, 3 control lines, IO.H/M.L , RD.L and WR.L

0000h ROM 0FFFh 1000h 17FFh 1800h 4K

0000h 0FFFh

0 0 0 0 0 0 0 0
lk 4K'lk blou seer

0 0 0 0 1 1 1 1

0 0 0 0 1 1 1 1
4K ROM iinde bir hafza hcresini seer

0 0 0 0 1 1 1 1

RWM

2K

1000h 17FFh

0 0 0 1 0 0 0 1

0 0 0 0 0 1 1 1

0 0 0 0 1 1 1 1
2K RWM iinde bir hafza hcresini seer

0 0 0 0 1 1 1 1

FFFFh

Bo

nc 2K'lk blou seer

58K

Address bit map

Memory map
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A Design Using Full Decoding

D7 - D0 Veri Yolu A11 - A0 12 A11 - A0 D7 - D0

Another Design Using Partial Decoding

2732 4K x 8 EPROM CE OE

74LS138 A13 A12 A11 C B A Y0 Y1 Y2 Y3 Y4 A15 IO / M A14 G2A G2B G1 Y5 Y6 Y7

07FFh-0000h 0FFFh-0800h 17FFh-1000h

RD

A10 - A0 11

A11 - A0

D7 - D0

6116 2K x 8 RWM CS OE WE
87 88

RD WR

1. Memory Basics 2. Memory Design with D Flip Flops 3. Random Access Memory 4. DRAM 5. Read Only Memory 6. Memory Decoding

Designing Larger Memories

Issues involved
Selection of a memory chip
Example: To design a 64M X 32 memory, we could use Eight 64M X 4 in 1 X 8 array (i.e., single row) Eight 32M X 8 in 2 X 4 array Eight 16M X 16 in 4 X 2 array

7. Memory System Design for Microprocessors

Designing M X N memory with D X W chips

Number of chips = M.N/D.W Number of rows = M/D Number of columns = N/W
89 90

8. Designing Larger Memories

Designing Larger Memories (contd)

64M X 32 memory using 16M X 16 chips

Designing Larger Memories (contd)

Design is simplified by partitioning the address lines (M X N memory with D X W memory chips)
Z bits are not connected (Z = log2(N/8)) Y bits are connected to all chips (Y = log2D) X remaining bits are used to map the memory block
Used to generate chip selects

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Memory Mapping
Full mapping

Memory Mapping (contd)

Partial mapping

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Alignment of Data

Alignment of Data (contd)

Alignment
2-byte data: Even address
Rightmost address bit should be zero

4-byte data: Address that is multiple of 4

Rightmost 2 bits should be zero

8-byte data: Address that is multiple of 8

Rightmost 3 bits should be zero

Soft alignment
Can handle aligned as well as unaligned data

Hard alignment
Handles only aligned data (enforces alignment)
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Interleaved Memory
In our memory designs
Block of contiguous memory addresses is mapped to a module
One advantage Incremental expansion Disadvantage Successive accesses take more time Not possible to hide memory latency

Interleaved Memory (contd)

The n-bit address is divided into two r and m bits: n=r+m Normal memory
Higher order r bits identify a module Lower order m bits identify a location in the module
Called high-order interleaving

Interleaved memories
Improve access performance
Allow overlapped memory access Use multiple banks and access all banks simultaneously Addresses are spread over banks Not mapped to a single memory module

Interleaved memory
Lower order r bits identify a module Higher order m bits identify a location in the module
Called low-order interleaving

Memory modules are referred to as memory banks

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Interleaved Memory (contd)

Interleaved Memory (contd)

Two possible implementations
Synchronized access organization
Upper m bits are presented to all banks simultaneously Data are latched into output registers (MDR) During the data transfer, next m bits are presented to initiate the next cycle

Independent access organization

Synchronized design does not efficiently support access to non-sequential access patterns Allows pipelined access even for arbitrary addresses Each memory bank has a memory address register (MAR) No need for MDR
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Interleaved Memory (contd)

Synchronized access organization

Interleaved Memory (contd)

Interleaved memory allows pipelined access to memory

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Interleaved Memory (contd)

Independent access organization

Interleaved Memory (contd)

Number of banks
M = memory access time in cycles To provide one word per cycle
Number of banks M

Drawbacks of interleaved memory

Involves complex design
Example: Need MDR or MAR

Reduced fault-tolerance
One bank failure leads to failure of the whole memory

Cannot be expanded incrementally

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Acknowledgement
The slides have been based in-part upon original slides of a number of books including: The x86 PC: Assembly Language, Design, and Interfacing, 5/E, M. A. Mazidi, J. G. Mazidi, D. Causey, Prentice Hall, 2010. Fundamentals of Computer Organization and Design, S. P. Dandamudi, Springer, 1060 pages, 2003. Mikroilemciler ve Bilgisayarlar, 6. Basm, H. Gmkaya, ALFA, 2011.

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