University of North Florida Electrical Engineering Program

EEE4309C- Electronic Circuits II Spring 2014 Instructor: Juan Aceros

Lab #1: Common Emitter Amplifier

Lab preformed on February 4, 2014 Lab report due on February 18, 2014

Completed by: Elizabeth Voelkel N00836576 Dawn Owens N00152181

Abstract This lab introduced designing a common emitter amplifier to desired parameters. The objective of the lab was to understand the characteristics of each component and to design, construct, and test a BJT common emitter amplifier that met the minimum parameters, and followed the operating specifications for a 2N222A transistor. 1. Equipment Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Quantity 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 Description Computer iPhone O/S Multisim O/S Word Processor Oscilloscope Digital Multi-Meter Breadboard Banana to Alligator Test Leads Oscilloscope Probe Bipolar Junction Transistor Electrolytic Capacitors Jumper Wires Function Generator Various Resistors Manufacturer HP Apple Apple National Instruments Microsoft Microsoft Tektronix Agilent E&L Instruments Tektronix BK Precision Model Number Pavilion g6 4S iOS 7.0.1 12.0 Windows 7 Word 2010 TDS 2014 34401A Cadet II 2N222A N/A 4003A -

Table 4.1 Equipment. 2. Design The common emitter amplifier consists of a single BJT circuit that takes a small signal as input and amplifies it with minimal distortion. Figure 1 shows the constructed circuit based on the following design parameters: 1. 2. 3. 4. 5. 6. 7. Use a 2N2222A BJT and a 12 V DC power supply. A midband voltage gain AV 50. A low cutoff frequency fL between 100 Hz and 300 Hz. An input impedance 1k. A vO symmetric swing 2.0 Vpeak. A load resistor RL = 1.5 k A source resistance RS = 50

The starting point in designing this amplifier was to perform all the calculation aiming for a higher gain (75-100) than the minimum requirement. The following BJT values were assumed in accordance with those listed in MultiSim: VBE = 750 mV, = 220, IC=2mA. The combination of the desired parameters and assumption yielded the component values shown in Table 4.2 and Common Emitter BJT Amplifier shown in Figure 4.1. Component Given Calculated R1 3.3k R2 230 RC 1.5k RE1 10 RE2 10 CC1 2.2F CC2 0.22F CE 1000 F RL 1.5k RS 50 Table 4.2. Common Emitter BJT Amplifier

Figure 4.1. Common Emitter BJT Amplifier Circuit

Figure 4.2. Common Emitter BJT Amplifier Circuit VBE (671 mV) and VCE (4.02V).

Figure 4.3. Common Emitter BJT Amplifier Frequency Analysis 3. Procedure 3.1 Building CE Amplifier and Specification Verification The circuit shown in Figure 4.3 was constructed using the PB-505 breadboard. The input voltage was measured from the source using Channel One on the oscilloscope. With a 1.5k load resistor connected to the CE Amplifier the output voltage across the resistor was measured using the oscilloscope, this waveform was recorded. Measured the Q-Point, midband voltage gain, and peak symmetric output voltage swing.

Figure 4.4. Common Emitter Amplifier. 3.2 Loading Effect. Using the same circuit shown in Figure 4.2 RL is replaced with 150 resistor then a 15 k resistor, so the loading affect could be observed. 3.3 Frequency Response. Replaced RL with the 1.5 k, the frequency is gradually increased, to observe the relationship between the input and output voltage. 3.4 Input and Output Impedance. Measured the input impedance as seen by the source, using the Agilent multimeter voltage across and current running through RS was measured. Measured the output impedance seen by the load resistor, using the Agilent multimeter voltage across and current running through RL was measured. 3.5 CE Adjustment Placed CE in parallel with RE2 then placed RC circuit in series with RE1. Measured the Q-point and midband voltage gain.

3.5 Adjusted CE analysis Steps 3.2-3.4 were repeated using the circuit built in step 3.5. 3.6 Removal of CE Removed CE and measured the Q-point and midband voltage gain. 3.6 Removal of CE analysis Steps 3.2-3.4 were repeated using the circuit built in step 3.6.

4. Results 4.1 Results From Procedure 3.1 Building CE Amplifier and Specification Verification The signal is slightly distorted, but as the frequency is increased the signal becomes less distorted. Table 4.3 display the measurements obtained during verification of desired specification. Figure 4.5 shows the ratio of the input voltage to the output voltage, and is tabulated in Table 4.4. Q-Point Data Vbe 0.649 Vce (V) 5.13 AM 65 fL 400 Table 4. 3 Q-Point Data

Figure 4.5 Input and Output Waveform Input Voltage Output Voltage 20log(Av) (V) (V) Gain (1.8kHz) (dB) 0.05 3.62 72.4 37.19477132 Table 4.4 Common Emitter Amplifier Gain

4.3 Results from Procedure 3.2 Loading Effect. As seen in Table 4.5, decreasing the load resistor decreases the gain, and increasing the load resistor increase the gain. Figures 4.6 and 4.7 show the ratio of the input and output voltage waveforms for the varied load resistance. Load Resistance Input Voltage Output Voltage () (V) (V) Gain 20log(Av) 15000 0.047 5.46 116.1702128 41.3018957 150 0.05 0.9 18 25.1054501 Table 4.5 Gain for various size load resistors.

Figure 4.6 Input and Output Waveform with RL = 15,000

Figure 4.7 Input and Output Waveform with RL = 150

4.3 Results from Procedure 3.3 Frequency Response. Results from the frequency analysis are shown in Table 4.6. Figure 4.8 shows the frequency response of the CE Amplifier. Input Voltage Output Voltage 20log(Av) Frequency (Hz) (V) (V) Gain (dB) 25 0.05 1.00E-01 2 6.020599913 30 0.05 0.148 2.96 9.425834221 45 0.05 0.216 4.32 12.70967494 55 0.05 0.26 5.2 14.32006687 60 0.05 0.288 5.76 15.20844967 70 0.05 0.368 7.36 17.33755629 80 0.05 0.412 8.24 18.31854423 90 0.05 0.53 10.6 20.50611731 101 0.1 1.56 15.6 23.86249197 125 0.1 2.02 20.2 26.10702739 150 0.1 2.62 26.2 28.36602583 175 0.1 3.24 32.4 30.2109002 200 0.1 3.64 36.4 31.22202767 228 0.1 4.04 40.4 32.1276273 252 0.1 4.44 44.4 32.9476594 277 0.1 4.68 46.8 33.40491706 302 0.1 5.1 51 34.15140352 325 0.1 5.22 52.2 34.35341006 382 0.1 6 60 35.56302501 4.00E+02 0.1 6.5 65 36.25826713 4.52E+02 0.1 6.7 67 36.52149605 7.00E+02 0.1 7 70 36.9019608 1.00E+03 0.1 7 70 36.9019608 2.50E+04 0.1 6.98 69.8 36.87710845 3.30E+04 0.1 7.1 71 37.02516697 1.56E+05 0.11 7.4 67.27272727 36.55678069 2.52E+05 0.108 7.3 67.59259259 36.59798209 4.20E+05 0.106 7.2 67.9245283 36.64053262 7.50E+05 0.106 6.9 65.09433962 36.27086451 8.55E+05 0.106 6.8 64.1509434 36.14406095 1.00E+06 0.108 6.6 61.11111111 35.7224036 Table 4.6 Frequency Response Data

Frequency (Hz)
40 35 30

20log(A) (dB)

25 20 15 10 5 0 20 200 2000 Frequency (Hz) 20000 200000

Figure 4.8 Frequency Response Plot 4.4 Results from Procedure 3.4 Input and Output Impedance. Table 4.7 shows the measured input and output impedance. INPUT I,Rs 1.00E-06 V,Rs 1.98E-03 Z 1983 OUTPUT Isc 8.00E-06 Voc 1.50E-02 Z 1875 Table 4.7. Input and Output Impedance 4.5 Results from Procedure 3.5 CE Adjustment Qpoint Data New VBE 0.621 New VCE 2.66 Av 36 Table 4.8. Q Point Data

RL Voutpp Gain 1.5k 7.6 29.6875 150 0.254 5.08 15k 10 40 Table 4.9 Load Affect Input Voltage Output Voltage (V) (V) Gain 0.1 1.02 0.1 1.24 0.1 1.48 0.1 2.08 0.1 2.78 0.1 3.32 0.1 3.76 0.1 3.94 0.1 4.12 0.1 4.28 0.1 4.54 0.1 4.6 0.1 5.12 0.1 5.2 0.1 5.14 0.1 5.68 0.1 5.76 0.1 5.72 0.1 5.64 0.1 5.56 Table 4.10 Frequency Response 20log(Av) (dB) 20.17200344 21.8684337 23.40523431 26.3612667 28.88089592 30.42276167 31.5037569 31.90992444 32.29794432 32.62887538 33.14111706 33.25515663 34.18539922 34.32006687 34.21926238 35.08696671 35.20844967 35.14792058 35.02558208 34.90149583

Frequency (Hz) 50 60 71.2 102 151 201 260 300 350 426 734 1000 2100 4000 9000 17000 28000 40000 124000 300000

10.2 12.4 14.8 20.8 27.8 33.2 37.6 39.4 41.2 42.8 45.4 46 51.2 52 51.4 56.8 57.6 57.2 56.4 55.6

Frequency (Hz)
40 35 30 20log(A) (dB) 25 20 15 10 5 0 20 200 2000 Frequency (Hz) 20000 200000

Figure 4.9. Frequency Response Plot

INPUT I,Rs 2.20E-06 V,Rs 1.50E-03 Z 6.82E+02 OUTPUT Isc 3.50E-06 Voc 6.00E-03 Z 1714.286 Table 4.11 Input and Output Impedance 4.6 Results from Procedure 3.7 CE Removed Qpoint Data Vbe 0.62 Vce 4.5 Av 32.61 Table 4.12 Q Point Data

RL Voutpp Gain 1.5k 2.12 21.2 150 0.64 6.4 15k 3.4 34 Table 4.13 Load Affect Input Voltage Output Voltage Frequency (Hz) (V) (V) Gain 50 0.1 0.24 60 0.1 0.26 70 0.1 0.34 100 0.1 0.46 151 0.1 0.5 201 0.1 0.52 260 0.1 0.668 300 0.1 0.75 350 0.1 0.79 426 0.1 0.8 734 0.1 0.95 1000 0.1 1 2100 0.1 1.32 4000 0.1 1.32 9000 0.1 1.32 17000 0.1 1.35 28000 0.1 1.35 40000 0.1 1.37 124000 0.1 1.39 300000 0.1 1.5 Table 4.14 Frequency Response 20log(Av) (dB) 7.604224834 8.299466959 10.62957834 13.25515663 13.97940009 14.32006687 16.49552925 17.50122527 17.95254183 18.06179974 19.55447211 20 22.41147862 22.41147862 22.41147862 22.60667537 22.60667537 22.73441134 22.86029601 23.52182518

2.4 2.6 3.4 4.6 5 5.2 6.68 7.5 7.9 8 9.5 10 13.2 13.2 13.2 13.5 13.5 13.7 13.9 15

Frequency (Hz)
25 20 20log(A) (dB) 15 10 5 0 20 200 2000 Frequency (Hz) 20000 200000

Figure 4.10 Frequency Response Plot

INPUT I,Rs 2.00E-06 V,Rs 5.00E-03 Z 2.50E+03 OUTPUT Isc 4.00E-06 Voc 3.20E-03 Z 800 Table 4.15 Input and Output Impedance 5. Questions 5.1 Compare the measurements in Lab Procedures steps 1-8 to the theoretical predictions obtained in the design simulation. Note how increasing the feedback affects the gain, bandwidth, and input and output impedances. When feedback is increased, an increase in gain and bandwidth is seen, while the input and ouput impedance is minimally affected. 5.2 How can the amount of feedback (gain) be varied using a potentiometer of a value equal to RE without affecting the Q-Point?

Using a potentiometer for RE with the wiper ac-grounded creates variable gain control. As the potentiometer is adjusted, more or less of is bypassed to ground, thus varying the gain. The total remains constant to DC, keeping the bias fixed. [2] 5.3 How can fH be reduced using external components? FH can be reduced by placing a coupling capacitor between the base and collector, which places a capacitor in parallel with the internal capacitance C. This increases the miller effect and decreases the high frequency cut off. 5.4 Why is the value of fH measured in the lab different from the value determined analytically or through simulation methods. Measured values in lab are affected by physical limitations of the components as well as the inconsistency of the input signal, as none of the components are ideal nor their sources.

6. Conclusion This laboratory exercise successfully demonstrated how important it is to study the common emitter amplifier. With this configuration, a small signal can be amplified accurately with gains of over 100. But designing this circuit to work correctly is not an easy task; the value of every component has to be calculated or assumed. This lab also provided an exposure to real life issues such as loading effect, component value variation and other non-ideal situations. References [1] J. Aceros, Lab 4: Common Emitter Amplifier UNF, Jacksonville, FL, EEL4309C Electronic Circuits II Lab Manual, January 2014. [2] Donald A. Neamen, Microelectronics Circuit Analysis and Design, Third Edition, McGrawHill, 2007.