The project Ultrasonic Distance Radar is a very interesting and useful project for many project applications.

In this project we have used the ultrasonic waves to measure the distance in between two points. The basic principal is based on the speed of ultrasonic waves in open air. Sensors are mount on the stepper motor bas platform. hen circuit is

on then motor moves in one direction and search the object . If the object is located then sensor provide a feedbac! and at the same time circuit count the step move by the stepper motor. "y counting the step of stepper motor we show the direction of the object e

have used a microcontroller #T$%S&' to transmit and receive ultrasonic waves through () *+, ultrasonic receiver and transmitters. "y measuring the time re-uired to travel the un!nown distance by ultrasonic waves in air we can find out the distance between two points. The distance measured is displayed on a ./D display. The transmission 0 reception of ultrasonic waves is very comple1 in nature so it needs very sophisticated techni-ues to process these waves. e have used a very comple1 structure of amplifier

and filters for this purpose. The speed of ultrasonic waves is dependent on temperature. So before using ultrasonic waves for any measurement we need to calibrate the speed of ultrasonic waves in current atmospheric temperature. 2or this purpose we have implemented a special algorithm to calibrate the speed of ultrasonic waves through a !nown distance of ')) /m. There are numerous applications of ultrasonic waves in instrumentation and control. These applications include measurement of distance3 speed3 flow etc. Ultrasonic also find many application in medical instrumentation.

8<) 5 #/

Step Down T42

2ull ave "ridge Rectifier

5oltage Regulator

;&5D/4&))m# ;%5D/48&)m#

'918 ./D

Display

/omparator 6sensitivity selector 7

:icrocontroller #T$%S&'

Driver /ircuit

Demodulator

/urrent #mplifier

#mplifier /ircuit 8ndstage

() *+, Ultrasonic Transmitter

#mplifier /ircuit 'st stage

() *+, Ultrasonic Receiver

In this project we combine two project. =ne is ultra sonic distance measurement and second is direction chec!er with the . In normal condition when we press the start switch then stepper motor is rotate. Stepper motor is connected to the port >'. >in no '383<3(. +ere we use bi?polar stepper motor to move in the cloc!wise direction and anticloc! wise direction :otor moves in any direction in steps. It ta!es a movement is steps. In one step it moves to '.$ degree3 there is lot of stepper motor available in the mar!et3 @ow in these days stepper motor easily available in the mar!et.

In this project we connect the stepper motor to the pin no '383<3( of the microcontroller. +ere we use $%s&' controller. $%s&' is a $)&' based controller. In the stepper motor there is four coil. To provide a voltage from the controller we connect two transistor circuit. =utput from the controller is firstly connected to the base of the >@> transistor via current limiting resistor. =utput from the controller is active low so firstly we provide a active low output to the base of the >@> transistor and output of the >@> transistor is connected to the base of the @>@ transistor. Amitter of the @>@ transistor connected to the ground pin and collector of the @>@ transistor is connected to the one coil of the stepper motor. +ere we use four coil stepper motor 3 so we use four series circuit of transistor to to the four coil of the

+ere in this project we use () !ht, transmitter . This () ! ht, fre-uency is generated by the microcontroller. e use one oscillation circuit; time

circuit to control the sending?out time of the ultrasonic pulse.

The circuit is the same as the ultrasonic range meter . The oscillation fre-uency is the same.

The inverter is used for the drive of the ultrasonic sensor. The two inverters are connected in parallel because of the transmission electric power increase. The phase with the voltage to apply to the positive terminal and the negative

terminal of the sensor has been '$) degrees shifted. "ecause it is cutting the direct current with the capacitor3 about twice of voltage of the inverter output are appied to the sensor. The ultrasonic signal which was received with the reception sensor is amplified by '))) times69)d"7 of voltage with the operational amplifier with two stages. It is ')) times at the first stage 6()d"7 and ') times 68)d"7 at the ne1t stage.. Benerally3 the positive and the negative power supply are used for the operational amplifier. The circuit this time wor!s with the single power supply of ;% 5. Therefore3 for the positive input of the operational amplifiers3 the half of the power supply voltage is applied as the bias voltage and it is made (.& 5 in the central voltage of the amplified alternating current signal. hen using the operational amplifier with the negative

feedbac!3 the voltage of the positive input terminal and the voltage of the negative input terminal become e-ual appro1imately. So3 by this bias voltage3 the side of the positive and the side of the negative of the alternating current signal can be e-ually amplified. hen not using this bias voltage3 hen the alternating

the distortion causes the alternating current signal.

current signal is amplified3 this way is used when wor!ing the operational

amplifier for the 8 power supply with the single power supply.

The detection is done to detect the received ultrasonic signal. It is the half? wave rectification circuit which used the Shott!y barrier diodes. The D/ voltage according to the level of the detection signal is gotten by the capacitor behind the diode. the Shott!y barrier diodes are used because the high fre-uency characteristic is good.

This circuit is the circuit which detects the ultrasonic which returned from the object. The output of the detection circuit is detected using the comparator. #t the circuit this time3 the operational amplifier of the single power supply is used instead of the comparator. The operational amplifier amplifies and outputs the difference between the positive input and the negative input.

In case of the operational amplifier which doesnCt have the negative feedbac!3 at a little input voltage3 the output becomes the saturation state. Benerally3 the operational amplifier has tens of thousands of times of mu factors. So3 when the positive input becomes higher a little than the negative input3 the difference is tens of thousands of times amplified and the output becomes the same as the power supply almost.6It is the saturation state7 =ppositely3 when the positive input becomes lower a little than the negative

input3 the difference is tens of thousands of times amplified and the output becomes ) 5 almost.6It is in the =22 condition7 This operation is the same as the operation of the comparator. +owever3 because the inner circuit is different about the comparator and the operational amplifier3 the comparator can not be used as the operational amplifier.

#t the circuit this time3 it connects the output of the detection circuit with the negative input of the signal detector and it ma!es the voltage of the positive input constant.

This circuit is the gate circuit to measure the time which is reflected with the object and returns after sending out the ultrasonic. It is using the SR 6the set and the reset7 flip?flop. 2or the details of SR?223 refer to The set condition is the time which begins to let out the ultrasonic with the transmitter. It uses the transmission timing pulse. The reset condition is the time which detected the signal with the signal detector of the receiver circuit. That is3 the time that the output of SR?22 6D7 is in the =@ condition becomes the time which returns after letting out the ultrasonic

The time that the sound wave goes and returns in the 40-cm distance hen the ambient temperature is 8)D/3 the propagation speed of the sound wave is <(<.& m4second. In the time to be propagated by $) cm 6the going and returning73 it is as follows. TS E ).$4<(<.& E ).))8<< E 2.33

milliseconds

The time that the sound wave goes and returns in the 10-m distance In the time to be propagated by 8) m 6the going and returning73 it is as follows.

T.

E 8)4<(<.& E ).)&$88 E 58.2

milliseconds

MIC !C!"T !##$ %T8&C51

%rchitecture o' 8051 'amil()-

The figure F ' above shows the basic architecture of $)&' family of microcontroller.
Features
G /ompatible with :/S?&'H >roducts G (* "ytes of In?System Reprogrammable 2lash :emory F AnduranceI '3))) rite4Arase /ycles G 2ully Static =perationI ) +, to 8( :+, G Three?.evel >rogram :emory .oc! G '8$ 1 $?"it Internal R#: G <8 >rogrammable I4= .ines G Two '9?"it Timer4/ounters G Si1 Interrupt Sources G >rogrammable Serial /hannel G .ow >ower Idle and >ower Down :odes

Description
The #T$%/&' is a low?power3 high?performance /:=S $?bit microcomputer with (* bytes of 2lash >rogrammable and Arasable Read =nly :emory 6>AR=:7. The device is manufactured using #tmels high density nonvolatile memory technology and is compatible with the industry standard :/S?&'H instruction set and pinout. The on?chip 2lash allows the program memory to be reprogrammed in?system or by a conventional nonvolatile memory programmer. "y combining a versatile $?bit />U with 2lash on a monolithic chip3 the #tmel #T$%/&' is a powerful microcomputer which provides a highly fle1ible and cost effective solution to many embedded control applications. The #T$%/&' provides the following standard featuresI (* bytes of 2lash3 '8$ bytes of R#:3 <8 I4= lines3 two '9?bit timer4counters3 five vector two?level interrupt architecture3 a full duple1 serial port3 and on?chip oscillator and cloc! circuitry. In addition3 the #T$%/&' is designed with static logic for operation down to ,ero fre-uency and supports two software selectable power saving modes. The Idle :ode stops the />U while allowing the R#:3 timer4counters3 serial port and interrupt system to continue functioning. The >ower down :ode saves the R#: contents but free,es the oscillator disabling all other chip functions until the ne1t hardware reset. *in +escri,tion -CC Supply voltage. ."+ Bround. *ort 0 >ort ) is an $?bit open drain bidirectional I4= port. #s an output port each pin can sin! eight TT. inputs. hen 's are written to port ) pins3 the pins can be used as high impedance inputs. >ort ) may also be configured to be the multiple1ed low order address4data bus during accesses to e1ternal program and data memory. In this mode >) has internal pull?ups. >ort ) also receives the code bytes during 2lash programming3 and outputs the code bytes during program verification.

A1ternal pull?ups are re-uired during program verification.

*ort 1 >ort ' is an $?bit bidirectional I4= port with internal pull?ups. The >ort ' output buffers can sin!4source four TT. inputs. hen 's are written to >ort ' pins they are pulled high by the internal pull?ups and can be used as inputs. #s inputs3 >ort ' pins that are e1ternally being pulled low will source current 6II.7 because of the internal pull?ups. >ort ' also receives the low?order address bytes during 2lash programming and verification. *ort 2 >ort 8 is an $?bit bidirectional I4= port with internal pull?ups. The >ort 8 output buffers can sin!4source four TT. inputs. hen 's are written to >ort 8 pins they are pulled high by the internal pull?ups and can be used as inputs. #s inputs3 >ort 8 pins that are e1ternally being pulled low will source current 6II.7 because of the internal pull?ups. >ort 8 emits the high?order address byte during fetches from e1ternal program memory and during accesses to e1ternal data memory that uses '9?bit addresses 6:=5J K D>TR7. In this application it uses strong internal pull?ups when emitting 's. During accesses to e1ternal data memory that uses $?bit addresses 6:=5J K RI7L >ort 8 emits the contents of the >8 Special 2unction Register. >ort 8 also receives the high?order address bits and some control signals during 2lash programming and verification. *ort 3 >ort < is an $?bit bidirectional I4= port with internal pull?ups. The >ort < output buffers can sin!4source four TT. inputs. hen 's are written to >ort < pins they are pulled high by the internal pull?ups and can be used as inputs. #s inputs3 >ort < pins that are e1ternally being pulled low will source current 6II.7 because of the pull?ups. >ort < also serves the functions of various special features of the #T$%/&' as listed belowI >ort < also receives some control signals for 2lash programming and verification. /T Reset input. # high on this pin for two machine cycles while the oscillator is running resets the device.

%#$0* !. #ddress .atch Anable output pulse for latching the low byte of the address during accesses to e1ternal memory. This pin is also the program pulse input 6>R=B7 during 2lash programming. In normal operation #.A is emitted at a constant rate of '49 the oscillator fre-uency3 and may be used for e1ternal timing or cloc!ing purposes. @ote3 however3 that one #.A pulse is s!ipped during each access to e1ternal Data :emory. If desired3 #.A operation can be disabled by setting bit ) of S2R location $A+. ith the bit set3 #.A is active only during a :=5J or :=5/ instruction. =therwise3 the pin is wea!ly pulled high. Setting the #.A?disable bit has no effect if the microcontroller is in e1ternal e1ecution mode. */$" >rogram Store Anable is the read strobe to e1ternal program memory. *ort *in %lternate 1unctions ><.) RJD 6serial input port7 ><.' TJD 6serial output port7 ><.8 I@T) 6e1ternal interrupt )7 ><.< I@T' 6e1ternal interrupt '7 ><.( T) 6timer ) e1ternal input7 ><.& T' 6timer ' e1ternal input7 ><.9 R 6e1ternal data memory write strobe7 ><.M RD 6e1ternal data memory read strobe7 hen the #T$%/&' is e1ecuting code from e1ternal program memory3 >SA@ is activated twice each machine cycle3 e1cept that two >SA@ activations are s!ipped during each access to e1ternal data memory. $%0-**

A1ternal #ccess Anable. A# must be strapped to B@D in order to enable the device to fetch code from e1ternal program memory locations starting at ))))+ up to 2222+. @ote3 however3 that if loc! bit ' is programmed3 A# will be internally latched on reset. A# should be strapped to 5// for internal program e1ecutions. This pin also receives the '8?volt programming enable voltage 65>>7 during 2lash programming3 for parts that re-uire '8?volt 5>>. 2T%#1 Input to the inverting oscillator amplifier and input to the internal cloc! operating circuit. 2T%#2 =utput from the inverting oscillator amplifier. !scillator Characteristics JT#.' and JT#.8 are the input and output3 respectively3 of an inverting amplifier which can be configured for use as an on?chip oscillator3 as shown in 2igure '. Aither a -uart, crystal or ceramic resonator may be used. To drive the device from an e1ternal cloc! source3 JT#.8 should be left unconnected while JT#.' is driven as shown in 2igure 8.There are no re-uirements on the duty cycle of the e1ternal cloc! signal3 since the input to the internal cloc!ing circuitry is through a divide?by?two flip?flop3 but minimum and ma1imum voltage high and low time specifications must be observed.

Idle Mode In idle mode3 the />U puts itself to sleep while all the on chip peripherals remain active. The mode is invo!ed by software. The content of the on?chip R#: and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled Interrupt or by hardware reset. It should be noted that when idle is terminated by a hard +ardware reset3 the device normally resumes program e1ecution3 from where it left off3 up to two machine cycles before the internal reset algorithm ta!es control. =n?chip hardware inhibits access to internal R#: in this event3 but access to the port pins is not inhibited. To eliminate the possibility of an une1pected write to a port pin when Idle is terminated by reset3 the instruction following the one that invo!es Idle should not be one that writes to a port pin or to e1ternal memory.

/tatus o' $3ternal *ins during Idle and *ower down Modes Mode *rogram Memor( %#$ */$" *! T0 *! T1 *! T2 *! T3 Idle Internal ' Data Idle A1ternal ' 2loat Data #ddress Data >ower down Internal ) Data >ower down A1ternal ) 2loat Data *ower down Mode In the power down mode the oscillator is stopped3 and the instruction that invo!es power down is the last instruction e1ecuted. The on?chip R#: and Special 2unction Registers retain their values until the power down mode is terminated. The only e1it from power down is a hardware reset. Reset redefines the S2Rs but does not change the on?chip R#:. The reset should not be activated before 5// is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabili,e. *rogram Memor( #oc4 5its =n the chip are three loc! bits which can be left un?programmed 6U7 or can be programmed 6>7 to obtain the additional features listed in the table belowI hen loc! bit ' is programmed3 the logic level at the A# pin is sampled and latched during reset. If the device is powered up without a reset3 the latch initiali,es to a random value3 and holds that value until reset is activated. It is necessary that the latched value of A# be in agreement with The current logic level at that pin in order for the device to function properly. #oc4 5it *rotection Modes *rogram #oc4 5its *rotection T(,e #51 #52 #53 ' U @o program loc! features. 8 > U :=5/ instructions e1ecuted from e1ternal program memory are disabled from fetching code

"ytes from internal memory3 A# is sampled and latched on reset3 and further programming of the 2lash is disabled. < > U Same as mode 83 also verify is disabled. ( > same as mode <3 also e1ternal e1ecution is disabled. *rogramming the 1lash The #T$%/&' is normally shipped with the on?chip 2lash memory array in the erased state 6that is3 contents E 22+7 and ready to be programmed. The programming interface accepts either a high?voltage 6'8?volt7 or a low?voltage 65//7 program enable signal. The low voltage programming mode provides a convenient way to program the #T$%/&' inside the users system3 while the high?voltage programming mode is compatible with conventional third party 2lash or A>R=: programmers. The #T$%/&' is shipped with either the high?voltage or low?voltage programming mode enabled. The respective top? side mar!ing and device signature codes are listed in the following table. The #T$%/&' code memory array is programmed byte?by byte In either programming mode. To program any nonblan! byte in the on?chip 2lash :emory3 the entire memory must be erased using the /hip Arase :ode. *rogramming %lgorithm) "efore programming the #T$%/&'3 the address3 data and control signals should be set up according to the 2lash programming mode table and 2igures < and (. To program the #T$%/&'3 ta!e the following steps. '. Input the desired memory location on the address lines. 8. Input the appropriate data byte on the data lines. <. #ctivate the correct combination of control signals. (. Raise A#45>> to '85 for the high?voltage programming mode. &. >ulse #.A4>R=B once to program a byte in the 2lash array or the loc! bits. The byte? write cycle is self?timed and typically ta!es no more than '.& ms. Repeat steps ' through &3 changing the address and data for the entire array or until the end of the object file is reached.

+ata *olling) The #T$%/&' features Data >olling to indicate the end of a write cycle. During a write cycle3 an attempted read of the last byte written will result in the complement of the written datum on >=.M. =nce the write cycle has been completed3 true data are valid on all outputs3 and the ne1t cycle may begin. Data >olling may begin any time after a write cycle has been initiated. ead(05us() The progress of byte programming can also be monitored by the RDN4"SN output signal. ><.( is pulled low after #.A goes high during programming to indicate "USN. ><.( is pulled high again when programming is done to indicate RA#DN. *rogram -eri'() If loc! bits ."' and ."8 have not been programmed3 the programmed code data can be read bac! via the address and data lines for verification. The loc! bits cannot be verified directly. 5erification of the loc! bits is achieved by observing that their features are enabled. Chi, $rase) The entire 2lash array is erased electrically by using the proper combination of control signals and by holding #.A4>R=B low for ') ms. The code array is written with all O'Ps. The chip erase operation must be e1ecuted before the code memory can be re? programmed. eading the /ignature 5(tes) The signature bytes are read by the same procedure as a normal verification of locations )<)+3 )<'+3 and )<8+3 e1cept that ><.9 and ><.M must be pulled to a logic low. The values returned are as follows. 6)<)+7 E 'A+ indicates manufactured by #tmel

6)<'+7 E &'+ indicates $%/&' 6)<8+7 E 22+ indicates '85 programming 6)<8+7 E )&+ indicates &5 programming *rogramming Inter'ace Avery code byte in the 2lash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated3 will automatically time itself to completion. #ll major programming vendors offer worldwide support for the #tmel microcontroller series. >lease contact your local programming vendor for the appropriate software revision. 1lash *rogramming Modes @oteI '. /hip Arase re-uires a ')?ms >R=B pulse.

/*$CI%# 16"CTI!" $.I/T$ 7/1 8 %++ $//$/) #// " >S S> D>TR D>. D>+ >) >' >8 >< T:=D T/=@ T+) T.= T+' #//U:U.#T=R " RABISTAR >R=BR#: ST#TUS ST#/* >=I@TAR D#T# >=I@TAR 8 "NTAS .= "NTA =2 D>TR $8+ $<+ $)+ %)+ )#)+ )")+ $%+ $$+ $/+ $#+ $D+ +IB+ "NTA =2 D>TR >=RT) >=RT' >=RT8 >=RT< TI:AR4/=U@TAR :=DA /=@TR=. TI:AR /=U@TAR /=@TR=. TI:AR ) +IB+ "NTA TI:AR ) .= "NTA TI:AR ' +IB+ "NTA =RD )A)+ )2)+ )D)+ $'+

T.' S/=@ S"U2 >/=@

TI:AR ' .=

"NTA

$"+ %$+ %%+ $M+

SARI#. /=@TR=. SARI#. D#T# "U22AR >= AR /=@TR=.

T:=D 6TI:AR :=DA7 RABISTAR

"oth timers are the $%c&' share the one register T:=D. ( .S" bit for the timer ) and ( :S" for the timer '. In each case lower 8 bits set the mode of the timer Upper two bits set the operations. B#TAI Bating control when set. Timer4counter is enabled only while the I@TJ hen cleared3 the timer is enabled whenever pin is high and the TR1 control pin is set. the TR1 control bit is set /4TI system cloc!7 :' :) :' ) ) ' ' >S :) ) ' ) ' :ode bit ' :ode bit ) :=DA ) ' 8 < =>AR#TI@B :=DA '< "IT TI:AR4:=DA '9 "IT TI:AR :=DA $ "IT #UT= RA.=#D S>.IT TI:AR :=DA =RD7 Timer or counter selected cleared for timer operation 6input from internal

6>R=BR#: ST#TUS

/N #/ 2) RS' RS) )5 ?? >

>S .M >S .9 >S .& >S .( >S .< >S .8 >S .' >S .)

/#RRN 2.#B #UJI.I#RN /#RRN #5#I.#".A 2=R T+A USAR 2R= BA@AR#. >UR>=SA RABISTAR "#@* SA.A/T=R "IT ' RABISTAR "#@* SA.A/T=R "IT ) =5AR2.= 2.#B USAR DA2I@#".A "IT >#RITN 2.#B SAT4/.A#RAD "N +#RD #RA

>/=@ RABIS#TAR 6@=@ "IT #DDRASS#".A7

If the S:=D E ) 6DA2#U.T =@ RASAT7 T+' E /RNST#. 2RAQUA@/N 8&9???? RRRRRRRRRRRRRRRRRRRR <$( J "#UD R#TA If the S:=D IS E ' /RNST#. 2RAQUA@/N T+' E 8&9?????????????????????????????????????? '%8 J "#UD R#TA There are two ways to increase the baud rate of data transfer in the $)&' '. 8. To use a higher fre-uency crystal To change a bit in the >/=@ register

>/=@ register is an $ bit register. =f the $ bits3 some are unused3 and some are used for the power control capability of the $)&'. The bit which is used for the serial communication is DM3 the S:=D bit. hen the $)&' is powered up3 DM 6S:=D "IT7

=2 >/=@ register is ,ero. rate

e can set it to high by software and thereby double the baud

"#UD R#TA /=:>#RISI=@ 2=R S:=D E ) #@D S:=D E' T+' 6DA/I:#.7 ?< ?9 ?'8 ?8( JT#. E ''.)&%8 :+S IA 6I@TARRU>T A@#".A RABIST=R7 +AJ 2D 2# 2( A$ S:=D E) %9)) ($)) 8()) '8)) S:=D E' '%8)) %9)) ($)) 8())

A#

IA.M

Disable all interrupts if A# E )3 no interrupts is ac!nowledged If A# is '3 each interrupt source is individually enabled or disabled "y sending or clearing its enable bit.

IA.9 AT8 AS AT' AJ' AT) AJ) IA.& IA.( IA.< IA.8 IA.' IA.)

@=T implemented enables or disables timer 8 overflag in $%c&8 only Anables or disables all serial interrupt Anables or Disables timer ' overflow interrupt Anables or disables e1ternal interrupt Anables or Disables timer ) interrupt. Anables or Disables e1ternal interrupt )

I@TARRU>T >RI=RITN RABISTAR

If the bit is )3 the corresponding interrupt has a lower priority and if the bit is ' the corresponding interrupt has a higher priority I>.M I>.9 >T8 >S I>.& I>.( @=T I:>.A:A@TAD3 RASAR5AD 2=R 2UTURA USA. @=T I:>.A:A@TAD3 RASAR5AD 2=R 2UTURA USA DA2I@A T+A TI:AR 8 I@TARRU>T >RI=RITN .A.5A. DA2I@AS T+A SARI#. >=RT I@TARRU>T >RI=RITN .A5A.

>T' >J' >T) >J)

I>.< I>.8 I>.' I>.)

DA2I@AS T+A TI:AR ' I@TARRU>T >RI=RITN .A5A. DA2I@AS AJTAR@#. I@TARRU>T ' >RI=RITN .A5A. DA2I@AS T+A TI:AR ) I@TARRU>T >RI=RITN .A5A. DA2I@AS T+A AJTAR@#. I@TARRU>T ) >RI=RITN .A5A.

S/=@I SARI#. >=RT /=@TR=. RABISTAR3 "IT #DDRASS#".A S/=@

S:) S:' S:8 RA@ T"$ R"$

I I I I I I

S/=@.M Serial >ort mode specified S/=@.9 Serial >ort mode specifier S/=@.& S/=@.( Set4cleared by the software to Anable4disable reception S/=@.< the %th bit that will be transmitted in modes 8 and <3 Set4cleared "y software S/=@.8 In modes 8 0<3 is the %th data bit that was received. In mode '3 If S:8 E )3 R"$ is the stop bit that was received. In mode ) R"$ is not used

T'

S/=@.' Transmit interrupt flag. Set by hardware at the end of the $th bit Time in mode )3 or at the beginning of the stop bit in the other :odes. :ust be cleared by software

R'

S/=@.) Receive interrupt flag. Set by hardware at the end of the $th bit Time in mode )3 or halfway through the stop bit time in the other :odes. :ust be cleared by the software.

T/=@ TI:AR /=U@TAR /=@TR=. RABISTAR This is a bit addressable T2' T/=@.M ' =verflows. /leared by hardware as processor TR' T/=@.9 Timer ' run control bit. Set4cleared by software to turn Timer Timer ' overflows flag. Set by hardware when the Timer4/ounter

TF1 TR1 TF0 TR0 IE IT IE0 IT0

/ounter ' =n4off T2) TR) IA' ITI IA) IT) T/=@.& T/=@.( T/=@.< T/=@.8 T/=@.' T/=@.) Timer ) overflows flag. Set by hardware when the timer4counter ) =verflows. /leared by hardware as processor Timer ) run control bit. Set4cleared by software to turn timer /ounter ) on4off. A1ternal interrupt ' edge flag Interrupt ' type control bit A1ternal interrupt ) edge Interrupt ) type control bit.

MC/-51 1%MI#9 I"/T 6CTI!" /$T

"otes on +ata %ddressing Modes Rn ? or!ing register R)?RM Direct ? '8$ internal R#: locations3 any l4= port3 control or status register KRi ? Indirect internal or e1ternal R#: location addressed by register R) or R' Tdata ? $?bit constant included in instruction Tdata '9 ? '9?bit constant included as bytes 8 and < of instruction "it ? '8$ software flags3 any bit addressable l4= pin3 control or status bit # ? #ccumulator "otes on *rogram %ddressing Modes addr'9 ? Destination address for ./#.. and .U:> may be anywhere within the 9(? *byte program memory address space. addr'' ? Destination address for #/#.. and #U:> will be within the same 8?*byte page of program memory as the first byte of the following instruction. Rel ? SU:> and all conditional jumps include an $ bit offset byte. Range is ; '8M4F '8$ bytes relative to the first byte of the following instruction. %C%## addr11 2unctionI #bsolute call DescriptionI #/#.. unconditionally calls a subroutine located at the indicated address. The instruction increments the >/ twice to obtain the address of the following instruction3 then pushes the '9?bit result onto the stac! 6low?order byte first7 and increments the stac! pointer twice. The destination address is obtained by successively concatenating the five high?order bits of the incremented >/3 op code bits M?&3 and the second byte of the instruction. The subroutine called must therefore start within the same 8* bloc! of program memory as the first byte of the instruction following #/#... @o flags are affected. A1ampleI Initially S> e-uals )M+. The labelPSU"RT@P is at program memory location )<(&+. #fter e1ecuting the instruction #/#.. SU"RT@ at location

)'8<+3 S> will contain )%+3 internal R#: location )$+ and )%+ will contain 8&+ and )'+3 respectively3 and the >/ will contain )<(&+. =perationI #/#.. 6>/7 V 6>/7 ; 8 6S>7 V 6S>7 ; ' 66S>77 V 6>/M?)7 6S>7 V 6S>7 ; ' 66S>77 V 6>/'&?$7 6>/')?)7 V >age address "ytesI 8 /yclesI 8 AncodingI a') a% a$ ' ) ) ) ' aM a9 a& a( a< a8 a' a) %++ %: ;src-<(te= 2unctionI #dd DescriptionI #DD adds the byte variable indicated to the accumulator3 leaving the result in the accumulator. The carry and au1iliary carry flags are set3 respectively3 if there is a /arry out of bit M or bit <3 and cleared otherwise. hen adding unsigned integers3 the hen carry flag indicates an overflow occurred. =5 is set if there is a carry out of bit 9 but not out of bit M3 or a carry out of bit M but not out of bit 9L otherwise =5 is cleared. adding signed integers3 =5 indicates a negative number produced as the sum of two positive operands3 or a positive sum from two negative operands. 2our source operand addressing modes are allowedI register3 direct3 register indirect3 or immediate. A1ampleI The accumulator holds )/<+ 6''))))''"7 and register ) holds )##+ 6')')')')"7. The instruction #DD #3 R) will leave 9D+ 6)'')'')'"7 in the accumulator with the #/ flag cleared and both the carry flag and =5 set to '. %++ %: n =perationI #DD

6#7 V 6#7 ; 6Rn7 "ytesI ' /yclesI ' %++ %: direct =perationI #DD 6#7 V 6#7 ; 6direct7 "ytesI 8 /yclesI ' AncodingI ) ) ' ) ' r r r AncodingI ) ) ' ) ) ' ) ' direct address %++ %: > i =perationI #DD 6#7 V 6#7 ; 66Ri77 "ytesI ' /yclesI ' %++ %: ?data =perationI #DD 6#7 V 6#7 ; Tdata "ytesI 8 /yclesI ' AncodingI ) ) ' ) ) ' ' i AncodingI ) ) ' ) ) ' ) ) immediate data %++C %: ; src-<(te= 2unctionI #dd with carry DescriptionI #DD/ simultaneously adds the byte variable indicated3 the carry flag and the accumulator contents3 leaving the result in the accumulator. The carry and au1iliary

/arry flags are set3 respectively3 if there is a carry out of bit M or bit <3 and cleared otherwise. hen adding unsigned integers3 the carry flag indicates an overflow occurred. hen adding signed integers3 =5 indicates a =5 is set if there is a carry out of bit 9 but not out of bit M3 or a carry out of bit M but not out of bit 9L otherwise =5 is cleared. negative number produced as the sum of two positive operands or a positive sum from two negative operands. 2our source operand addressing modes are allowedI register3 direct3 register indirect3 or immediate. A1ampleI The accumulator holds )/<+ 6''))))''"7 and register ) holds )##+ 6')')')')"7 with the carry flag set. The instruction #DD/ #3 R) will leave 9A+ 6)'')''')"7 in the accumulator with #/ cleared and both the carry flag and =5 set to '. %++C %: n =perationI #DD/ 6#7 V 6#7 ; 6/7 ; 6Rn7 "ytesI ' /yclesI ' %++C %: direct =perationI #DD/ 6#7 V 6#7 ; 6/7 ; 6direct7 "ytesI 8 /yclesI ' AncodingI ) ) ' ' ' r r r AncodingI ) ) ' ' ) ' ) ' direct address %++C %: > i =perationI #DD/ 6#7 V 6#7 ; 6/7 ; 66Ri77 "ytesI ' /yclesI '

%++C %: ?data =perationI #DD/ 6#7 V 6#7 ; 6/7 ; Tdata "ytesI 8 /yclesI ' AncodingI ) ) ' ' ) ' ' i AncodingI ) ) ' ' ) ' ) ) immediate data %@M* addr11 2unctionI #bsolute jump DescriptionI #U:> transfers program e1ecution to the indicated address3 which is formed at runtime by concatenating the high?order five bits of the >/ 6after incrementing the >/ twice73 op code bits M?&3 and the second byte of the instruction. The destination must therefore be within the same 8* bloc! of program memory as the first byte of the instruction following #U:>. A1ampleI The labelPU:>#DRP is at program memory location )'8<+. The instruction #U:> U:>#DR is at location )<(&+ and will load the >/ with )'8<+. =perationI #U: > 6>/7 V 6>/7 ; 8 6>/')?)7 V >age address "ytesI 8 /yclesI 8 AncodingI a') a% a$ ) ) ) ) ' aM a9 a& a( a< a8 a' a) %"# ;dest-<(te=: ;src-<(te= 2unctionI .ogical #@D for byte variables DescriptionI #@. performs the bitwise logical #@D operation between the variables indicated and stores the results in the destination variable. @o flags are affected. The two operands allow si1 addressing mode combinations. hen the destination is an accumulator3 the source can use register3 direct3 register?indirect3 or immediate

addressingL when the destination is a direct address3 the source can be the accumulator or immediate data. "ote) hen this instruction is used to modify an output port3 the value used as the original >ort data will be read from the output data latch3 not the input pins. A1ampleI If the accumulator holds )/<+ 6''))))''"7 and register ) holds )##+ 6')')')')"7 then the instruction #@. #3 R) ill leave $'+ 6'))))))'"7 in the accumulator. hen the destination is a directly addressed byte3 this instruction will clear combinations of bits in any R#: location or hardware register. The mas! byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the accumulator at run?time. The instruction #@. >'3 T)'''))''" will clear bits M3 <3 and 8 of output port '. %"# %: n =perationI #@. 6#7 V 6#7 W 6Rn7 "ytesI ' /yclesI ' AncodingI ) ' ) ' ' r r r %"# %: direct =perationI #@. 6#7 V 6#7 W 6direct7 "ytesI 8 /yclesI ' %"# %: > i =perationI #@. 6#7 V 6#7 W 66Ri77

"ytesI ' /yclesI ' %"# %: ?data =perationI #@. 6#7 V 6#7 W Tdata "ytesI 8 /yclesI ' %"# direct: % =perationI #@. 6direct7 V 6direct7 W 6#7 "ytesI 8 /yclesI ' AncodingI ) ' ) ' ) ' ) ' direct address AncodingI ) ' ) ' ) ' ' i AncodingI ) ' ) ' ) ' ) ) immediate data AncodingI ) ' ) ' ) ' ) ' direct address %"# direct: ?data =perationI #@. 6direct7 V 6direct7 W Tdata "ytesI < /yclesI 8 AncodingI ) ' ) ' ) ) ' ' direct address immediate data %"# C: ;src-<it= 2unctionI .ogical #@D for bit variables DescriptionI If the "oolean value of the source bit is logic ) then clear the carry flagL otherwise leave the carry flag in its current state. # slash 6P4P preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used

as the source value3 but the source bit itself is not affected. @o other flags are affected. =nly direct bit addressing is allowed for the source operand. A1ampleI Set the carry flag if and only if3 >'.) E '3 #//.M E ' and =5 E )I :=5 /3 >'.)L .oad carry with input pin state #@. /3 #//.ML #@D carry with accumulator bit M #@. /3 4=5L #@D with inverse of overflow flag %"# C: <it =perationI #@. 6/7 V 6/7 W 6bit7 "ytesI 8 /yclesI 8 %"# C: 0<it =perationI #@. 6/7 V 6/7 W X 6bit7 "ytesI 8 /yclesI 8 AncodingI ' ) ) ) ) ) ' ) bit address AncodingI ' ) ' ' ) ) ) ) bit address C@"$ ;dest-<(te =: ; src-<(te =: rel 2unctionI /ompare and jump if not e-ual DescriptionI /U@A compares the magnitudes of the first two operands3 and branches if their values are not e-ual. The branch destination is computed by adding the signed relative displacement in the last instruction byte to the >/3 after incrementing the >/ to the start of the ne1t instruction. The carry flag is set if the unsigned integer value of Ydest?byteZ is less than the unsigned integer value of Ysrc?byteZL otherwise3 the carry is cleared. @either operand is affected. The first two operands allow four addressing mode combinationsI the accumulator may be compared with any directly addressed byte or

immediate data3 and any indirect R#: location or wor!ing register can be compared with an immediate constant. A1ampleI The accumulator contains <(+. Register M contains &9+. The first instruction in the se-uence /U@A RM3 T 9)+3 @=TRAQL . . . . . . . . L RM E 9)+ @=TRAQ U/ RAQR.= L If RM Y 9)+L . . . . . . . . L RM Z 9)+ sets the carry flag and branches to the instruction at label @=TRAQ. "y testing the carry flag3 this instruction determines whether RM is greater or less than 9)+. If the data being presented to port ' is also <(+3 then the instruction #ITI /U@A #3 >'3 #IT clears the carry flag and continues with the ne1t instruction in se-uence3 since the accumulator does e-ual the data read from >'. 6If some other value was input on >'3 the program will loop at this point until the >' data changes to <(+7. C@"$ %: direct: rel =perationI 6>/7 V 6>/7 ; < if 6#7 Y Z 6direct7 then 6>/7 V 6>/7 ; relative offset if 6#7 Y 6direct7 then 6/7 V' else 6/7 V ) "ytesI < /yclesI 8 C@"$ %: ?data: rel =perationI 6>/7 V 6>/7 ; < if 6#7 Y Z data then 6>/7 V 6>/7 ; relative offset if 6#7 V data then 6/7 V' else 6/7 V ) "ytesI < /yclesI 8

C@"$ ": ?data: rel =perationI 6>/7 V 6>/7 ; < if 6Rn7 Y Z data then 6>/7 V 6>/7 ; relative offset if 6Rn7 Y data then 6/7 V ' else 6/7 V ) "ytesI < /yclesI 8 AncodingI ' ) ' ' ) ' ) ' direct address rel. address AncodingI ' ) ' ' ) ' ) ) immediate data rel. address AncodingI ' ) ' ' ' r r r immediate data rel. address C@"$ > i: ?data: rel =perationI 6>/7 V 6>/7 ; < if 66Ri77 Y Z data then 6>/7 V 6>/7 ; relative offset if 66Ri77 Y data then 6/7 V ' else 6/7 V ) "ytesI < /yclesI 8 AncodingI ' ) ' ' ) ' ' i immediate data rel. address C# % 2unctionI /lear accumulator DescriptionI The accumulator is cleared 6all bits set to ,ero7. @o flags are affected. A1ampleI The accumulator contains &/+ 6)')'''))"7. The instruction /.R # will leave the accumulator set to ))+ 6))))))))"7.

=perationI /.R 6#7 V ) "ytesI ' /yclesI ' AncodingI ' ' ' ) ) ' ) ) C# <it 2unctionI /lear bit DescriptionI The indicated bit is cleared 6reset to ,ero7. @o other flags are affected. /.R can operate on the carry flag or any directly addressable bit. A1ampleI >ort ' has previously been written with &D+ 6)')''')'"7. The instruction /.R >'.8 will leave the port set to &%+ 6)')''))'"7. C# C =perationI /.R 6/7 V ) "ytesI ' /yclesI ' C# <it =perationI /.R 6bit7 V ) "ytesI 8 /yclesI ' AncodingI ' ' ) ) ) ) ' ' AncodingI ' ' ) ) ) ) ' ) bit address C*# % 2unctionI /omplement accumulator

DescriptionI Aach bit of the accumulator is logically complemented 6ones complement7. "its which previously contained a one are changed to ,ero and vice versa. @o flags are affected. A1ampleI The accumulator contains &/+ 6)')'''))"7. The instruction />. # will leave the accumulator set to )#<+ 6')')))'' "7. =perationI />. 6#7 V X 6#7 "ytesI ' /yclesI ' AncodingI ' ' ' ' ) ' ) ) C*# <it 2unctionI /omplement bit DescriptionI The bit variable specified is complemented. # bit which had been a one is changed to ,ero and vice versa. @o other flags are affected. />. can operate on the carry or any directly addressable bit. "ote) hen this instruction is used to modify an output pin3 the value used as the original data will be read from the output data latch3 not the input pin. A1ampleI >ort ' has previously been written with &D+ 6)')''')'"7. The instruction se-uence />. >'.' />. >'.8 will leave the port set to &"+ 6)')'')''"7. C*# C =perationI />. 6/7 V X 6/7 "ytesI ' /yclesI '

C*# <it =perationI />. 6bit7 V X 6bit7 "ytesI 8 /yclesI ' AncodingI ' ) ' ' ) ) ' ' AncodingI ' ) ' ' ) ) ' ) bit address +% % 2unctionI Decimal adjust accumulator for addition DescriptionI D# # adjusts the eight?bit value in the accumulator resulting from the earlier addition of two variables 6each in pac!ed "/D format73 producing two four?bit digits. #ny #DD or #DD/ instruction may have been used to perform the addition. If accumulator bits <?) are greater than nine 61111')')?1111''''73 or if the #/ flag is one3 si1 is added to the accumulator producing the proper "/D digit in the low order nibble. This internal addition would set the carry flag if a carry?out of the low order four?bit field propagated through all high?order bits3 but it would not clear the carry flag otherwise. If the carry flag is now set3 or if the four high?order bits now e1ceed nine 6')')1111? ''''111173 these high?order bits are incremented by si13 producing the proper "/D digit in the high?order nibble. #gain3 this would set the carry flag if there was a carryout of the high?order bits3 but wouldnt clear the carry. The carry flag thus indicates if the sum of the original two "/D variables is greater than '))3 allowing multiple precision decimal additions. =5 is not affected. #ll of this occurs during the one instruction cycle. AssentiallyL this instruction performs the decimal conversion by adding ))+3 )9+3 9)+3 or 99+ to the accumulator3 depending on initial accumulator and >S "ote) D# # cannot simply convert a he1adecimal number in the accumulator to "/D notation3 nor does D# # apply to decimal subtraction. conditions.

A1ampleI The accumulator holds the value &9+ 6)')')'')"7 representing the pac!ed "/D digits of the decimal number &9. Register < contains the value 9M+ 6)''))'''"7 representing the pac!ed "/D digits of the decimal number 9M. The carry flag is set. The instruction se-uence #DD/ #3 R< D# # will first perform a standard twos?complement binary addition3 resulting in the value )"A+ 6')''''')"7 in the accumulator. The carry and au1iliary carry flags will be cleared. The decimal adjust instruction will then alter the accumulator to the value 8(+ 6))'))'))"73 indicating the pac!ed "/D digits of the decimal number 8(3 the low order two digits of the decimal sum of &93 9M3 and the carry?in. The carry flag will be set by the decimal adjust instruction3 indicating that a decimal overflow occurred. The true sum &93 9M3 and ' is '8(. "/D variables can be incremented or decremented by adding )'+ or %%+. If the accumulator initially holds <)+ 6representing the digits of <) decimal73 then the instruction se-uence #DD #3 T%%+ D# # will leave the carry set and 8%+ in the accumulator3 since <) ; %% E '8%. The low order byte of the sum can be interpreted to mean <) F ' E 8%. =perationI D# contents of accumulator are "/D if [[6#<?)7 Z %\ ] [6#/7 E '\\ then 6#<?)7 V 6#<?)7 ; 9 and if [[6#M?(7 Z %\ ] [6/7 E '\\ then 6#M?(7 V 6#M?(7 ; 9 "ytesI ' /yclesI '

AncodingI ' ' ) ' ) ' ) ) +$C <(te 2unctionI Decrement DescriptionI The variable indicated is decremented by '. #n original value of ))+ wills underflow to )22+. @o flags are affected. 2our operand addressing modes are allowedI accumulator3 register3 direct3 or register?indirect. "ote) hen this instruction is used to modify an output port3 the value used as the original port data will be read from the output data latch3 not the input pins. A1ampleI Register ) contains M2+ 6)'''''''"7. Internal R#: locations MA+ and M2+ contain ))+ and ()+3 respectively. The instruction se-uence DA/ KR) DA/ R) DA/ KR) will leave register ) set to MA+ and internal R#: locations MA+ and M2+ set to )22+ and <2+. +$C % =perationI DA/ 6#7 V 6#7 F ' "ytesI ' /yclesI ' +$C n =perationI DA/ 6Rn7 V 6Rn7 F ' "ytesI ' /yclesI ' AncodingI ) ) ) ' ) ' ) ) AncodingI ) ) ) ' ' r r r

+$C direct =perationI DA/ 6direct7 V 6direct7 F ' "ytesI 8 /yclesI ' +$C > i =perationI DA/ 66Ri77 V 66Ri77 F ' "ytesI ' /yclesI ' AncodingI ) ) ) ' ) ' ) ' direct address AncodingI ) ) ) ' ) ' ' i +I- %5 2unctionI Divide DescriptionI DI5 #" divides the unsigned eight?bit integer in the accumulator by the unsigned eight?bit integer in register ". The accumulator receives the integer part of the -uotientL register " receives the integer remainder. The carry and =5 flags will be cleared. A1ceptionI If " had originally contained ))+3 the values returned in the accumulator and " register will be undefined and the overflow flag will be set. The carry flag is cleared in any case. A1ampleI The accumulator contains 8&' 6)2"+ or ''''')''"7 and " contains '$ 6'8+ or )))'))')"7. The instruction DI5 #" will leave '< in the accumulator 6)D+ or ))))'')' "7 and the value 'M 6''+ or )))')))'"7 in "3 since 8&' E 6'<1'$7 ; 'M. /arry and =5 will both be cleared. =perationI DI5 6#'&?$7

6"M?)7 "ytesI ' /yclesI ( AncodingI ' ) ) ) ) ' ) ) V 6#7 4 6"7 +@"A ;<(te=: ; rel-addr= 2unctionI Decrement and jump if not ,ero DescriptionI DU@S decrements the location indicated by '3 and branches to the address indicated by the second operand if the resulting value is not ,ero. #n original value of ))+ wills underflow to )22+. @o flags are affected. The branch destination would be computed by adding the signed relative?displacement value in the last instruction byte to the >/3 after incrementing the >/ to the first byte of the following instruction. The location decremented may be a register or directly addressed byte. "ote) hen this instruction is used to modify an output port3 the value used as the original port data will be read from the output data latch3 not the input pins. A1ampleI Internal R#: locations ()+3 &)+3 and 9)+ contain the values3 )'+3 M)+3 and '&+3 respectively. The instruction se-uence DU@S ()+3 .#"A.R' DU@S &)+3 .#"A.R8 DU@S 9)+3 .#"A.R< will cause a jump to the instruction at label .#"A.R8 with the values ))+3 92+3 and '&+ in the three R#: locations. The first jump was not ta!en because the result was ,ero. This instruction provides a simple way of e1ecuting a program loop a given number of times3 or for adding a moderate time delay 6from 8 to &'8 machine cycles7 with a single instruction. The instruction se-uence :=5 R83 T$ T=BB.AI />. >'.M DU@S R83 T=BB.A

will toggle >'.M eight times3 causing four output pulses to appear at bit M of output port '. Aach pulse will last three machine cyclesL two for DU@S and one to alter the pin. +@"A n: rel =perationI DU@S 6>/7 V 6>/7 ; 8 6Rn7 V 6Rn7 F ' if 6Rn7 Z ) or 6Rn7 Y ) then 6>/7 V 6>/7 ; rel "ytesI 8 /yclesI 8 +@"A direct: rel =perationI DU@S 6>/7 V 6>/7 ; 8 6direct7 V 6direct7 F ' if 6direct7 Z ) or 6direct7 Y ) then 6>/7 V 6>/7 ; rel "ytesI < /yclesI 8 AncodingI ' ' ) ' ' r r r rel. address AncodingI ' ' ) ' ) ' ) ' direct address rel. address I"C ;<(te= 2unctionI Increment DescriptionI I@/ increments the indicated variable by '. #n original value of )22+ will overflow to ))+. @o flags are affected. Three addressing modes are allowedI register3 direct3 or register?indirect. "ote) hen this instruction is used to modify an output port3 the value used as the original port data will be read from the output data latch3 not the input pins.

A1ampleI Register ) contains MA+ 6)'''''')"7. Internal R#: locations MA+ and M2+ contain )22+ and ()+3 respectively. The instruction se-uence I@/ KR) I@/ R) I@/ KR) will leave register ) set to M2+ and internal R#: locations MA+ and M2+ holding 6respectively7 ))+ and ('+. I"C % =perationI I@/ 6#7 V 6#7 ; ' "ytesI ' /yclesI ' I"C n =perationI I@/ 6Rn7 V 6Rn7 ; ' "ytesI ' /yclesI ' AncodingI ) ) ) ) ) ' ) ) AncodingI ) ) ) ) ' r r r I"C direct =perationI I@/ 6direct7 V 6direct7 ; ' "ytesI 8 /yclesI ' I"C > i =perationI I@/ 66Ri77 V 66Ri77 ; '

"ytesI ' /yclesI ' AncodingI ) ) ) ) ) ' ) ' direct address AncodingI ) ) ) ) ) ' ' i I"C +*T 2unctionI Increment data pointer DescriptionI Increment the '9?bit data pointer by '. # '9?bit increment 6modulo 8'97 is performedL an overflow of the low?order byte of the data pointer 6D>.7 from )22+ to ))+ will increment the high?order byte 6D>+7. @o flags are affected. This is the only '9? bit register which can be incremented. A1ampleI Registers D>+ and D>. contain '8+ and )2A+3 respectively. The instruction se-uence I@/ D>TR I@/ D>TR I@/ D>TR will change D>+ and D>. to '<+ and )'+. =perationI I@/ 6D>TR7 V 6D>TR7 ; ' "ytesI ' /yclesI 8 AncodingI ' ) ' ) ) ) ' ' @5 <it: rel 2unctionI Uump if bit is set DescriptionI If the indicated bit is a one3 jump to the address indicatedL otherwise proceed with the ne1t instruction. The branch destination is computed by adding the signed relative?displacement in the third instruction byte to the >/3 after incrementing the >/ to the first byte of the ne1t instruction. The bit tested is not modified. @o flags are affected. A1ampleI The data present at input port ' is ''))')')". The accumulator holds &9 6)')')'')"7. The instruction se-uence

U" >'.83 .#"A.' U" #//.83 .#"A.8 will cause program e1ecution to branch to the instruction at label .#"A.8. =perationI U" 6>/7 V 6>/7 ; < if 6bit7 E ' then 6>/7 V 6>/7 ; rel "ytesI < /yclesI 8 AncodingI ) ) ' ) ) ) ) ) bit address rel. address @5C <it: rel 2unctionI Uump if bit is set and clear bit DescriptionI If the indicated bit is one3 branch to the address indicatedL otherwise proceed with the ne1t instruction. In either case3 clear the designated bit. The branch destination is computed by adding the signed relative displacement in the third instruction byte to the >/3 after incrementing the >/ to the first byte of the ne1t instruction. @o flags are affected. "ote) hen this instruction is used to test an output pin3 the value used as the original data will be read from the output data latch3 not the input pin. A1ampleI The accumulator holds &9+ 6)')')'')"7. The instruction se-uence U"/ #//.<3 .#"A.' U"/ #//.83 .#"A.8 will cause program e1ecution to continue at the instruction identified by the label .#"A.83 with the accumulator modified to &8+ 6)')'))')"7. =perationI U"/ 6>/7 V 6>/7 ; < if 6bit7 E ' then 6bit7 V ) 6>/7 V 6>/7 ; rel

"ytesI < /yclesI 8 AncodingI ) ) ) ' ) ) ) ) bit address rel. address @C rel 2unctionI Uump if carry is set DescriptionI If the carry flag is set3 branch to the address indicatedL otherwise proceed with the ne1t instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the >/3 after incrementing the >/ twice. @o flags are affected. A1ampleI The carry flag is cleared. The instruction se-uence U/ .#"A.' />. / U/ .#"A.8 will set the carry and cause program e1ecution to continue at the instruction identified by the label .#"A.8. =perationI U/ 6>/7 V 6>/7 ; 8 if 6/7 E ' then 6>/7 V 6>/7 ; rel "ytesI 8 /yclesI 8 AncodingI ) ' ) ) ) ) ) ) rel. address @M* >% B +*T 2unctionI Uump indirect DescriptionI #dd the eight?bit unsigned contents of the accumulator with the si1teen?bit data pointer3 and load the resulting sum to the program counter. This will be the address for subse-uent instruction fetches. Si1teen?bit addition is performed 6modulo 8'97I a carry?out from the low?order eight bits propagates through the higher?order bits. @either the accumulator nor the data pointer is altered. @o flags are affected.

A1ampleI #n even number from ) to 9 is in the accumulator. The following se-uence of instructions will branch to one of four #U:> instructions in a jump table starting at U:>RT".I :=5 D>TR3 TU:>RT". U:> K# ; D>TR U:>RT".I #U:> .#"A.) #U:> .#"A.' #U:> .#"A.8 #U:> .#"A.< If the accumulator e-uals )(+ when starting this se-uence3 e1ecution will jump to label .#"A.8. Remember that #U:> is a two?byte instruction3 so the jump instructions start at every other address. =perationI U:> 6>/7 V 6#7 ; 6D>TR7 "ytesI ' /yclesI 8 AncodingI ) ' ' ' ) ) ' ' @"5 <it: rel 2unctionI Uump if bit is not set DescriptionI If the indicated bit is a ,ero3 branch to the indicated addressL otherwise proceed with the ne1t instruction. The branch destination is computed by adding the signed relative?displacement in the third instruction byte to the >/3 after incrementing the >/ to the first byte of the ne1t instruction. The bit tested is not modified. @o flags are affected. A1ampleI The data present at input port ' is ''))')')". The accumulator holds &9+ 6)')')'')"7. The instruction se-uence U@" >'.<3 .#"A.' U@" #//.<3 .#"A.8 will cause program e1ecution to continue at the instruction at label .#"A.8. =perationI U@"

6>/7 V 6>/7 ; < if 6bit7 E ) then 6>/7 V 6>/7 ; rel. "ytesI < /yclesI 8 AncodingI ) ) ' ' ) ) ) ) bit address rel. address @"C rel 2unctionI Uump if carry is not set DescriptionI If the carry flag is a ,ero3 branch to the address indicatedL otherwise proceed with the ne1t instruction. The branch destination is computed by adding the signed relative?displacement in the second instruction byte to the >/3 after incrementing the >/ twice to point to the ne1t instruction. The carry flag is not modified. A1ampleI The carry flag is set. The instruction se-uence U@/ .#"A.' />. / U@/ .#"A.8 will clear the carry and cause program e1ecution to continue at the instruction identified by the label .#"A.8. =perationI U@/ 6>/7 V 6>/7 ; 8 if 6/7 E ) then 6>/7 V 6>/7 ; rel "ytesI 8 /yclesI 8 AncodingI ) ' ) ' ) ) ) ) rel. address @"A rel 2unctionI Uump if accumulator is not ,ero

DescriptionI If any bit of the accumulator is a one3 branch to the indicated addressL otherwise proceed with the ne1t instruction. The branch destination is computed by adding the signed relative?displacement in the second instruction byte to the >/3 after incrementing the >/ twice. The accumulator is not modified. @o flags are affected. A1ampleI The accumulator originally holds ))+. The instruction se-uence U@S .#"A.' I@/ # U@S .#"A.8 will set the accumulator to )'+ and continue at label .#"A.8. =perationI U@S 6>/7 V 6>/7 ; 8 if 6#7 ^ ) then 6>/7 V 6>/7 ; rel. "ytesI 8 /yclesI 8 AncodingI ) ' ' ' ) ) ) ) rel. address @A rel 2unctionI Uump if accumulator is ,ero DescriptionI If all bits of the accumulator are ,ero3 branch to the address indicatedL otherwise proceed with the ne1t instruction. The branch destination is computed by adding the signed relative?displacement in the second instruction byte to the >/3 after incrementing the >/ twice. The accumulator is not modified. @o flags are affected. A1ampleI The accumulator originally contains )'+. The instruction se-uence US .#"A.' DA/ # US .#"A.8 will change the accumulator to ))+ and cause program e1ecution to continue at the instruction identified by the label .#"A.8. =perationI US 6>/7 V 6>/7 ; 8

if 6#7 E ) then 6>/7 V 6>/7 ; rel "ytesI 8 /yclesI 8 AncodingI ) ' ' ) ) ) ) ) rel. address #C%## addr1C 2unctionI .ong call DescriptionI ./#.. calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the ne1t instruction and then pushes the '9?bit result onto the stac! 6low byte first73 incrementing the stac! pointer by two. The high?order and low?order bytes of the >/ are then loaded3 respectively3 with the second and third bytes of the ./#.. instruction. >rogram e1ecution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 9( *bytes program memory address space. @o flags are affected. A1ampleI Initially the stac! pointer e-uals )M+. The labelPSU"RT@P is assigned to program memory location '8<(+. #fter e1ecuting the instruction ./#.. SU"RT@ at location )'8<+3 the stac! pointer will contain )%+3 internal R#: locations )$+ and )%+ will contain 89+ and )'+3 and the >/ will contain '8<(+. =perationI ./#.. 6>/7 V 6>/7 ; < 6S>7 V 6S>7 ; ' 66S>77 V 6>/M?)7 6S>7 V 6S>7 ; ' 66S>77 V 6>/'&?$7 6>/7 V addr'&?) "ytesI < /yclesI 8 AncodingI ) ) ) ' ) ) ' ) addr'&. . addr$ addrM. . addr)

#@M* addr1C 2unctionI .ong jump DescriptionI .U:> causes an unconditional branch to the indicated address3 by loading the high order and low?order bytes of the >/ 6respectively7 with the second and third instruction bytes. The destination may therefore be anywhere in the full 9(* program memory address space. @o flags are affected. A1ampleI The labelPU:>#DRP is assigned to the instruction at program memory location '8<(+. The instruction .U:> U:>#DR at location )'8<+ will load the program counter with '8<(+. =perationI .U:> 6>/7 V addr'&?) "ytesI < /yclesI 8 AncodingI ) ) ) ) ) ) ' ) addr'& . . . addr$ addrM . . . addr) M!- ;dest-<(te=: ;src-<(te= 2unctionI :ove byte variable DescriptionI The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. @o other register or flag is affected. This is by far the most fle1ible operation. 2ifteen combinations of source and destination addressing modes are allowed. A1ampleI Internal R#: location <)+ holds ()+. The value of R#: location ()+ is ')+. The data present at input port ' is ''))')')" 6)/#+7. :=5 R)3 T<)+L R) Y E <)+ :=5 #3 KR)L # Y E ()+ :=5 R'3 #L R' Y E ()+ :=5 "3 KR'L " Y E ')+ :=5 KR'3 >'L R#: 6()+7 Y E )/#+ :=5 >83 >'L >8 Y E )/#+ leaves the value <)+ in register )3 ()+ in both the accumulator and register '3 ')+

in register "3 and )/#+ 6''))')')"7 both in R#: location ()+ and output on port 8. M!- %: n =perationI :=5 6#7 V 6Rn7 "ytesI ' /yclesI ' M!- %: direct D8 =perationI :=5 6#7 V 6direct7 "ytesI 8 /yclesI ' _7 :=5 #3 #// is not a valid instruction. AncodingI ' ' ' ) ' r r r AncodingI ' ' ' ) ) ' ) ' direct address M!- %:> i =perationI :=5 6#7 V 66Ri77 "ytesI ' /yclesI ' M!- %: ?data =perationI :=5 6#7 V Tdata "ytesI 8 /yclesI ' M!- n: % =perationI :=5

6Rn7 V 6#7 "ytesI ' /yclesI ' M!- n: direct =perationI :=5 6Rn7 V 6direct7 "ytesI 8 /yclesI 8 AncodingI ' ' ' ) ) ' ' i AncodingI ) ' ' ' ) ' ) ) immediate data AncodingI ' ' ' ' ' r r r AncodingI ' ) ' ) ' r r r direct address M!- n: ?data =perationI :=5 6Rn7 V Tdata "ytesI 8 /yclesI ' M!- direct: % =perationI :=5 6direct7 V 6#7 "ytesI 8 /yclesI ' M!- direct: n =perationI :=5 6direct7 V 6Rn7 "ytesI 8 /yclesI 8

M!- direct: direct =perationI :=5 6direct7 V 6direct7 "ytesI < /yclesI 8 AncodingI ) ' ' ' ' r r r immediate data AncodingI ' ' ' ' ) ' ) ' direct address AncodingI ' ) ) ) ' r r r direct address AncodingI ' ) ) ) ) ' ) ' dir.addr. 6src7 dir.addr. 6dest7 M!- direct: > i =perationI :=5 6direct7 V 66Ri77 "ytesI 8 /yclesI 8 M!- direct: ?data =perationI :=5 6direct7 V Tdata "ytesI < /yclesI 8 M!- > i: % =perationI :=5 66Ri77 V 6#7 "ytesI ' /yclesI ' M!- > i: direct =perationI :=5

66Ri77 V 6direct7 "ytesI 8 /yclesI 8 AncodingI ' ) ) ) ) ' ' i direct address AncodingI ) ' ' ' ) ' ) ' direct address immediate data AncodingI ' ' ' ' ) ' ' i AncodingI ' ) ' ) ) ' ' i direct address M!- > i: ?data =perationI :=5 66Ri77 V Tdata "ytesI 8 /yclesI ' AncodingI ) ' ' ' ) ' ' i immediate data M!- ;dest-<it=: ;src-<it= 2unctionI :ove bit data DescriptionI The "oolean variable indicated by the second operand is copied into the location specified by the first operand. =ne of the operands must be the carry flagL the other may be any directly addressable bit. @o other register or flag is affected. A1ampleI The carry flag is originally set. The data present at input port < is '')))')'". The data previously written to output port ' is <&+ 6))'')')'"7. :=5 >'.<3 / :=5 /3 ><.< :=5 >'.83 / will leave the carry cleared and change port ' to <%+ 6))'''))' "7. M!- C: <it =perationI :=5 6/7 V 6bit7 "ytesI 8

/yclesI ' M!- <it: C =perationI :=5 6bit7 V 6/7 "ytesI 8 /yclesI 8 AncodingI ' ) ' ) ) ) ' ) bit address AncodingI ' ) ) ' ) ) ' ) bit address M!- +*T : ?data1C 2unctionI .oad data pointer with a '9?bit constant DescriptionI The data pointer is loaded with the '9?bit constant indicated. The '9 bit constant is loaded into the second and third bytes of the instruction. The second byte 6D>+7 is the high?order byte3 while the third byte 6D>.7 holds the low?order byte. @o flags are affected. This is the only instruction which moves '9 bits of data at once. A1ampleI The instruction :=5 D>TR3 T'8<(+ will load the value '8<(+ into the data pointerI D>+ will hold '8+ and D>. will hold <(+. =perationI :=5 6D>TR7 V Tdata'&?) D>+ D>. V Tdata'&?$ TdataM?) "ytesI < /yclesI 8 AncodingI ' ) ) ' ) ) ) ) immed. data '& . . . $ immed. data M . . . ) M!-C %: >% B ;<ase-reg= 2unctionI :ove code byte DescriptionI The :=5/ instructions load the accumulator with a code byte3 or constant from program memory. The address of the byte fetched is the sum of the original

unsigned eight?bit accumulator contents and the contents of a si1teen?bit base register3 which may be either the data pointer or the >/. In the latter case3 the >/ is incremented to the address of the following instruction before being added to the accumulatorL otherwise the base register is not altered. Si1teen?bit addition is performed so a carry?out from the low?order eight bits may propagate through higher?order bits. @o flags are affected. A1ampleI # value between ) and < is in the accumulator. The following instructions will translate the value in the accumulator to one of four values defined by the D" 6define byte7 directive. RA.R>/I I@/ # :=5/ #3 K# ; >/ RAT D" 99+ D" MM+ D" $$+ D" %%+ If the subroutine is called with the accumulator e-ual to )'+3 it will return with MM+ in the accumulator. The I@/ # before the :=5/ instruction is needed toPget aroundP the RAT instruction above the table. If several bytes of code separated the :=5/ from the table3 the corresponding number would be added to the accumulator instead. M!-C %: >% B +*T =perationI :=5/ 6#7 V 66#7 ; 6D>TR77 "ytesI ' /yclesI 8 AncodingI ' ) ) ' ) ) ' ' M!-C %: >% B *C =perationI :=5/ 6>/7 V 6>/7 ; '

6#7 V 66#7 ; 6>/77 "ytesI ' /yclesI 8 AncodingI ' ) ) ) ) ) ' ' M!-2 ;dest-<(te=: ;src-<(te= 2unctionI :ove e1ternal DescriptionI The :=5J instructions transfer data between the accumulator and a byte of e1ternal data memory3 hence thePJP appended to :=5. There are two types of instructions3 differing in whether they provide an eight bit or si1teen?bit indirect address to the e1ternal data R#:. In the first type3 the contents of R) or R' in the current register ban! provide an eight?bit address multiple1ed with data on >). Aight bits are sufficient for e1ternal l4= e1pansion decoding or a relatively small R#: array. 2or somewhat larger arrays3 any output port pins can be used to output higher?order address bits. These pins would be controlled by an output instruction preceding the :=5J. In the second type of :=5J instructions3 the data pointer generates a si1teen?bit address. >8 outputs the high?order eight address bits 6the contents of D>+7 while >) multiple1es the low? order eight bits 6D>.7 with data. The >8 special function register retains its previous contents while the >8 output buffers are emitting the contents of D>+. This form is faster and more efficient when accessing very large data arrays 6up to 9( *bytes73 since no additional instructions are needed to set up the output ports. It is possible in some situations to mi1 the two :=5J types. # large R#: array with its high?order address lines driven by >8 can be addressed via the data pointer3 or with code to output high? order address bits to >8 followed by a :=5J instruction using R) or R'. A1ampleI #n e1ternal 8&9 byte R#: using multiple1ed address4data lines 6e.g. an S#" $'&& R#:4I4=4timer7 is connected to the S#" $)6c7 &JJ port ). >ort < provides control lines for the e1ternal R#:. >orts ' and 8 are used for normal l4=. Registers ) and ' contain '8+ and <(+. .ocation <(+ of the e1ternal R#: holds the value &9+. The instruction se-uence :=5J #3 KR' :=5J KR)3 #

copies the value &9+ into both the accumulator and e1ternal R#: location '8+. M!-2 %:> i =perationI :=5J 6#7 V 66Ri77 "ytesI ' /yclesI 8 M!-2 %:>+*T =perationI :=5J 6#7 V 66D>TR77 "ytesI ' /yclesI 8 M!-2 > i: % =perationI :=5J 66Ri77 V 6#7 "ytesI ' /yclesI 8 M!-2 >+*T : % =perationI :=5J 66D>TR77 V 6#7 "ytesI ' /yclesI 8 AncodingI ' ' ' ) ) ) ' i AncodingI ' ' ' ) ) ) ) ) AncodingI ' ' ' ' ) ) ' i AncodingI ' ' ' ' ) ) ) ) M6# %5

2unctionI :ultiply DescriptionI :U. #" multiplies the unsigned eight?bit integers in the accumulator and register ". The low?order byte of the si1teen?bit product is left in the accumulator3 and the high?order byte in ". If the product is greater than 8&& 6)22+7 the overflow flag is setL otherwise it is cleared. The carry flag is always cleared. A1ampleI =riginally the accumulator holds the value $) 6&)+7. Register " holds the value '9) 6)#)+7. The instruction :U. #" will give the product '83$)) 6<8))+73 so " is changed to <8+ 6))''))')"7 and the accumulator is cleared. The overflow flag is set3 carry is cleared. =perationI :U. 6#M?)7 6"'&?$7 "ytesI ' /yclesI ( AncodingI ' ) ' ) ) ' ) ) V 6#7 1 6"7 "!* 2unctionI @o operation DescriptionI A1ecution continues at the following instruction. =ther than the >/3 no registers or flags are affected. A1ampleI It is desired to produce a low?going output pulse on bit M of port 8 lasting e1actly & cycles. # simple SAT"4/.R se-uence would generate a one?cycle pulse3 so four additional cycles must be inserted. This may be done 6assuming no interrupts are enabled7 with the instruction se-uence /.R >8.M @=> @=> @=> @=>

SAT" >8.M =perationI @=> "ytesI ' /yclesI ' AncodingI ) ) ) ) ) ) ) ) ! # ;dest-<(te= ;src-<(te= 2unctionI .ogical =R for byte variables DescriptionI =R. performs the bitwise logical =R operation between the indicated variables3 storing the results in the destination byte. @o flags are affected. The two operands allow si1 addressing mode combinations. hen the destination is the accumulator3 the source can use register3 direct3 register?indirect3 or immediate addressingL when the destination is a direct address3 the source can be the accumulator or immediate data. "ote) hen this instruction is used to modify an output port3 the value used as the original port data will be read from the output data latch3 not the input pins. A1ampleI If the accumulator holds )/<+ 6''))))''"7 and R) holds &&+ 6)')')')'"7 then the instruction =R. #3 R) will leave the accumulator holding the value )DM+ 6'')')'''"7. hen the destination is a directly addressed byte3 the instruction can set combinations of bits in any R#: location or hardware register. The pattern of bits to be set is determined by a mas! byte3 which may be either a constant data value in the instruction or a variable computed in the accumulator at run?time. The instruction =R. >'3 T))''))')" will set bits &3 (3 and ' of output port '. ! # %: n =perationI =R. 6#7 V 6#7 ] 6Rn7

"ytesI ' /yclesI ' AncodingI ) ' ) ) ' r r r ! # %: direct =perationI =R. 6#7 V 6#7 ] 6direct7 "ytesI 8 /yclesI ' ! # %:> i =perationI =R. 6#7 V 6#7 ] 66Ri77 "ytesI ' /yclesI ' ! # %: data =perationI =R. 6#7 V 6#7 ] Tdata "ytesI 8 /yclesI ' ! # direct: % =perationI =R. 6direct7 V 6direct7 ] 6#7 "ytesI 8 /yclesI ' AncodingI ) ' ) ) ) ' ) ' direct address AncodingI ) ' ) ) ) ' ' i AncodingI ) ' ) ) ) ' ) ) immediate data AncodingI ) ' ) ) ) ) ' ) direct address

! # direct: ?data =perationI =R. 6direct7 V 6direct7 ] Tdata "ytesI < /yclesI 8 AncodingI ) ' ) ) ) ) ' ' direct address immediate data ! # C: ;src-<it= 2unctionI .ogical =R for bit variables DescriptionI Set the carry flag if the "oolean value is logic 'L leave the carry in its current state otherwise. # slash 6P4P7 preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value3 but the source bit itself is not affected. @o other flags are affected. A1ampleI Set the carry flag if and only if3 >'.) E '3 #//.M E ' or =5 E )I :=5 /3 >'.)L .oad carry with input pin >'.) =R. /3 #//.ML =R carry with the accumulator bit M =R. /3 4=5L =R carry with the inverse of =5 ! # C: <it =perationI =R. 6/7 V 6/7 ] 6bit7 "ytesI 8 /yclesI 8 ! # C: 0<it =perationI =R. 6/7 V 6/7 ] X 6bit7 "ytesI 8 /yclesI 8 AncodingI ) ' ' ' ) ) ' ) bit address

AncodingI ' ) ' ) ) ) ) ) bit address *!* direct 2unctionI >op from stac! DescriptionI The contents of the internal R#: location addressed by the stac! pointer are read3 and the stac! pointer is decremented by one. The value read is the transfer to the directly addressed byte indicated. @o flags are affected. A1ampleI The stac! pointer originally contains the value <8+3 and internal R#: locations <)+ through <8+ contain the values 8)+3 8<+3 and )'+3 respectively. The instruction se-uence >=> D>+ >=> D>. will leave the stac! pointer e-ual to the value <)+ and the data pointer set to )'8<+. #t this point the instruction >=> S> will leave the stac! pointer set to 8)+. @ote that in this special case the stac! pointer was decremented to 82+ before being loaded with the value popped 68)+7. =perationI >=> 6direct7 V 66S>77 6S>7 V 6S>7 F ' "ytesI 8 /yclesI 8 AncodingI ' ' ) ' ) ) ) ) direct address *6/E direct 2unctionI >ush onto stac! DescriptionI The stac! pointer is incremented by one. The contents of the indicated variable is then copied into the internal R#: location addressed by the stac! pointer. =therwise no flags are affected.

A1ampleI =n entering an interrupt routine the stac! pointer contains )%+. The data pointer holds the value )'8<+. The instruction se-uence >US+ D>. >US+ D>+ will leave the stac! pointer set to )"+ and store 8<+ and )'+ in internal R#: locations )#+ and )"+3 respectively. =perationI >US+ 6S>7 V 6S>7 ; ' 66S>77 V 6direct7 "ytesI 8 /yclesI 8 AncodingI ' ' ) ) ) ) ) ) direct address $T 2unctionI Return from subroutine DescriptionI RAT pops the high and low?order bytes of the >/ successively from the stac!3 decrementing the stac! pointer by two. >rogram e1ecution continues at the resulting address3 generally the instruction immediately following an #/#.. or ./#... @o flags are affected. A1ampleI The stac! pointer originally contains the value )"+. Internal R#: locations )#+ and )"+ contain the values 8<+ and )'+3 respectively. The instruction RAT will leave the stac! pointer e-ual to the value )%+. >rogram e1ecution will continue at location )'8<+. =perationI RAT 6>/'&?$7 V 66S>77 6S>7 V 6S>7 F ' 6>/M?)7 V 66S>77 6S>7 V 6S>7 F ' "ytesI ' /yclesI 8 AncodingI ) ) ' ) ) ) ' )

$TI 2unctionI Return from interrupt DescriptionI RATI pops the high and low?order bytes of the >/ successively from the stac!3 and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The stac! pointer is left decremented by two. @o other registers are affectedL the >S is not automatically restored to its pre?interrupt status. >rogram e1ecution continues at the resulting address3 which is generally the instruction immediately after the point at which the interrupt re-uest was detected. If a lower or same?level interrupt is pending when the RATI instruction is e1ecuted3 that one instruction will be e1ecuted before the pending interrupt is processed. A1ampleI The stac! pointer originally contains the value )"+. #n interrupt was detected during the instruction ending at location )'88+. Internal R#: locations )#+ and )"+ contain the values 8<+ and )'+3 respectively. The instruction RATI will leave the stac! pointer e-ual to )%+ and return program e1ecution to location )'8<+. =perationI RATI 6>/'&?$7 V 66S>77 6S>7 V 6S>7 F ' 6>/M?)7 V 66S>77 6S>7 V 6S>7 F ' "ytesI ' /yclesI 8 AncodingI ) ) ' ' ) ) ' ) #% 2unctionI Rotate accumulator left DescriptionI The eight bits in the accumulator are rotated one bit to the left. "it M is rotated into the bit ) position. @o flags are affected.

A1ampleI The accumulator holds the value )/&+ 6'')))')'"7. The instruction R. # leaves the accumulator holding the value $"+ 6')))')''"7 with the carry unaffected. =perationI R. 6#n ; '7 V 6#n7 n E )?9 6#)7 V 6#M7 "ytesI ' /yclesI ' AncodingI ) ) ' ) ) ) ' ' #C % 2unctionI Rotate accumulator left through carry flag DescriptionI The eight bits in the accumulator and the carry flag are together rotated one bit to the left. "it M moves into the carry flagL the original state of the carry flag moves into the bit ) position. @o other flags are affected. A1ampleI The accumulator holds the value )/&+ 6'')))')'"73 and the carry is ,ero. The instruction R./ # leaves the accumulator holding the value $#+ 6')))')')"7 with the carry set. =perationI R./ 6#n ; '7 V 6#n7 n E )?9 6#)7 V 6/7 6/7 V 6#M7 "ytesI ' /yclesI ' AncodingI ) ) ' ' ) ) ' ' % 2unctionI Rotate accumulator right DescriptionI The eight bits in the accumulator are rotated one bit to the right. "it ) is rotated into the bit M positions. @o flags are affected. A1ampleI The accumulator holds the value )/&+ 6'')))')'"7. The instruction

RR # leaves the accumulator holding the value )A8+ 6''')))')"7 with the carry unaffected. =perationI RR 6#n7 V 6#n ; '7 n E )?9 6#M7 V 6#)7 "ytesI ' /yclesI ' AncodingI ) ) ) ) ) ) ' ' C% 2unctionI Rotate accumulator right through carry flag DescriptionI The eight bits in the accumulator and the carry flag are together rotated one bit to the right. "it ) moves into the carry flagL the original value of the carry flag moves into the bit M position. @o other flags are affected. A1ampleI The accumulator holds the value )/&+ 6'')))')'"73 the carry is ,ero. The instruction RR/ # leaves the accumulator holding the value 98+ 6)'')))')"7 with the carry set. =perationI RR/ 6#n7 V 6#n ; '7 nE)?9 6#M7 V 6/7 6/7 V 6#)7 "ytesI ' /yclesI ' AncodingI ) ) ) ' ) ) ' ' /$T5 ;<it= 2unctionI Set bit DescriptionI SAT" sets the indicated bit to one. SAT" can operate on the carry flag or any directly addressable bit. @o other flags are affected. A1ampleI The carry flag is cleared. =utput port ' has been written with the value <(+

6))'')'))"7. The instructions SAT" / SAT" >'.) will leave the carry flag set to ' and change the data output on port ' to <&+ 6))'')')'"7. /$T5 C =perationI SAT" 6/7 V ' "ytesI ' /yclesI ' /$T5 <it =perationI SAT" 6bit7 V ' "ytesI 8 /yclesI ' AncodingI ' ' ) ' ) ) ' ' AncodingI ' ' ) ' ) ) ' ) bit address /@M* rel 2unctionI Short jump DescriptionI >rogram control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the >/3 after incrementing the >/ twice. Therefore3 the range of destinations allowed is from '8$ bytes preceding this instruction to '8M bytes following it. A1ampleI The label PRA.#DRP is assigned to an instruction at program memory location )'8<+. The instruction SU:> RA.#DR

will assemble into location )'))+. #fter the instruction is e1ecuted3 the >/ will contain the value )'8<+. "ote) Under the above conditions the instruction following SU:> will be at ')8+. Therefore3 the displacement byte of the instruction will be the relative offset 6)'8<+?)')8+7 E 8'+. In other words3 an SU:> with a displacement of )2A+ would be a one?instruction infinite loop. =perationI SU:> 6>/7 V 6>/7 ; 8 6>/7 V 6>/7 ; rel "ytesI 8 /yclesI 8 AncodingI ' ) ) ) ) ) ) ) rel. address /655 %: ;src-<(te= 2unctionI Subtract with borrow DescriptionI SU"" subtracts the indicated variable and the carry flag together from the accumulator3 leaving the result in the accumulator. SU"" sets the carry 6borrow7 flag if a borrow is needed for bit M3 and clears / otherwise. 6If / was set before e1ecuting a SU"" instruction3 this indicates that a borrow was needed for the previous step in a multiple precision subtraction3 so the carry is subtracted from the accumulator along with the source operand7. #/ is set if a borrow is needed for bit <3 and cleared otherwise. =5 is set if a borrow is needed into bit 9 but not into bit M3 or into bit M but not bit 9. hen subtracting signed integers =5 indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number. The source operand allows four addressing modesI register3 direct3 register indirect3 or immediate. A1ampleI The accumulator holds )/%+ 6''))'))'"73 register 8 holds &(+ 6)')')'))"73 and the carry flag is set. The instruction SU"" #3 R8

will leave the value M(+ 6)''')'))"7 in the accumulator3 with the carry flag and #/ cleared but =5 set. @otice that )/%+ minus &(+ is M&+. The difference between this and the above result is due to the 6borrow7 flag being set before the operation. If the state of the carry is not !nown before starting a single or multiple?precision subtraction3 it should be e1plicitly cleared by a /.R / instruction. /655 %: n =perationI SU"" 6#7 V 6#7 F 6/7 F 6Rn7 "ytesI ' /yclesI ' /655 %: direct =perationI SU"" 6#7 V 6#7 F 6/7 F 6direct7 "ytesI 8 /yclesI ' /655 %: > i =perationI SU"" 6#7 V 6#7 F 6/7 F 66Ri77 "ytesI ' /yclesI ' /655 %: ?data =perationI SU"" 6#7 V 6#7 F 6/7 F Tdata "ytesI 8 /yclesI ' AncodingI ' ) ) ' ) ' ) ' direct address AncodingI ' ) ) ' ) ' ' i

AncodingI ' ) ) ' ) ' ) ) immediate data /F%* % 2unctionI Swap nibbles within the accumulator DescriptionI S #> # interchanges the low and high?order nibbles 6four?bit fields7 of the accumulator 6bits <?) and bits M?(7. The operation can also be thought of as a four bit rotate instruction. @o flags are affected. A1ampleI The accumulator holds the value )/&+ 6'')))')'"7. The instruction S #> # leaves the accumulator holding the value &/+ 6)')'''))"7. =perationI S #> 6#<?)7 6#M?(73 6#M?(7 V 6#<?)7 "ytesI ' /yclesI ' AncodingI ' ' ) ) ) ' ) ) 2CE %: ;<(te= 2unctionI A1change accumulator with byte variable DescriptionI J/+ loads the accumulator with the contents of the indicated variable3 at the same time writing the original accumulator contents to the indicated variable. The source4destination operand can use register3 direct3 or register?indirect addressing. A1ampleI R) contains the address 8)+. The accumulator holds the value <2+ 6))''''''"7. Internal R#: location 8)+ holds the value M&+ 6)''')')'"7. The instruction J/+ #3 KR) will leave R#: location 8)+ holding the value <2+ 6))'''''' "7 and M&+ 6)''')')'"7 in the accumulator. 2CE %: n =perationI J/+ 6#7 6Rn7

"ytesI ' /yclesI ' 2CE %: direct =perationI J/+ 6#7 6direct7 "ytesI 8 /yclesI ' AncodingI ' ' ) ) ' r r r AncodingI ' ' ) ) ) ' ) ' direct address 2CE %: > i =perationI J/+ 6#7 66Ri77 "ytesI ' /yclesI ' AncodingI ' ' ) ) ) ' ' i 2CE+ %:> i 2unctionI A1change digit DescriptionI J/+D e1changes the low?order nibble of the accumulator 6bits <?)3 generally representing a he1adecimal or "/D digit7L with that of the internal R#: location indirectly addressed by the specified register. The high?order nibbles 6bits M?(7 of each register are not affected. @o flags are affected. A1ampleI R) contains the address 8)+. The accumulator holds the value <9+ 6))'')'')"7. Internal R#: location 8)+ holds the value M&+ 6)''')')'"7. The instruction J/+D #3 K R) will leave R#: location 8)+ holding the value M9+ 6)''')'')"7 and <&+ 6))'')')'"7 in the accumulator. =perationI J/+D

6#<?)7 66Ri7 <?)7 "ytesI ' /yclesI ' AncodingI ' ' ) ' ) ' ' i 2 # ;dest-<(te=: ;src-<(te= 2unctionI .ogical A1clusive =R for byte variables DescriptionI JR. performs the bitwise logical A1clusive =R operation between the indicated variables3 storing the results in the destination. @o flags are affected. The two operands allow si1 addressing mode combinations. hen the destination is the accumulator3 the source can use register3 direct3 register?indirect3 or immediate addressingL when the destination is a direct address3 the source can be accumulator or immediate data. "ote) hen this instruction is used to modify an output port3 the value used as the original port data will be read from the output data latch3 not the input pins. A1ampleI If the accumulator holds )/<+ 6''))))''"7 and register ) holds )##+ 6')')')')"7 then the instruction JR. #3 R) will leave the accumulator holding the value 9%+ 6)'')'))'"7. hen the destination is a directly addressed byte3 this instruction can complement combinations of bits in any R#: location or hardware register. The pattern of bits to be complemented is then determined by a mas! byte3 either a constant contained in the instruction or a variable computed in the accumulator at run?time. The instruction JR. >'3 T))'')))'" will complement bits &3 (3 and ) of output port '. 2 # %: n =perationI JR.8 6#7 V 6#7 ` 6Rn7 "ytesI '

/yclesI ' AncodingI ) ' ' ) ' r r r 2 # %: direct =perationI JR. 6#7 V 6#7 ` 6direct7 "ytesI 8 /yclesI ' 2 # %: > i =perationI JR. 6#7 V 6#7 ` 66Ri77 "ytesI ' /yclesI ' 2 # %: ?data =perationI JR. 6#7 V 6#7 Tdata "ytesI 8 /yclesI ' 2 # direct: % =perationI JR. 6direct7 V 6direct7 ` 6#7 "ytesI 8 /yclesI ' AncodingI ) ' ' ) ) ' ) ' direct address AncodingI ) ' ' ) ) ' ' i AncodingI ) ' ' ) ) ' ) ) immediate data AncodingI ) ' ' ) ) ) ' ) direct address

2 # direct: ?data =perationI JR. 6direct7 V 6direct7 ` Tdata "ytesI < /yclesI 8 AncodingI ) ' ' ) ) ) ' ' direct address immediate data Instruction /et /ummar( %rithmetic !,erations Mnemonic +escri,tion 5(te C(cle #DD #3 Rn #dd register to accumulator ' ' #DD #3 direct #dd direct byte to accumulator 8 ' #DD #3 KRi #dd indirect R#: to accumulator ' ' #DD #3 data #dd immediate data to accumulator 8 ' #DD/ #3 Rn #dd register to accumulator with carry flag ' ' #DD/ #3 direct #dd direct byte to # with carry flag 8 ' #DD/ #3 KRi #dd indirect R#: to # with carry flag ' ' #DD/ #3 Tdata #dd immediate data to # with carry flag 8 ' SU"" #3 Rn Subtract register from # with borrow ' ' SU"" #3 direct Subtract direct byte from # with borrow 8 ' SU"" #3KRi Subtract indirect R#: from # with borrow ' ' SU"" #3 data Subtract immediate data from # with borrow 8 ' I@/ # Increment accumulator ' ' I@/ Rn Increment register ' ' I@/ direct Increment direct byte 8 ' I@/ KRi Increment indirect R#: ' ' DA/ # Decrement accumulator ' ' DA/ Rn Decrement register ' ' DA/ direct Decrement direct byte 8 ' DA/ KRi Decrement indirect R#: ' ' I@/ D>TR Increment data pointer ' 8

:U. #" :ultiply # and " ' ( DI5 #" Divide # by " ' ( D# # Decimal adjust accumulator ' ' #ogic !,erations Mnemonic +escri,tion 5(te C(cle #@. #3 Rn #@D register to accumulator ' ' #@. #3 direct #@D direct byte to accumulator 8 ' #@. #3KRi #@D indirect R#: to accumulator ' ' #@. #3 Tdata #@D immediate data to accumulator 8 ' #@. direct3 # #@D accumulator to direct byte 8 ' #@. direct3 Tdata #@D immediate data to direct byte < 8 =R. #3 Rn =R register to accumulator ' ' =R. #3 direct =R direct byte to accumulator 8 ' =R. #3KRi =R indirect R#: to accumulator ' ' =R. #3 Tdata =R immediate data to accumulator 8 ' =R. direct3 # =R accumulator to direct byte 8 ' =R. direct3 Tdata =R immediate data to direct byte < 8 JR. #3 Rn A1clusive =R register to accumulator ' ' JR. # direct A1clusive =R direct byte to accumulator 8 ' JR. #3KRi A1clusive =R indirect R#: to accumulator ' ' JR. #3 Tdata A1clusive =R immediate data to accumulator 8 ' JR. direct3 # A1clusive =R accumulator to direct byte 8 ' JR. direct3 Tdata A1clusive =R immediate data to direct byte < 8 /.R # /lear accumulator ' ' />. # /omplement accumulator ' ' R. # Rotate accumulator left ' ' R./ # Rotate accumulator left through carry ' ' RR # Rotate accumulator right ' ' RR/ # Rotate accumulator right through carry ' ' S #> # Swap nibbles within the accumulator ' '

+ata Trans'er _7 :=5 #3 #// is not a valid instruction Mnemonic +escri,tion 5(te C(cle :=5 #3 Rn :ove register to accumulator ' ' :=5 #3 direct _7 :ove direct byte to accumulator 8 ' :=5 #3KRi :ove indirect R#: to accumulator ' ' :=5 #3 Tdata :ove immediate data to accumulator 8 ' :=5 Rn3 # :ove accumulator to register ' ' :=5 Rn3 direct :ove direct byte to register 8 8 :=5 Rn3 Tdata :ove immediate data to register 8 ' :=5 direct3 # :ove accumulator to direct byte 8 ' :=5 direct3 Rn :ove register to direct byte 8 8 :=5 direct3 direct :ove direct byte to direct byte < 8 :=5 direct3KRi :ove indirect R#: to direct byte 8 8 :=5 direct3 Tdata :ove immediate data to direct byte < 8 :=5 KRi3 # :ove accumulator to indirect R#: ' ' :=5 KRi3 direct :ove direct byte to indirect R#: 8 8 :=5 KRi3 Tdata :ove immediate data to indirect R#: 8 ' :=5 D>TR3 Tdata'9 .oad data pointer with a '9?bit constant < 8 :=5/ #3K# ; D>TR :ove code byte relative to D>TR to accumulator ' 8 :=5/ #3K# ; >/ :ove code byte relative to >/ to accumulator ' 8 :=5J #3KRi :ove e1ternal R#: 6$?bit addr.7 to # ' 8 :=5J #3KD>TR :ove e1ternal R#: 6'9?bit addr.7 to # ' 8 :=5J KRi3 # :ove # to e1ternal R#: 6$?bit addr.7 ' 8 :=5J KD>TR3 # :ove # to e1ternal R#: 6'9?bit addr.7 ' 8 >US+ direct >ush direct byte onto stac! 8 8 >=> direct >op direct byte from stac! 8 8 J/+ #3 Rn A1change register with accumulator ' ' J/+ #3 direct A1change direct byte with accumulator 8 ' J/+ #3KRi A1change indirect R#: with accumulator ' '

J/+D #3KRi A1change low?order nibble indir. R#: with # ' ' 5oolean -aria<le Mani,ulation *rogram and Machine Control Mnemonic +escri,tion 5(te C(cle /.R / /lear carry flag ' ' /.R bit /lear direct bit 8 ' SAT" / Set carry flag ' ' SAT" bit Set direct bit 8 ' />. / /omplement carry flag ' ' />. bit /omplement direct bit 8 ' #@. /3 bit #@D direct bit to carry flag 8 8 #@. /3 4bit #@D complement of direct bit to carry 8 8 =R. /3 bit =R direct bit to carry flag 8 8 =R. /3 4bit =R complement of direct bit to carry 8 8 :=5 /3 bit :ove direct bit to carry flag 8 ' :=5 bit3 / :ove carry flag to direct bit 8 8 #/#.. addr'' #bsolute subroutine call 8 8 ./#.. addr'9 .ong subroutine call < 8 RAT Return from subroutine ' 8 RATI Return from interrupt ' 8 #U:> addr'' #bsolute jump 8 8 .U:> addr'9 .ong jump < 8 SU:> rel Short jump 6relative addr.7 8 8 U:> K# ; D>TR Uump indirect relative to the D>TR ' 8 US rel Uump if accumulator is ,ero 8 8 U@S rel Uump if accumulator is not ,ero 8 8 U/ rel Uump if carry flag is set 8 8 U@/ rel Uump if carry flag is not set 8 8 U" bit3 rel Uump if direct bit is set < 8 U@" bit3 rel Uump if direct bit is not set < 8

U"/ bit3 rel Uump if direct bit is set and clear bit < 8 /U@A #3 direct3 rel /ompare direct byte to # and jump if not e-ual < 8 Mnemonic +escri,tion 5(te C(cle /U@A #3 Tdata3 rel /ompare immediate to # and jump if not e-ual < 8 /U@A Rn3 Tdata rel /ompare immed. to reg. and jump if not e-ual < 8 /U@A KRi3 Tdata3 rel /ompare immed. to ind. and jump if not e-ual < 8 DU@S Rn3 rel Decrement register and jump if not ,ero 8 8 DU@S direct3 rel Decrement direct byte and jump if not ,ero < 8 @=> @o operation ' '

%TM$# /$ I$/ !1 MIC !C!"T !##$ /

./D SA/TI=@ DAT#I.SI?

./D DAT#I. . 2re-uently3 an $)&' program must interact with the outside world using input and output devices that communicate directly with a human being. =ne of the most common devices attached to an $)&' is an ./D display. Some of the most common ./Ds connected to the $)&' are '918 and 8)18 displays. This means '9 characters per line by 8 lines and 8) characters per line by 8 lines3 respectively. Fortunately, a very popular standard exists which allows us to communicate with the vast majority of LCDs regardless of their manufacturer. The standard is referred to as HD the LCD. 44780 BACKGROUND The !"# standard re)uires * control lines as well as either or " +,- lines for !"#$, which refers to the controller chip which receives data from an external source %in this case, the "#&'( and communicates directly with

the data .us. The user may select whether the LCD is to operate with a /.it data .us or an "/.it data .us. +f a /.it data .us is used, the LCD will re)uire a total of ! data lines %* control lines plus the lines for the data .us(. The three control lines are referred to as EN, RS, and RW. The EN line is called 01na.le.0 This control line is used to tell the LCD that you are sending it data. To send data to the LCD, your program should first set this line high %'( and then set the other two control lines and,or put data on the data .us. 2hen the other lines are completely ready, .ring EN low %#( again. The '/# transition tells the !"# to ta3e the data currently found on the other control lines and on the data .us and to treat it as a command. lines for the data .us(. +f an "/.it data .us is used, the LCD will re)uire a total of '' data lines %* control lines plus the "

The RS line is the 04egister 5elect0 line. 2hen 45 is low %#(, the data is to .e treated as a command or special instruction %such as clear screen, position cursor, etc.(. 2hen 45 is high %'(, the data .eing sent is text data which should .e displayed on the screen. For example, to display the letter 0T0 on the screen you would set 45 high. The RW line is the 04ead,2rite0 control line. 2hen 42 is low %#(, the information on the data .us is .eing written to the LCD. 2hen 42 is high %'(, the program is effectively )uerying %or reading( the LCD. -nly one instruction %06et LCD status0( is a read command. 7ll others are write commands//so 42 will almost always .e low. Finally, the data .us consists of or " lines %depending on the mode of operation

selected .y the user(. +n the case of an "/.it data .us, the lines are referred to as D8#, D8', D89, D8*, D8 , D8&, D8:, and D8!. AN EXA !"E #ARDWARE CONF$GURA%$ON 7s we;ve mentioned, the LCD re)uires either " or '' +,- lines to communicate with. For the sa3e of this tutorial, we are going to use an "/.it data .us//so we;ll .e using '' of the "#&';s +,- pins to interface with the LCD. Let;s draw a sample psuedo/schematic of how the LCD will .e connected to the "#&'.

7s you can see, we;ve esta.lished a '/to/' relation .etween a pin on the "#&' and a line on the to the lines .y their !"# LCD. Thus as we write our assem.ly program to access !"# name as opposed to <#.', <#.9, etc. Let;s go ahead the LCD, we are going to e)uate constants to the "#&' ports so that we can refer and write our initial e)uates=

+50 $G6 *1.0 +51 $G6 *1.1 +52 $G6 *1.2 +53 $G6 *1.3 +54 $G6 *1.4 +55 $G6 *1.5 +5C $G6 *1.C +5H $G6 *1.H $" $G6 *3.H / $G6 *3.C F $G6 *3.5 +%T% $G6 *1 +aving established the above e-uates3 we may now refer to our I4= lines by their ((M$) name. 2or e1ample3 to set the R line high 6'73 we can e1ecute the following insutrctionI

/$T5 F E%"+#I". TE$ $" C!"T !# #I"$ 7s we mentioned a.ove, the 1> line is used to tell the LCD that you are ready for it to execute an instruction that you;ve prepared on the data .us and on the other control lines. >ote that the 1> line must .e raised,lowered .efore,after each instruction sent to the LCD regardless of whether that instruction is read or write, text or instruction. +n short, you must always manipulate 1> when communicating with the LCD. 1> is the LCD;s way of 3nowing that you are tal3ing to it. +f you don;t raise,lower 1>, the LCD doesn;t 3now you;re tal3ing to it on the other lines. Thus, .efore we interact in any way with the LCD we will always .ring the EN line high with the following instruction= /$T5 $" #nd once weCve finished setting up our instruction with the other control lines and data bus lines3 weCll always bring this line bac! lowI C# $" *rogramming Ti,) The ./D interprets and e1ecutes our command at the instant the $" line is brought low. If you never bring $" low3 your instruction will never be e1ecuted. #dditionally3 when you bring $" low and the ./D e1ecutes your instruction3 it re-uires a certain amount of time to e1ecute the command. The time it re-uires to e1ecute an instruction depends on the instruction and the speed of the crystal which is attached to the ((M$)Cs oscillator input.

CE$CII". TE$ 56/9 /T%T6/ !1 TE$ #C+ 7s previously mentioned, it ta3es a certain amount of time for each instruction to .e executed .y the LCD. The delay varies depending on the fre)uency of the

crystal attached to the oscillator input of the which is .eing executed.

!"# as well as the instruction

2hile it is possi.le to write code that waits for a specific amount of time to allow the LCD to execute instructions, this method of 0waiting0 is not very flexi.le. +f the crystal fre)uency is changed, the software will need to .e modified. 7dditionally, if the LCD itself is changed for another LCD which, although properly modified. 7 more ro.ust method of programming is to use the 06et LCD 5tatus0 command to determine whether the LCD is still .usy executing the last instruction received. The 06et LCD 5tatus0 command will return to us two tid.its of information? the information that is useful to us right now is found in D8!. +n summary, when we issue the 06et LCD 5tatus0 command the LCD will immediately raise D8! if it;s still .usy executing a command or lower D8! to indicate that the LCD is no longer occupied. Thus our program can )uery the LCD until D8! goes low, indicating the LCD is no longer .usy. 7t that point we are free to continue and send the next command. 5ince we will use this code every time we send an instruction to the LCD, it is useful to ma3e it a su.routine. Let;s write the code= F%ITJ#C+) /$T5 $" LStart ./D command C# / LItCs a command /$T5 F LItCs a read command M!- +%T%:?011h LSet all pins to 22 initially M!- %:+%T% LRead the return value @5 %CC.H:F%ITJ#C+ LIf bit M high3 ./D still busy C# $" L2inish the command !"# compati.le, re)uires more time to perform its operations, the program will not wor3 until it is

C# $T

F LTurn off R

for future commands

Thus3 our standard practice will be to send an instruction to the ./D and then call our F%ITJ#C+ routine to wait until the instruction is completely e1ecuted by the ./D. This will assure that our program gives the ./D the time it needs to e1ecute instructions and also ma!es our program compatible with any ./D3 regardless of how fast or slow it is. *rogramming Ti,) The above routine does the job of waiting for the ./D3 but were it to be used in a real application a very definite improvement would need to be madeI as written3 if the ./D never becomes anot busya the program will effectively ahang3a waiting for D"M to go low. If this never happens3 the program will free,e. =f course3 this should never happen and wonKt happen when the hardware is wor!ing properly. "ut in a real application it would be wise to put some !ind of time limit on the delay??for e1ample3 a ma1imum of 8&9 attempts to wait for the busy signal to go low. This would guarantee that even if the ./D hardware fails3 the program would not loc! up.

I"ITI%#IAI". TE$ #C+ 8efore you may really use the LCD, you must initiali@e and configure it. This is accomplished .y sending a num.er of initiali@ation instructions to the LCD. The first instruction we send must tell the LCD whether we;ll .e communicating with it with an "/.it or /.it data .us. 2e also select a &x" dot character font. These two options are selected .y sending the command *"h to the LCD as a command. 7s you will recall from the last section, we mentioned that the RS line must .e low if we are sending a command to the LCD. Thus, to send this *"h command to the LCD we must execute the following "#&' instructions=

SAT" A@ /.R RS :=5 D#T#3T<$h /.R A@ ./#.. #ITR./D *rogramming Ti,) The ./D command <$h is really the sum of a number of option bits. The instruction itself is the instruction 8)h 6a2unction seta7. +owever3 to this we add the values ')h to indicate an $?bit data bus plus )$h to indicate that the display is a two?line display. eCve now sent the first byte of the initiali,ation se-uence. The second byte of the initiali,ation se-uence is the instruction )Ah. Thus we must repeat the initiali,ation code from above3 but now with the instruction. Thus the ne1t code segment isI /$T5 $" C# / M!- +%T%:?0$h C# $" #C%## F%ITJ#C+

*rogramming Ti,) The command )Ah is really the instruction )$h plus )(h to turn the ./D on. To that an additional )8h is added in order to turn the cursor on. The last byte we need to send is used to configure additional operational parameters of the ./D. C# e must send the value )9h. / /$T5 $" M!- +%T%:?0Ch C# $" #C%## F%ITJ#C+ *rogramming Ti,) The command )9h is really the instruction )(h plus )8h to configure the ./D such that every time we send it a character3 the cursor position automatically moves to the right. So3 in all3 our initiali,ation code is as followsI I"ITJ#C+)

/$T5 $" C# / M!- +%T%:?38h C# $" #C%## F%ITJ#C+ /$T5 $" C# / M!- +%T%:?0$h C# $" #C%## F%ITJ#C+ /$T5 $" C# / M!- +%T%:?0Ch C# $" #C%## F%ITJ#C+ $T +aving e1ecuted this code the ./D will be fully initiali,ed and ready for us to send display data to it. C"EAR$NG %#E D$S!"A& 2hen the LCD is first initiali@ed, the screen should automatically .e cleared .y the !"# controller. However, it;s always a good idea to do things yourself so that you can .e completely sure that the display is the way you want it. Thus, it;s not a .ad idea to clear the screen as the very first opreation after the LCD has .een initialie@d. 7n LCD command exists to accomplish this function. >ot suprisingly, it is the command #'h. 5ince clearing the screen is a function we very li3ely will wish to call more than once, it;s a good idea to ma3e it a su.routine= C#$% J#C+)

/$T5 $" C# / M!- +%T%:?01h C# $" #C%## F%ITJ#C+ $T +ow that weCve written a a/lear Screena routine3 we may clear the ./D at any time by simply e1ecuting an #C%## C#$% J#C+. *rogramming Ti,) A1ecuting the a/lear Screena instruction on the ./D also positions the cursor in the upper left?hand corner as we would e1pect. F ITI". T$2T T! TE$ #C+ >ow we get to the real meat of what we;re trying to do= 7ll this effort is really so we can display text on the LCD. 4eally, we;re pretty much done. -nce again, writing text to the LCD is something we;ll almost certainly want to do over and over//so let;s ma3e it a su.routine. F IT$JT$2T) /$T5 $" /$T5 / M!- +%T%:% C# $" #C%## F%ITJ#C+ $T The F IT$JT$2T routine that we just wrote will send the character in the accumulator to the ./D which will3 in turn3 display it. Thus to display te1t on the ./D all we need to do is load the accumulator with the byte to display and ma!e a call to this routine. >retty easy3 huhb A '#E""O WOR"D' !ROGRA

>ow that we have all the component su.routines written, writing the classic 0Hello 2orld0 program//which displays the text 0Hello 2orld0 on the LCD is a relatively trivial matter. Consider= #C%## I"ITJ#C+ #C%## C#$% J#C+ M!- %:?KEK #C%## F IT$JT$2T M!- %:?K$K #C%## F IT$JT$2T M!- %:?K#K #C%## F IT$JT$2T M!- %:?K#K #C%## F IT$JT$2T M!- %:?K!K #C%## F IT$JT$2T M!- %:?K K #C%## F IT$JT$2T M!- %:?KFK #C%## F IT$JT$2T M!- %:?K!K #C%## F IT$JT$2T M!- %:?K K #C%## F IT$JT$2T M!- %:?K#K #C%## F IT$JT$2T M!- %:?K+K #C%## F IT$JT$2T The above a+ello orlda program should3 when e1ecuted3 initiali,e the ./D3 clear the orlda in the upper left?hand corner of the display. ./D screen3 and display a+ello CURSOR !OS$%$ON$NG

The a.ove 0Hello 2orld0 program is simplistic in the sense that it prints its text in the upper left/hand corner of the screen. However, what if we wanted to display the word 0Hello0 in the upper left/hand corner .ut wanted to display the word 02orld0 on the second line at the tenth characterA This sounds simple//and actually, it is simple. However, it re)uires a little more understanding of the design of the LCD. The !"# contains a certain amount of memory which is assigned to the !"# is stored in this memory, and the !"#

display. 7ll the text we write to the

su.se)uently reads this memory to display the text on the LCD itself. This memory can .e represented with the following 0memory map0=

Thus, the first character in the upper left/hand corner is at address ##h. The following character position %character B9 on the first line( is address #'h, etc. This continues until we reach the ':th character of the first line which is at address #Fh. However, the first character of line 9, as shown in the memory map, is at address #h. This means if we write a character to the last position of the first line and then write a second character, the second character will not appear on the second line. That is .ecause the second character will effectively .e written to address '#h//.ut the second line .egins at address #h.

Thus we need to send a command to the LCD that tells it to position the cursor on the second line. The 05et Cursor <osition0 instruction is "#h. To this we must add the address of the location where we wish to position the cursor. +n our example, we said we wanted to display 02orld0 on the second line on the tenth character position. 4eferring again to the memory map, we see that the tenth character position of the second line is address 7h. Thus, .efore writing the word 02orld0 to the LCD, we must send a 05et Cursor <osition0 instruction//the value of this command will .e "#h %the instruction code to position the cursor( plus the address 7h. "#h C 7h D C h. Thus sending the command C h to the LCD will position the cursor on the second line at the tenth character position=

/$T5 $" C# / M!- +%T%:?0C4h C# $" #C%## F%ITJ#C+ The above code will position the cursor on line 83 character '). To display a+elloa in the upper left?hand corner with the word a orlda on the second line at character position ') just re-uires us to insert the above code into our e1isting a+ello results in the followingI #C%## I"ITJ#C+ #C%## C#$% J#C+ M!- %:?KEK #C%## F IT$JT$2T M!- %:?K$K orlda program. This

#C%## F IT$JT$2T M!- %:?K#K #C%## F IT$JT$2T M!- %:?K#K #C%## F IT$JT$2T M!- %:?K!K #C%## F IT$JT$2T /$T5 $" C# / M!- +%T%:?0C4h C# $" #C%## F%ITJ#C+ M!- %:?KFK #C%## F IT$JT$2T M!- %:?K!K #C%## F IT$JT$2T M!- %:?K K #C%## F IT$JT$2T M!- %:?K#K #C%## F IT$JT$2T M!- %:?K+K #C%## F IT$JT$2T

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1low Chart)-

Start

Initiali,e the I4= >orts3 ./D3 5ariables3 Timers and Interruption

Display :essage on ./D

D Is #ny *eyb @o

Is *ey E :easure !eyb

Nes #

Is *ey E find speed !eyb

Nes

"

#
Is Transmitter *ey E Anable the Reset !eyb Nes Reset the System >arameters

Start the wait timer @o

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@o

Anable Receiver

ait for the return >ulse

Is a 5alid return pulse

@o

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:easure the time between pulse transmission 0 reception 2ind out the distance in cm

Display the Distance on ./D

"

Anable the Transmitter

Start the wait timer

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ait for the return >ulse

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:easure the time between pulse transmitted 0 received

2ind out the speed in mtr 4sec

Display the Speed on ./D

Updated $4'M4%$ For4ing Fith /te,,er Motors

=nline Tutorial T'

This page is divided into several sections. Choose a section to jump to from the list, or scroll down to view the entire document. E E E E E E E +ntroduction / 7 general introduction to this document. 5ources / 2here to find stepper motors. -peration / How stepper motors wor3. Characteristics / Common characteristics of stepper motors. Types / $nipolar vs. 8ipolar motor types of stepper motors. Translators / 1xample translator circuits. 5oftware examples / 1xample code snippets for controlling stepper motors.

$N%RODUC%$ON + am .y no means an expert on stepper motors. + have not completed my education, so + do not 3now all of the mathematics or mechanics that go into the design and operation of stepper motors. 2hat + do 3now is what + have learned from my experience with these electro/mechanical wonders. This document willout line sources that carry stepper motors and how to control them manually %with discrete logic(, with a microcontroller, and with computer control.

W#ERE %O F$ND S%E!!ER O%ORS 5tepper motors can .e found in almost any piece of electro/mechanical e)uipment. From my personal experiences, good sources for stepper motors include= 5urplus dot/matrix printers +f you find one of these at a swap meet, surplus store, or garage sale for a good

price, .uy itF They usually contain at least 9 motors, sometimes with optical shaft encoders attached to the motorsF 7lso a good source for matching gears and toothed .elts. 7s a general rule, larger printers will have larger, more powerful stepper motors in them. -ld floppy dis3 drives These usually contain at least ' stepper motor, and if you;re fortunate, possi.ly a driver +C that can .e salvaged and re/used in your own projects. 7long with the motor you will get some optical interrupter units used .y the drive to sense the state of the write/protect ta.s and to index the dis3. 5urplus stores These places .uy surplus from others and sell it to the pu.lic, often at great prices. The average price for a small to medium stepper motor is usually around G&.##. Hail -rder Companies Iou can find surplus motors or even new, pac3aged units. >aturally the new units are going to cost more, .ut this may save time and money if you;re .uilding e)uipment with the motors that will .e used at more than a 0ho..y0 level. For general tin3ering and small scale ro.otics, used motors will wor3 just fine.

#OW S%E!!ER O%ORS WORK 2e;ve all experimented with small 0ho..y motors0, or free/spinning DC motors. Have you ever tried to position something accurately with oneA +t can .e pretty difficult. 1ven if you get the timing just right for starting and stopping the motor, the armature does not stop immediately. DC motors have a very gradual acceleration and deceleration curves? sta.ili@ation is slow. 7dding gearing to the motor will help to reduce this pro.lem, .ut overshoot is still present and will throw off the anticipated stop position. The only way to effectively use a DC motor for precise positioning is to use a servo. 5ervos usually implement a small DC motor, a feed.ac3 mechanism %usually a potentiometer with attached to the shaft .y gearing or other means(, and a control circuit which compares the position of the motor with the desired position, and moves the motor accordingly. This can get fairly complex and expensive for most ho..y applications. 5tepper motors, however, .ehave differently than standard DC motors. First of all, they cannot run freely .y themselves. 5tepper motors do as their name suggests // they 0step0 a little .it at a time.5tepper motors also differ from DC motors in their tor)ue/speed relationship. DC motors generally are not very good at producing high tor)ue at low speeds, without the aid of a gearing mechanism. 5tepper motors, on the other hand, wor3 in the opposite manner. They produce the highest tor)ue at lowspeeds. 5tepper motors also have another characteristic, holding torque, which is not present in DC motors. Holding tor)ue allows a stepper motor to hold its position firmly when not turning. This can .e useful for applications where the motor may .e starting and stopping, while the force acting against the motor remains present. This eliminates the need for a mechanical .ra3e mechanism. 5teppers don;t simply respond to a cloc3 signal, they have several windings which need to .e energi@ed in the correct se)uence .efore the motor;s shaft will rotate. 4eversing the order of the se)uence will cause the motor to rotate the other way. +f the control signals are not sent in the correct order, the motor will not turn properly. +t may simply .u@@ and not move, or it may actually turn, .ut in a rough or jer3y manner. 7 circuit which is responsi.le for converting step and direction signals into winding energi@ation patterns is called a translator. Host stepper motor control systems include adriver in addition to the translator, to handle the current drawn .y the motor;s windings.

Figure 1.1 - A typical translator / driver connection

A basic example of the "translator + driver" type of configuration. Notice the separate voltages for logic and for the stepper motor. Usually the motor will require a different voltage than the logic portion of the system. Typically logic voltage is +5 Vdc and the stepper motor voltage can range from +5 Vdc up to about +48 Vdc. The driver is also an "open collector" driver, wherein it takes its outputs to GND to activate the motor's windings. Most semiconductor circuits are more capable of sinking(providing a GND or negative voltage) than sourcing (outputting a positive voltage).

CO ON C#ARAC%ER$S%$CS OF S%E!!ER O%ORS( 5tepper motors are not just rated .y voltage. The following elements characteri@e a given steppermotor= Joltage 5tepper motors usually have a voltage rating. This is either printed directly on the unit, or is specified in the motor;s datasheet. 1xceeding the rated voltage is sometimes necessary to o.tain the desired tor)ue from a given motor, .ut doing so may produce excessive heat and,or shorten the life of the motor. 4esistance 4esistance/per/winding is another characteristic of a stepper motor. This resistance will determine current draw of the motor, as well as affect the motor;s tor)ue curve and maximum operating speed. Degrees per step This is often the most important factor in choosing a stepper motor for a given application. This factor specifies the num.er of degrees the shaft will rotate for each full step. Half step operation of the motor will dou.le the num.er of steps,revolution, and cut the degrees/per/step in half. For unmar3ed motors, it is often possi.le to carefully count, .y hand, the num.er of steps per revolution of the motor. The degrees per step can .e calculated .y dividing *:# .y the num.er of steps in ' complete revolution Common degree,step num.ers include= #.!9, '.", *.:, !.&, '&, and even K#. Degrees per step is often referred to as the resolution of the motor. 7s in the case of an unmar3ed motor, if a motor has only the num.er of steps,revolution printed on it, dividing *:# .y this num.er will yield the degree,step value.

%&!ES OF S%E!!ER O%ORS 5tepper motors fall into two .asic categories= <ermanent magnet and varia.le reluctance. The type of motor determines the type of drivers, and the type of translator used. -f the permanent magnet stepper motors, there are several 0su.flavors0 availa.le. These include the $nipolar, 8ipolar, and Hultiphase varieties.

E !er)anent

a*net Stepper

otors

$nipolar 5tepper Hotors $nipolar motors are relatively easy to control. 7 simple '/of/;n; counter circuit can generate the proper stepping se)uence, and drivers as simple as ' transistor per winding are possi.le with unipolar motors. $nipolar stepper motors are characteri@ed .y their center/tapped windings. 7 common wiring scheme is to ta3e all the taps of the center/tapped windings and feed them CHJ %Hotor voltage(. The driver circuit would then ground each winding to energi@e it.

Figure 2.1 - A typical unipolar stepper motor driver circuit. Note the 4 back EMF protection diodes.

$nipolar stepper motors are recogni@ed .y their center/tapped windings. The num.er of phases is twice the num.er of coils, since each coil is divided in two. 5o the diagram .elow %Figure *.'(, which has two center/tapped coils, represents the connection of a /phase unipolar stepper motor.

Figure 3.1 - Unipolar stepper motor coil setup (le t! and "-phase drive pattern (ri#ht!.

+n addition to the standard drive se)uence, high/tor)ue and half/step drive se)uences are also possi.le. +n the high/tor)ue se)uence, two windings are active at a time for each motor step. This two/winding com.ination yields around '.& times more tor)ue than the standard se)uence, .ut it draws twice the current. Half/stepping is achieved .y com.ining the two se)uences. First, one of the windings is activated, then two, then one, etc. This effectively dou.les the num.er of steps the motor will advance for each revolution of the shaft, and it cuts the num.er of degrees per step in half. Full-stepping animation Half-stepping animation

Figure 4.1 - $%o-phase steppin# se&uence (le t! and hal -step

se&uence (ri#ht!. Click on the links above the figure to see animated demonstrations.

8ipolar 5tepper Hotors $nli3e unipolar stepper motors, 8ipolar units re)uire more complex driver circuitry. 8ipolar motorsare 3nown for their excellent si@e,tor)ue ratio, and provide more tor)ue for their si@e than unipolar motors. 8ipolar motors are designed with separate coils that need to .e driven in either direction %the polarity needs to .e reversed during operation( for proper stepping to occur. This presents a driver challenge. 8ipolar stepper motors use the same .inary drive pattern as a unipolar motor, only the ;#; and ;'; signals correspond to the polarity of the voltage applied to the coils, not simply ;on/off; signals. Figure &.' shows a .asic /phase .ipolar motor;s coil setup and drive se)uence.

Figure 5.1 - 'ipolar stepper motor coil setup (le t! and drive pattern (ri#ht!.

7 circuit 3nown as an 0H/.ridge0 %shown .elow( is used to drive 8ipolar stepper motors. 1ach coil of the stepper motor needs its own H/.ridge driver circuit. Typical .ipolar steppers have leads, connected to two isolated coils in the motor. +Cs specifically designed to drive .ipolar steppers %or DC motors( are availa.le %<opular are the L9K!,9K" series from 5T Hicroelectronics, and the LHD'"T9 & from >ational 5emiconductor(. $sually these +C modules only contain a single H/.ridge circuit inside of them, so two of them are re)uired for driving a single .ipolar motor. -ne pro.lem with the .asic %transistor( H/.ridge circuit is that with a certain com.ination of input values %.oth ;';s( the result is that the power supply feeding the motor .ecomes shorted .y the transistors. This could cause a situation where the transistors and,or power supply may .e destroyed. 7 small L-4 logic circuit was added in figure :.' to 3eep .oth inputs from .eing seen as ;';s .y the transistors. 7nother characteristic of H/.ridge circuits is that they have electrical 0.ra3es0 that can .e applied to slow or even stop the motor from spinning freely when not moving under control .y the driver circuit. This is accomplished .y essentially shorting the coil%s( of the motor together, causing any voltage produced in the

coils .y during rotation to 0fold .ac30 on itself and ma3e the shaft difficult to turn. The faster the shaft is made to turn, the more the electrical 0.ra3es0 tighten.

Figure 6.1 - A typical (-'rid#e circuit. $he 4 diodes clamp inductive kickback.

E +aria,-e Re-uctance Stepper otors 5ometimes referred to as Hybrid motors, varia.le reluctance stepper motors are the simplest to control over other types of stepper motors. Their drive se)uence is simply to energi@e each of the windings in order, one after the other %see drive pattern ta.le .elow( This type of stepper motor will often have only one lead, which is the common lead for all the other leads. This type of motor feels li3e a DC motor when the shaft is spun .y hand? it turns freely and you cannot feel the steps. This type of stepper motor is not permanently magneti@ed li3e its unipolar and .ipolar counterparts.

Figure 7.1 - )ariable reluctance stepper motor coil setup (le t! and drive pattern (ri#ht!.

EXA !"E %RANS"A%OR C$RCU$%S +n this section, + will show examples of .asic stepper motor translation circuits. >ot all of these examples have .een tested, so .e sure to prototype the circuit .efore soldering anything. Figure ".' illustrates the simplest solution to generating a one/phase drive se)uence. For unipolar stepper motors, the circuit in Figure 9.', or for .ipolar stepper motors, the circuit in Figure :.' can .e connected to the outputs of this circuit to provide a complete translator C driver solution. This circuit is limited in that it cannot reverse the direction of the motor. This circuit would .e most useful in applications where the motor does not need to change directions.

Figure 8.1 - A simple* sin#le direction* sin#le phase drive translator. Figure K.' is an translator for two/phase operation. + have seen this circuit many places, .ut + .elieve it originated from The Robot Builders Bonan!a .oo3, .y 6ordon HcCom.. + have used this circuit in the past and seem to recall that it had a pro.lem. This may not .e the case .ut + thin3 when you reverse direction and continue stepping, the motor will advance ' more step in the previous direction it was going .efore responding. 7s always, prototype this circuit to .e sure it will wor3 for your application .efore you .uild anything with it.

Figure 9.1 - A simple* bidirectional* t%o-phase drive stepper motor translator circuit. There are several standard stepper motor translation circuits which use discrete logic +Cs. 8elow you will find yet another one of these. The circuit in Figure '#.' has not .een tested .ut theoretically should wor3 without pro.lems.

Figure 10.1 - Another e+ample o a t%o-phase drive translator circuit* this time usin# a multiple+er.

CON%RO" SOF%WARE EXA !"ES 8elow you will find some small pieces of code, mostly in C,CCC, some in 7ssem.ly language for various processors and microcontrollers. This code is .y no means complete, .ut is provided only to give a .asic understanding of the software involved in controlling stepper motors .oth with and without the use of a hardware translator circuit. Wor.s o/ caution( 2hen ma3ing connections to either a <C parallel port, or +,- pins of a microcontroller, .e sure to isolate the motor well. High voltage spi3es of several hundered volts are possi.le as .ac3 1HF from stepper motor coils. 7lways use clamping diodes to short these spi3es .ac3 to the motor;s power .us. The use of optical isolation devices %optoisolators( will add yet another layer or protection .etween the delicate control logic and the high/voltage potentials which may .e present in the power output stage. 2henever possi.le, use separate power supplies for the motor and the translator , microcontroller. This further reduces the chance of destructive voltages reaching the controller, and reduces or eliminates power supply noise that may .e introduced .y the motor. +f you;re using a computer that has a parallel port as part of its on.oard +,-, you may want to consider purchasing a parallel port card to use instead. +;ve seen them for as little as GK.KK at

Fry;s 1lectronics and other computer stores. >ot only does this reduce the ris3 of permanently damaging or destroying your mother.oard %it happened to a friend of mineF(, .ut it will also allow you to experiment without the need for swapping ca.les or flipping a switch.ox when you want to use your parallel printer, since your experiments won;t .e sharing its port. +t is much cheaper to throw out a G'#.## parallel port card than it is to replace your mother.oardF Complete 5oftware Control= $nder complete software control, there is no translator circuit external to the <arallel port or microcontroller. This scheme reduces parts count, component cost, and ma3es for simpler .oard design. -n the other hand, it places the responsi.ility of generating all of the se)uencing signals on the software. +f the <C or microcontroller is not fast enough %due to code inefficiency or slow processor speed(, or too many motors are driven simultaneously, things can .egin to slow down. +nterrupts and other system events can plague the control software more in this case. Despite the downfalls of addressing a stepper motor directly in this manner, it is definitely the easiest and most straightforward approach to controlling a stepper motor. This method of controlling a motor can also .e useful where the hardware is not critical at first and a simple interface is needed to allow more time to .e spent on the development of the software .efore the hardware is refined.

$nless otherwise indicated, all material on this site is the original wor3 of Mason Mohnson. Copyright N 'KK" Mason Mohnson

Return to eio's Home Page or view Arti !es"Reviews# $r%er &n'ormation# (vents# Hot )ea!s# Forums# )is ussion *rou+s# ,ee-!. /+e ia!s# 0ont1!. /+e ia!s# /+e ia!s# &nventor.# Resour es# 99 2ent Page or (30ai! us

/IR/UIT

=R*I@B =2 STA>>AR :=T=R /=@TR=..

In this project when we interface the data from the computer then firstly we interface the circuit with the optocoupler. In optocoupler circuit we use ic $'M optocoupler. +ere we use four optocoupler with this circuit. =utput of the optpcoupler is negative. So to convert this negative output to the positive we use one inverter ic. In this project we use ic ()(% as a inverter. >in no <3&3M3%3'' is the input pin and pin no 83(393')3 '8 is the output pin. . from the output pin we interface the transistor circuit. +ere we use @>@ transistor. Amitter of the @>@ transistor is connected to the negative voltage. /ollector of the @>@ transistor is connected to the coil of the stepper motor . +ere we use total four transistors . collector of the transistor is connected to the each coil of the stepper motor. @ow with the help of the

cinclude 6reg&'1a.I@/7

./DRD#T# lcdRen lcdRrw lcdRrs !ey' output 2.#B flag) >U.S. >U.S+ desRcontr org ))))h ljmp main e-u bit bit bit

e-u >8.& >8.9 >8.M bit

>)

p8.) bit p<.9

e-u bit 88h 8<h e-u

8)h 2.#B.)

e-u

82h

org )))<h reti org )))bh reti org ))'<h reti org ))'bh

reti org ))8<h reti mainI mov psw3T))h mov sp3T)M)h mov tmod3T)'h mov tcon3T))h mov scon3T))h mov ie3T)$h mov ip3T)$h mov p)3T))h mov p'3T)ffh mov p83T)ffh mov p<3T)ffh mov delayr)3T))h mov delayr'3T))h mov >U.S.3T))h mov >U.S+3T))h clr lcdRrs

clr lcdRrw clr lcdRen clr flag)

lcall DA.#N(' lcall DA.#N(' lcall I@ITR./D lcall /.RR./D mov dptr3T:SB) lcall .I@AR' mov dptr3T:SB' lcall .I@AR8 lcall DA.#N(' lcall DA.#N(' "AB'I lcall DA.#N(' jb !ey'3"AB' lcall DA.#N(' jb !ey'3"AB' "ABI

:=5 T+)3T) :=5 T.)3T)

pulseI setb p<.) mov r'3T'8 djn, r'3c clr p<.) mov r'3T& djn, r'3 djn, r83 pulse setb tr) clr p<.8 mov r83T8) djn, r83c setb p<.8 lp8I jb p<.'3lp' clr tr) mov dptr3T:SB8 lcall .I@AR8

lcall DA.#N(' lcall DA.#N(' mov r)3T.) mov r'3T+) mov r83T&$ mov r<3T) call UDI5'9 clr c mov a3r) add a3T'$d mov r)3a

mov a3r' addc a3T)d mov r'3a

mov >U.S+3r' mov >U.S.3r) call disp' lcall DA.#N(' lcall DA.#N(' clr output

mov p'3T)ffh jmp beg' lp'I mov a3th) cjne a3T'Mh3lp8 mov dptr3T:SB< lcall .I@AR8 setb output n1tRupI jb flag)3n1tRdn mov inc a cjne a3T8))d3n1tRstep setb flag) sjmp n1tRstep n1tRdnI jnb flag)3n1tRup mov dec a cjne a3T)d3n1tRstep clr flag) sjmp n1tRstep a3desRcontr a3desRcontr

n1tRstepI mov anl desRcontr3a a3T)<h

cjne a3T<d3n1tRstep' mov p'3T<d n1tRstep'I cjne a3T8d3n1tRstep8 mov p'3T9d n1tRstep8I cjne a3T'd3n1tRstep< mov p'3T'8d n1tRstep<I cjne a3T)d3n1tRstep( mov p'3T%d n1tRstep(I lcall DA.#N(' lcall DA.#N(' jmp beg UDI5'9I mov rM3T) mov r93T)

mov "3T'9 divRloopI mov a3rM divR'I mov a3r( rlc a mov r(3a mov a3r& rlc a mov r&3a djn, "3divRloop mov a3r& mov r'3a mov a3r( mov r)3a mov a3rM mov r<3a mov a3r9 mov r83a ret +e18"/DI

:=5 R<3T))D :=5 R(3T))D :=5 R&3T))D :=5 R93T))D :=5 RM3T))D :=5 "3T')D :=5 #3R8 DI5 #" :=5 R<3" :=5 "3T') DI5 #" :=5 R(3" :=5 R&3# /U@A R'3T)+3+IB+R"NTA SU:> A@DD +IB+R"NTAI :=5 #3T9 #DD #3R< :=5 "3T') DI5 #"

:=5 R<3" #DD #3T& #DD #3R( :=5 "3T') DI5 #" :=5 R(3" #DD #3T8 #DD #3R& :=5 "3T') DI5 #" :=5 R&3" /U@A R93T))D3#DDRIT SU:> /=@TI@UA #DDRITI #DD #3R9 /=@TI@UAI :=5 R93# DU@S R'3+IB+R"NTA :=5 "3 T')D :=5 #3R9 DI5 #"

:=5 R93" :=5 RM3# A@DDI ret DIS>'I mov r'3>U.S+ mov r83>U.S. ./#.. +AJ8"/D :=5 dp'3r< :=5 dp83r( :=5 dp<3r& mov ./DRD#T#3T)cch lcall /=::#@DR"NTA #DD a3T<)h mov ./DRD#T#3a lcall D#T#R"NTA mov ./DRD#T#3T)cdh lcall /=::#@DR"NTA mov a3dp8 #DD a3T<)h mov ./DRD#T#3a

lcall D#T#R"NTA mov ./DRD#T#3T)ceh lcall /=::#@DR"NTA mov ./DRD#T#3a lcall D#T#R"NTA mov a3desRcontr

mov b3T'$d mul ab

mov r'3b mov r83a ./#.. +AJ8"/D :=5 dp(3r< :=5 dp&3r( :=5 dp93r& :=5 dpM3r9 mov ./DRD#T#3T)c<h lcall /=::#@DR"NTA mov a3dpM #DD a3T<)h mov ./DRD#T#3a

lcall D#T#R"NTA mov ./DRD#T#3T)c(h lcall /=::#@DR"NTA mov a3dp9 #DD a3T<)h mov ./DRD#T#3a lcall D#T#R"NTA mov ./DRD#T#3T)c&h lcall /=::#@DR"NTA mov a3dp& #DD a3T<)h mov ./DRD#T#3a lcall D#T#R"NTA mov ./DRD#T#3T)c9h lcall /=::#@DR"NTA mov ./DRD#T#3TC.C lcall D#T#R"NTA mov ./DRD#T#3T)cMh lcall /=::#@DR"NTA mov a3dp(

#DD a3T<)h mov ./DRD#T#3a lcall D#T#R"NTA ret .I@AR'I mov ./DRD#T#3T)$)h

lcall /=::#@DR"NTA lcall DA.#N' lcall ret .I@AR8I mov ./DRD#T#3T)c)h RITAR:SB

lcall /=::#@DR"NTA lcall DA.#N' lcall ret I@ITR./DI mov ./DRD#T#3T))h RITAR:SB

lcall /=::#@DR"NTA lcall DA.#N'

mov

./DRD#T#3T))h

lcall /=::#@DR"NTA lcall DA.#N' mov ./DRD#T#3T)<$h

lcall /=::#@DR"NTA lcall DA.#N' mov ./DRD#T#3T)<$h

lcall /=::#@DR"NTA lcall DA.#N' mov ./DRD#T#3T)<$h

lcall /=::#@DR"NTA lcall DA.#N' mov ./DRD#T#3T)<$h

lcall /=::#@DR"NTA lcall DA.#N' mov ./DRD#T#3T))$h

lcall /=::#@DR"NTA lcall DA.#N' mov ./DRD#T#3T))ch

lcall /=::#@DR"NTA

lcall DA.#N' mov ./DRD#T#3T))9h

lcall /=::#@DR"NTA lcall DA.#N' ret /.RR./DI mov ./DRD#T#3T))'h

lcall /=::#@DR"NTA lcall DA.#N' ret RITAR:SBI mov movc cjne ret RITAR/=@TI mov ./DRD#T#3a a3T))h a3Ka;dptr a3TCcC3 RITAR/=@T

lcall D#T#R"NTA inc ljmp dptr RITAR:SB

/=::#@DR"NTAI clr lcdRrs

lcall DA.#N ljmp /:D')

D#T#R"NTAI setb lcdRrs

lcall DA.#N /:D')I clr lcdRrw

lcall DA.#N setb lcdRen

lcall DA.#N clr lcdRen

lcall DA.#N(' ret DA.#NI mov DA.I djn, ret delayr)3DA. delayr)3T')d

DA.#N'I mov mov DA.#N')I djn, djn, ret DA.#N('I mov mov D.>(')I djn, djn, ret :SB)I db :SB'I db :SB8I db :SB<I db CUltrasonic RadarcC CDAS.; DIS. :etercC CDe Di cC delayr)3D.>(') delayr'3D.>(') delayr)3T)d delayr'3T'&d delayr)3DA.#N') delayr'3DA.#N') delayr)3T)d delayr'3T8)d

C Search Range cC

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