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VeriBest FPGA Synthesis VHDL Reference Manual

VeriBest FPGA Synthesis VHDL Reference Manual

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Published by: dientuspktv on Oct 08, 2009
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05/07/2013

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VeriBest FPGA SynthesisVHDL Reference Manual
VB 98.0 ReprintDLA029300
 
ii • VeriBest FPGA Synthesis VHDL Reference Manual
Warranties and Liabilities
All warranties given by VeriBest, Inc. (hereinafter collectively called VeriBest), are set forth in the Software LicenseAgreement, and nothing stated in, or implied by, this document or its contents shall be considered or deemed a modifica-tion or amendment of such warranties.The information and the software discussed in this document are subject to change without notice and should not be con-strued as commitments by VeriBest. VeriBest assumes no responsibility for any errors that may appear in this document.The software discussed in this document is furnished under a license and may be used or copied only in accordance withthe terms of this license.
RESTRICTED RIGHTS LEGEND
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of theRights in Technical Data and Computer Software clause at DFARS 252.227-7013 or subparagraphs (c)(1) and (2) ofCommercial Computer Software -- Restricted Rights at 48 CFT 52.227-19, as applicable.Reprinted with permission -- rights reserved under the Copyright Laws of the United States.Synopsys, Inc., San Jose, CA and VeriBest, Inc., Boulder, CO
Trademarks
VeriBest® is a registered trademark of VeriBest Incorporated.VeriBest FPGA Synthesis is a trademark of VeriBest Incorporated.Synopsys, the Synopsys logo, BiNMOS-CBA, CMOS-CBA, COSSAP, DESIGN (ARROWS), DesignPower,dont_use, ExpressModel, LM-1000, LM-1200, Logic Modeling, the Logic Modeling logo, ModelAccess, Model-Tools, SmartLicense, SmartLogic, SmartModel, SmartModels, SNUG, SOLV-IT!, SourceModel Library, StreamDriven Simulator, Synopsys VHDL Compiler, Synthetic Designs, and Synthetic Libraries are registered trademarksof Synopsys, Inc.Behavioral Compiler, CBA Design System, characterize, Compiled Designs, Cyclone, Data Path Architect, DataPath Express, DC Expert, DC Professional, Design Analyzer, Design Compiler, DesignSource, DesignTime,DesignWare, DesignWare Developer, dont_touch, dont_touch_network, ECL Compiler, Falcon Interface, Floor-plan Manager, FoundryModel, FPGA Compiler, FPGA Express, Frame Compiler, General Purpose Post-Proces-sor, GPP, HDL Advisor, HDL Compiler, Integrator, Interactive Waveform Viewer, Library Compiler, LM-1400, LM-700, LM-family, Logic Model, Memory Architect, ModelSource, ModelWare, MS-3200, MS-3400, PLdebug, Prime-Time, Shadow Debugger, Shortcut, Silicon Architects, SimuBus, SmartCircuit, SmartModel Windows, Source-Level Design, SourceModel, SWIFT, SWIFT Interface, Synopsys Graphical Environment, Test Compiler, TestCompiler Plus, Test Manager, TestBench Manager, TestSim, 3-D Debugging, VHDL System Simulator, Visualyze,VSS Expert, and VSS Professional are trademarks of Synopsys, Inc.In-Sync and LEARN-IT! are service marks of Synopsys, Inc.Other brands and product names are trademarks of their respective owners.No sponsorship or affiliation of any kind is implied in this manual by reference to brand names of other companies.
 
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Table of Contents
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