In the name of God Digital Logic Shahid Beheshti University fall semester 2011 ModelSim 6.

5 Brief Tutorial

Here are some tips for you to get used to Verilog Language and ModelSim 6.5 environment. After Installing ModelSim go to crk folder and run MentorKG then If its your first time opening ModelSim or if you encounter problems with licenses, you can run the license wizard: Start > All Programs > ModelSim SE > Licensing Wizard. Choose install a new license and select the file LICENSE.TXT in crk Folder, you must see a congratulation message that you cracked successfully! Its time to see different parts of modelsim, well go through it step by step with and example of designing a full adder module, Ill explain important part to you when we encountered them. First youll see something like the picture below, start by choosing new Project, name it fullAdder:

ok, now choose new file, name it whatever you like, consider to choose Verilog, the default is VHDL, now youll see your file and the status is ? it means it didnt compile yet,

first of all lets sharpen our tools by choosing right component in modelSim, so go to view tab and be sure the Library, Objects , Project , Transcript and Wave are selected.

Library: A directory that contains compiled design units, such as modules. Projects: A collection of various files for designs under test, such as Verilog source files, local working libraries, references to resource libraries, and simulation configuration (*.mpf files). Objects: is where you can find you variables, input outputs, etc. Wave: Here you can see the input/outputs of your module in waveform. Transcript: this tool will allow you to execute your commands by typing (something like command prompt in window) e.g. instead of click a file to compile you can type
vlog work [working library] [filename.v] Example: vlog work work fullAdder.

Thats enough till now, lets start coding :-D Here you can see a full adder:

go to Project component and double click the Verilog file to change it

we want to create a fullAdder Module.

I wrote code and name it FullAdder.v and I explained different code part by commenting it, if you want to use my code instead of creating new file you can choose add existing file and choose my file, you must then compile that, but I strongly suggest you for first time write your code on your own to get familiar with Verilog.

ok, go to project and compile the file, if your code doesnt have compile error youll see a check mark in status.

Note: After any change in your code you must save it then compile it, it wont save automatically, after you type use ctl+s shortcut key then recompile it.

Consider that when you compiled a module correctly it will be added to your Work library with Module name you defined in your code here is: fullAdder Well then, time to simulate In simulate tab click start simulation

in work library find fullAdder Module

Click Ok, now in Object Component you must see all of you inputs and outputs to and from module

we want to see the waveform of these signals so by right clicking and: Add->To wave->Signal in Regions Youll add all signals(if you want to select some signals you can choose your signals and then choose selected signals(for example sometimes you just interested in outputs) Now they are added in wave

HiZ means high impedance, because we didnt set any input yet. X in output means it doesnt have any value yet Next step we should set the inputs, Force values: Force follows this type: Force [variable] [value] [time] value means the constant you want to set. time means after how much time change will occur. So here I set these
force a 1 force b 0 force b 1 100 ns force Cin 1

Now its time to run, so from time 0 to time 100 the outputs should be: S = 0 , Cout = 1

From time 100 to 500 the outputs should be: S = 1, Cout = 1 (times are in nano second scale by using ns suffix) to run simply type:
Run 500 ns

NOTE: when you type run itll not start from 0 time , itll start from current time, so after previous run if I type run 120 wave form will show you 500 to 620 .In general after run when you type anything itll effect the changes after that time For example here If I write this:
force a 0 50 ns force b 0 run 120

Ill see this:

Note: if you want to restart all waves and back to time zero with HiZ simply type : restart f
reference : Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science
Instructor: Dr.Abbaspour TA: Aryan Yaghoubian www.sites.google.com/site/sbudigitalogic