Bay ging K thut Vi x l

Ngnh in t-Vin thng i hc Bch khoa Nng ca H Vit Vit, Khoa CNTT-TVT

Ti liu tham kho [1] K thut vi x l, Vn Th Minh, NXB Gio dc, 1997 [2] K thut vi x l v Lp trnh Assembly cho h vi x l, Xun Tin, NXB Khoa hc & k thut, 2001

Chng 3 Vi x l 8088-Intel 3.1 Kin trc v hot ng ca 8088 - Nguyn l hot ng - S khi chc nng 3.2 Cu trc thanh ghi ca 8088 3.3 Phng php qun l b nh 3.4 M t tp lnh Assembly

Nguyn l hot ng ca mt b vi x l

Ly - Gii m - Thc hin lnh

Tm v copy cc byte lnh t b nh

To ra cc tn hiu iu khin thc hin lnh

Gii m lnh

Chu k lnh v Chu k my

Chu k lnh: Tng thi gian tm lnh, gii m lnh v thc hin 1 lnh Ni chung, Chu k lnh ca cc lnh khc nhau l khc nhau Chu k lnh bao gi cng bng mt s nguyn ln chu k my Chu k my bng nghch o ca tn s hot ng (tc ng h) ca b vi x l

3.1 Kin trc v Hot ng ca 8088

n v giao tip Bus - BIU

Pht cc tn hiu a ch n b nh v cc cng I/O thng qua A-Bus c m lnh t b nh thng qua D-Bus c d liu t b nh thng qua D-Bus Ghi d liu vo b nh thng qua D-Bus c d liu t cc cng I thng qua D-Bus Ghi d liu ra cc cng O thng qua D-Bus

n v thc hin - EU
Bao gm CU v ALU CU : Gii m lnh to ra cc tn hiu iu khin nhm thc hin lnh c gii m ALU: thc hin cc thao tc khc nhau i vi cc ton hng ca lnh

T chc ca microprocessor
CPU Control registers

ALU BIU Control

Control Address Data

General purpose registers

Status Registers

X l lnh ca cc vi x l trc 8086/8088

Mt th tc n gin gm 3 bc:
Ly lnh t b nh Gii m lnh Thc hin lnh
Ly cc ton hng t b nh (nu c) Lu tr kt qu

Fetch 1

Decode 1

Execute 1

Fetch 2

Decode 2

Execute 2

...

Microprocessor

Busy

Idle

Busy

Busy

Idle

Busy

...

Bus

C ch Pipelining
P ip e lin in g

F e tc h 1

F e tc h 2 D ecode 1

F e tc h 3

F e tc h 4

S to r e 1

F e tc h 5 Id le

F e tc h 6

Load 2

F e tc h 7 Id le

...

Bus

D ecode D ecode D ecode 2 3 4

D ecode D ecode 5 6

Decode 7

...

In s tr u c tio n U n it

Exec. 1

Exec. 2

Exec. 3

Exec. 4

Id Id le le

Exec. 5

Exec. 6

Id le

Exec. 7

E x e c u tio n U n it

M e m o ry re q u e s t

M e m o ry re q u e s t

3.2 Cu trc thanh ghi ca 8088

8088 c 14 thanh ghi 16-bit

Cu trc thanh ghi ca h x86

General Purpose Special Registers
Accumulator
EAX AH AX AL

Instr Pointer
EIP BL

Index Registers
IP

Stack Pointer
FLAG ESP

SP

Base
EBX

BH BX

Flags
EFLAG

Base Pointer
EBP

BP

Count
ECX

CH CX

CL

Segment Registers
CS

Dest Index
EDI

DI

Data
EDX

DH DX

DL DS ES SS FS GS

Code Segment Data Segment Extra Segment Stack Segment

Source Index
ESI

SI

Cu trc thanh ghi 8086/8088

7 0 7 0

Accumulator Base Counter Data

15

AH BH CH DH CS DS SS ES
15

AL BL CL DL
0

AX BX CX DX

Code Segment Data Segment Stack Segment Extra Segment Instruction Pointer Stack Pointer Base Pointer Source Index Destination Index

IP SP BP SI DI

} }

Cc thanh ghi a nng

7 0 7 0

Accumulator Base Counter Data

AH BH CH DH

AL BL CL DL

AX BX CX DX

- C th truy cp nh cc thanh ghi 8-bit

- Lu tr tm thi d liu truy cp nhanh hn v trnh khi phi truy cp b nh - C cng dng c bit i vi mt s cu lnh

Cc thanh ghi segment

15 0

Code Segment Data Segment Stack Segment Extra Segment

CS DS SS ES

- Lu tr a ch segment ca mt nh cn truy cp

- Kt hp vi cc thanh ghi offset nht nh

Cc thanh ghi offset

Instruction Pointer Stack Pointer Base Pointer Source Index Destination Index

IP SP BP SI DI

- Lu tr a ch offset ca mt nh cn truy cp

- Kt hp vi cc thanh ghi segment nht nh

Thanh ghi c
15 0

x OF DF IF TF SF ZF x AF x PF x CF

- Khng phi tt c cc bit u c s dng - Mi bit c s dng c gi l mt c - Cc c u c tn v c th c Lp/Xo ring l - Bao gm cc c trng thi v cc c iu khin

Flags register
AC (Alignment check) (VM) Virtual mode (RF) Resume (NT) Nested task (IOPL) Input/output privilege level (O) Overflow (D) Direction (I) Interrupt (T) Trace (S) Sign (Z) Zero (A) Auxiliary Carry (P) Parity (C) Carry

8086, 8088, 80186

80386, 80486DX

80286

80486SX

3.3 Phng php qun l b nh

- B nh c xem l mt tp hp cc nh - Mi nh c nhn dng bng mt a ch vt l duy nht 20-bit - Trong hot ng truy cp mt nh, a ch vt l ca n c to ra t hai gi tr 16-bit: a ch segment v a ch Offset - a ch logic = a ch segment:a ch offset

Mi lin h gia CVL v CLG

A=Bus

19 a ch vt l

15

15

Thanh ghi offset.

Thanh ghi Segment

0000

3.4 M t tp lnh Assembly ca 8086/8088

- Khun dng: Mnemonics Cc ton hng - Nhm lnh chuyn s liu - Nhm lnh s hc - Nhm lnh logic - Nhm lnh R nhnh - Nhm lnh thao tc string - Nhm lnh hn hp

Nhm lnh chuyn s liu Data Transfer Instructions

-Chuyn s liu (sao chp s liu) t v tr ny sang v tr khc - Ngun s liu khng thay i - ich s c gi tr nh gi tr ca Ngun - Cc lnh chuyn s liu khng nh hng n cc c trng thi trn thanh ghi c - Mt s lnh tiu biu: MOV, XCHG

- Tc dng: (ch) - ch: c th l:

Data Transfer Instructions MOV Khun dng: MOV ch,Ngun

(Ngun)

1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau)

Ngun: c th l:

1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau) 3. Mt gi tr c th

Mt s lu i vi MOV
- ch v Ngun phi c cng kch c - ch v Ngun khng th ng thi thuc b nh - Nu ch l mt thanh ghi segment ca VXL th Ngun khng th l mt gi tr c th (ni cch khc, khng th np gi tr trc tip cho mt thanh ghi segment bng lnh MOV)

Data Transfer Instructions - XCHG

Khun dng: XCHG T/h1,T/h2

- Tc dng: (T/h1) - T/h1: c th l: (T/h2)

1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau)

T/h2: c th l:

1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau)

Mt s lu i vi XCHG
- T/h1 v T/h2 phi c cng kch c - T/h1 v T/h2 khng th ng thi thuc b nh - T/h1 v T/h2 khng th l cc thanh ghi segment

Cc mode a ch
- Khi thc hin lnh, VXL s thc hin nhng thao tc nht nh trn s liu, cc s liu ny c gi chung l cc ton hng. - Cc ton hng trong mt cu lnh c th l mt phn ca cu lnh ( dng m my), c th nm mt thanh ghi ca VXL hoc B nh -Cch xc nh ton hng trong cc cu lnh c gi l cc mode (nh) a ch

Cc mode a ch
- Mode a ch thanh ghi: MOV AX,BX - Mode a ch tc th: MOV AL,55h - Cc mode a ch b nh: Cc cch thc xc nh a ch vt l ca ton hng nm trong b nh: Mode a ch trc tip Cc mode a ch gin tip

Mode a ch trc tip (Direct Addressing Mode)

Mode a ch gin tip thanh ghi (Register Indirect Addressing Mode)

Mode a ch c s-ch s (Based-Indexed Addressing Mode)

Nh cc mode a ch b nh nh th no? Tt c bt u trong bng sau y:

DISP BX BP SI DI

Ly ra 0 hoc 1 phn t t mi ct (Khng ly 2 phn t t mt ct) Phi ly t nht 1 phn t t bng

Cc v d
Instruction Comment Addressing Mode Register 89 D8 Memory Contents MOV AX, BX Move to AX the 16-bit value in BX
OP MODE

MOV AX, DI

Move to AX the 16-bit value in DI

Register

89 F8

OP

MODE

MOV AH, AL

Move to AL the 8-bit value in AX

Register

88 C4

OP

MODE

MOV AH, 12h

Move to AH the 8-bit value 12H

Immediate

B4 12

OP

DATA8

MOV AX, 1234h

Move to AX the value 1234h Move to AX the constant defined as CONST Move to AX the address or offset of the variable X Move to AX the value at memory location 1234h Move to AX the value in memory location DS:X

Immediate

B8 34

OP

DATA16

MOV AX, CONST

Immediate

B8 lsb msb

OP

DATA16

MOV AX, X

Immediate

B8 lsb msb

OP

DATA16

MOV AX, [1234h]

Direct

A1 34 12

OP

DISP16

MOV AX, [X]

Direct

A1 lsb msb

OP

DISP16

Cc v d
Instruction Comment Move to the memory location pointed to by DS:X the value in AX Move to AX the 16-bit value pointed to by DS:DI Move to address DS:DI the 16-bit value in AX Move to AX the 16-bit value pointed to by DS:BX Move to the memory address DS:BX the 16-bit value stored in AX Move to memory address SS:BP the 16-bit value in AX Move to AX the value in memory at DS:BX + TAB Move value in AX to memory address DS:BX + TAB Move to AX the value in memory at DS:BX + DI Addressing Mode Direct Memory Contents MOV [X], AX A3 lsb msb
OP DATA16

MOV AX, [DI]

Indexed

8B 05

OP

MODE

MOV [DI], AX

Indexed Register Indirect Register Indirect Register Indirect Register Relative Register Relative Base Plus Index

89 05

OP

MODE

MOV AX, [BX]

8B 07

OP

MODE

MOV [BX], AX

89 07

OP

MODE

MOV [BP], AX

89 46

OP

MODE

MOV AX, TAB[BX]

8B 87 lsb msb

OP

MODE

DISP16

MOV TAB[BX], AX

89 87 lsb msb

OP

MODE

DISP16

MOV AX, [BX + DI]

8B 01

OP

MODE

Cc v d
Instruction Comment Addressing Mode Memory Contents

MOV [BX + DI], AX

Move to the memory location pointed to by DS:X the value in AX

Base Plus Index

89 01

OP

MODE

MOV AX, [BX + DI + 1234h]

Move word in memory location DS:BX + DI + 1234h to AX register

Base Rel Plus Index

8B 81 34 12

OP

MODE

DISP16

MOV word [BX + DI + 1234h], 5678h

Move immediate value 5678h to memory location BX + DI + 1234h

Base Rel Plus Index

C7 81 34 12 78 56

Mt lnh c th di t1 n 6 byte Byte 1 gm:

M my

Opcode (6 bit) xc nh php ton cn thc hin Bit D xc nh ton hng REG ca Byte 2 l ngun hay ch: 1: ch 0: Ngun Bit W xc nh kch c ca ton hng l 8 bit hay 16 bit 0: 8 bit 1: 16 bit Byte 2 gm:Mode field (MOD), Register field (REG) Register/memory field (R/M field)

Anatomy of an instruction
Opcode Mode Displacement Data/Immediate

D W

OPCODE

Opcode contains the type of instruction we execute plus two special bits, D and W The mode byte is used only in instructions that use register addressing modes and encodes the source and destination for instructions with two operands D stands for direction and defines the data flow of the instruction
D=0, data flows from REG to R/M D=1, data flows from R/M to REG

MOD

REG

R/M

W stands for the size of data

W=0, byte-sized data W=1, word (in real mode) or double-word sized (in protected mode)

Anatomy of an instruction
Opcode Mode Displacement Data/Immediate

D W

OPCODE

MOD field specifies the addressing mode 00 no displacement 01 8-bit displacement, sign extended 10 16-bit displacement 11 R/M is a register, register addressing mode If MOD is 00,01, or 10, the R/M field selects one of the memory addressing modes

MOD

REG

R/M

Registers in the REG and R/M fields

Code 000 001 010 011 100 101 110 111 W=0 (Byte) AL CL DL BL AH CH DH BH W=1 (Word) AX CX DX BX SP BP SI DI W=1 (DWord) EAX ECX EDX EBX ESP EBP ESI EDI

Example
Consider the instruction 8BECh 1000 1011 1110 1100 binary Opcode 100010 -> MOV D=1 data goes from R/M to REG W=1 data is word-sized MOD=11, register addressing REG=101 destination, R/M=100 source MOV BP, SP
Code 000 001 010 011 100 101 110 111 W=0 AL CL DL BL AH CH DH BH W=1 AX CX DX BX SP BP SI DI W=1 EAX ECX EDX EBX ESP EBP ESI EDI

Displacement addressing
If MOD is 00, 01, or 10 R/M has an entirely different meaning
MOD 00 01 10 11 No displacement 8-bit sign-extended displacement 16-bit displacement R/M is a register (register addressing mode) FUNCTION

R/M Code 000 001 010 011 100 101 110 111

Function DS:BX+SI DS:BX+DI SS:BP+SI SS:BP+DI DS:SI DS:DI SS:BP DS:BX

Examples: If MOD=00 and R/M=101 mode is [DI] If MOD=01 and R/M=101 mode is [DI+33h] If MODE=10 and R/M=101 modes is [DI+2233h]

Example
Instruction 8A15h 1000 1010 0001 0101 Opcode 100010 -> MOV D=1, data flows from R/M to REG W=0, 8-bit argument MOD=00 (no displacement) REG=010 (DL) REG=101 ([DI] addressing mode) MOV DL, [DI]

Code 000 001 010 011 100 101 110 111

W=0 AL CL DL BL AH CH DH BH

W=1 AX CX DX BX SP BP SI DI

W=1 EAX ECX EDX EBX ESP EBP ESI EDI

R/M Code 000 001 010 011 100 101 110 111

Function DS:BX+SI DS:BX+DI SS:BP+SI SS:BP+DI DS:SI DS:DI SS:BP DS:BX

Direct Addressing Mode

MOD is always 00 R/M is always 110 REG encodes the register to/from we take data as usual Third byte contains the lower-order bytes of the displacement, fourth byte contains the high order byte of the displacement

Direct Addressing
Example: 8816 00 10 1000 1000 0001 0110 0000 0000 0001 0000 Opcode 100010 -> MOV W=0 (byte-sized data) D=0 data flows from REG MOD 00, REG=010 (DL), R/M=110 Low-order byte of displacement 00 High-order byte of displacement 10 MOV [1000h], DL
Code 000 001 010 011 100 101 110 111 AL CL DL BL AH CH DH BH

W=0

W=1 AX CX DX BX SP BP SI DI

W=1 EAX ECX EDX EBX ESP EBP ESI EDI

Segment MOV instructions

Different opcode 100011 Segments are selected by setting the REG Example MOV BX, CS field
REG Code 000 001 010 011 100 101 Segment reg. ES CS SS DS FS GS

Opcode 10001100 MOD=11 (register addressing) REG=001 (CS) R/M=011 (BX) 8CCB

M my
REG xc nh thanh ghi cho ton hng th nht

M my
MOD v R/M cng nhau xc nh ton hng th hai

M my
MOD v R/M cng nhau xc nh ton hng th hai

V d
M ho lnh MOV

BL,AL

Opcode i vi MOV l 100010 Ta m ho AL sao cho AL l ton hng ngun: D = 0 (AL l ton hng ngun) W bit = 0 (8-bit) MOD = 11 (register mode) REG = 000 (m ca AL) R/M = 011 (m ca BL) Kt qu:: 10001000 11000011 = 88 C3

Nhm lnh S hc
Bn cnh tc dng, cn ch n nh hng ca lnh i vi cc c trng thi Cc lnh s hc th/thng: ADD, SUB, Cc lnh s hc khc: CMP. NEG, INC, DEC, nh hng n cc c trng thi
CF OF AF Ph thuc vo qu trnh thc hin php ton

ZF = 1 nu Kt qu bng 0 SF = 1 nu MSB ca Kt qu = 1 PF = 1 nu byte thp ca kt qu c Parity chn

Arithmetic Instructions - ADD Khun dng: ADD ch,Ngun

- Tc dng: (ch) - ch: c th l:
(ch)+(Ngun) 1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau)

Ngun: c th l:

1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau) 3. Mt gi tr c th

nh hng ca ADD
ZF = 1 nu Kt qu bng 0 SF = 1 nu MSB ca Kt qu = 1 PF = 1 nu byte thp ca kt qu c Parity chn

CF c lp nu trn khng du (c nh t MSB) OF c lp nu trn c du: - C nh t MSB, Khng c nh vo MSB - C nh vo MSB, Khng c nh t MSB AF c lp nu c nh t nibble thp vo nibble cao (t bit 3 vo bit 4)

Cc c trn thanh ghi c

Cc bit nht nh trn thanh ghi c iu khin hot ng hoc phn nh trng thi ca vi x l
Cc c iu khin (TF, IF, DF)
Quyt nh cch p ng ca vi x l trong cc tnh hung nht nh

Cc c trng thi (CF, PF, AF, ZF, SF, OF)

B nh hng bi cc php ton nht nh Phc v cho cc lnh c iu kin

Cc c iu khin
DF - Direction flag (C hng)
DF = 1: hung xung DF = 0: hng ln

IF Interrupt flag (C ngt)

IF = 1: cho php ngt ngoi IF = 0: cm ngt ngoi (i vi ngt che c)

TF - Trace flag
TF = 1: vi x l thc hin tng lnh mt

Cc c trng thi
Carry
carry or borrow at MSB in add or subtract last bit shifted out

Zero
result is 0

Sign
result is negative

Parity
low byte of result has even parity

Overflow
signed overflow occurred during add or subtract

Auxiliary
carry or borrow at bit 3

(Signed) Overflow
Can only occur when adding numbers of the same sign (subtracting with different signs) Detected when carry into MSB is not equal to carry out of MSB
Easily detected because this implies the result has a different sign than the sign of the operands

Programs can ignore the Flags!

Signed Overflow Example

10010110 + 10100011 00111001 Carry in = 0, Carry out = 1 Neg+Neg=Pos Signed overflow occurred OF = 1 (set) 00110110 + 01100011 10011001 Carry in = 1, Carry out = 0 Pos+Pos=Neg Signed overflow occurred OF = 1 (set)

Examples of No Signed Overflow

10010110 + 01100011 11111001 Carry in = 0, Carry out = 0 Neg+Pos=Neg No Signed overflow occurred OF = 0 (clear) 10010110 + 11110011 10001001 Carry in = 1, Carry out = 1 Neg+Neg=Neg No Signed overflow occurred OF = 0 (clear)

Unsigned Overflow
The carry flag is used to indicate if an unsigned operation overflowed The processor only adds or subtracts - it does not care if the data is signed or unsigned!
10010110 + 11110011 10001001 Carry out = 1 Unsigned overflow occurred CF = 1 (set)

DEBUG's Register Display

-R 000 SP=0010 BP=0000 SI=0000 DI=0000 00F IP=004F NV UP DI PL NZ NA PO NC

The state of the Flags are shown in line 2

OV/NV: EI/DI: NG/PL: AC/NA: CY/NC: (no)oVerflow DN/UP: direction En(Dis)abled Interrupts sign ZR/NZ: (not)Zero (no)Auxiliary PE/PO: Even/Odd (no)Carry (set/clear)

Arithmetic Instructions - SUB Khun dng: SUB ch,Ngun

- Tc dng: (ch) - ch: c th l:
(ch)-(Ngun) 1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau)

Ngun: c th l:

1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau) 3. Mt gi tr c th

nh hng ca SUB
ZF = 1 nu Kt qu bng 0 SF = 1 nu MSB ca Kt qu = 1 PF = 1 nu byte thp ca kt qu c Parity chn

CF c lp nu trn khng du (c mn vo MSB) OF c lp nu trn c du: - C mn t MSB, Khng c mn t MSB - C mn t MSB, Khng c mn vo MSB AF c lp nu c mn t nibble cao vo nibble thp (t bit 4 vo bit 3)

Arithmetic Instructions - CMP Khun dng: CMP ch,Ngun

- Tc dng: (ch)-(Ngun) - ch: c th l:
1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau)

Ngun: c th l:

1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau) 3. Mt gi tr c th

Arithmetic Instructions INC, DEC, NEG

INC T/h
Trong : T/h c th l cc thanh ghi hoc v tr nh

Tc dng: (T/h) DEC T/h

(T/h)+1

Trong : T/h c th l cc thanh ghi hoc v tr nh

Tc dng: (T/h)

(T/h)-1

Lu : Cc lnh INC v DEC khng nh hng n c CF

Lnh NEG T/h: o du ca T/h (Ly b 2)

Lnh NEG s lp c OF nu gi tr ca T/h l gi tr m nht trong di gi tr ca cc s c du tng ng

Nhm lnh Logic

Cn ch n nh hng ca lnh i vi cc c trng thi Cc lnh logic th/thng: NOT, AND, OR, XOR NOT A: ~A AND A,B: A &= B OR A,B : A |= B XOR A,B: A ^= B NOT khng nh hung n cc c trng thi. Cc lnh khc:
CF = 0 OF = 0 ZF = 1 nu Kt qu bng 0 SF = 1 nu MSB ca Kt qu = 1 PF = 1 nu byte thp ca kt qu c Parity chn AF khng xc nh

Mt s v d
AL 1100 1010 NOT AL AL 0011 0101 AL 0011 0101 BL 0110 1101 AND AL, BL AL 0010 0101 AL 0011 0101 BL 0000 1111 AND AL, BL AL 0000 0101 AL BL 0011 0101 0110 1101 OR AL, BL AL 0111 1101 AL BL 0011 0101 0000 1111 OR AL, BL AL 0011 1111 AL 0011 0101 BL 0110 1101 XOR AL, BL AL 0101 1000

Mt s ng dng
Bi ton Xo bit: Xo mt bit no ca mt ton hng m khng lm nh hng n cc bit cn li ca ton hng Bi ton Kim tra bit: Xc nh mt bit no ca mt ton hng l bng 0 hay 1 (thng qua gi tr ca mt c trng thi) Bi ton Lp bit: Lp mt bit no ca mt ton hng m khng lm nh hng n cc bit cn li ca ton hng

Nhm lnh logic

Cc lnh logic khc: Lnh TEST, Cc lnh dch (Shift) v Cc lnh quay (Rotate) Lnh TEST ch khc lnh AND l khng gi li kt qu ca php ton Cc lnh dch v Cc lnh quay u c hai khun dng: Khun dng 1: Mnemonic Ton hng,1 Khun dng 2: Mnmonic Ton hng,CL Tc dng ca mt cu lnh theo khun dang 2 ging nh tc dng lin tip ca N cu lnh tng ng theo khun dng 1, vi N l gi tr ca thanh ghi CL

Cc lnh Dch tri: SHL, SAL

CF Register 0

Shift right SHR

Register

CF

Shift right SAR

Register CF

Rotate through Carry L/R (Quay tri/phi thng qua carry)

RCL

RCR

Rotate left/right (Quay tri/phi khng qua carry)

ROL

ROR

Nhm lnh r nhnh

Lm thay i trt t thc hin lnh bnh thng ca vi x l
Lnh nhy khng iu kin: JMP Cc lnh nhy c iu kin: Jxxx Lnh lp: LOOP v cc bin th ca n Cc lnh c lin quan n Chng trnh con: - CALL (gi chng trnh con) - RET (tr v chng trnh gi) Cc lnh c lin quan n Chng trnh con phc v ngt - INT (gi chng trnh con phc v ngt - Gi ngt) - IRET (quay v chng trnh gi ngt)

Lnh nhy khng iu kin

JMP nhn
Nhy gn: E9 xx xx (3 byte) Nhy ngn: EB xx (2 byte) Nhy xa: EA xx xx xx xx (5 byte) Nhn: tn do ngI lp trnh t t ra theo qui tc t tn ca Assembler v c th t vo trc mt cu lnh bt k trong chng trnh cng vi du : nhn: Cu lnh cn thc hin Nhn s c dch thnh a ch Khong cch nhy: Khong cch i s (c du) t lnh nhy n lnh cn thc hin

C ch thc hin lnh nhy

Cc lnh nhy ngn v gn ch lm thay i gi tr ca thanh ghi IP
Lnh nhy ngn cng khong cch nhy 8-bit c du vo gi tr hin thi ca IP Lnh nhy gn cng khong cch nhy 16-bit c du vo gi tr hin thi ca IP

Lnh nhy xa lm thay i c CS v IP

Gn cho CS v IP cc gi tr mi

M my ca lnh nhy
1106:0100 EB2A JMP 012C 012C-0102=002A 1106:0102 EBFC JMP 0100 0100-0104=FFFC 1106:0104 E97F00 JMP 0186 0186-0106=0080 (too far for short!) 0186-0107=007F 1106:0107 E9F5FE JMP FFFF FFFF-010A=FEF5

Cc lnh nhy c iu kin

Jxxx nhn
C gn 40 menmonic khc nhau

Cc lnh nhy iu kin n: ph thuc vo gi tr ca 1 c. JNZ/JNE - Nhy nu c ZF = 0, ngha l kt qu ca php ton trc khc khng JC - Nhy nu CF = 1, ngha l cu lnh trc lp c carry JZ/JE JNC

Cc lnh nhy c iu kin

Tt c cc lnh nhy c iu kin phi l nhy ngn
khong cch nhy: -128 to +127 bytes

T hp vi lnh nhy khng iu kin c th vt qua gii hn ny. Cc lnh nhy iu kin kp: ph thuc vo gi tr ca nhiu c JB/JNAE JNL/JGE

ng dng ca cc lnh nhy c iu kin

Kt hp vi JMP xy dng cc cu trc lp trnh c bn: - Cu trc iu kin - Cu trc lp Cc lnh nhy thng theo sau cc lnh lm thay i gi tr ca cc c trng thi:
CMP TEST

Cu trc iu kin
mov ax,n cmp ax,7 jz nhan1 lnh 1 jmp nhan2 nhan1:lnh 2 nhan2:lnh 3

Cu trc lp
mov ax,n nhan1: cmp ax,0 jz nhan2 lnhi sub ax,2 jmp nhan1 nhan2: lnhk

Cu trc iu kin - AND

char n; int w,x; if (n>='A' && w==x) whatever();
;if(n>='A'&&w==x) mov ah,n cmp ah,'A' jl nogo mov ax,w cmp ax,x jne no_go ;then-part call whatever nogo:

Cu trc iu kin - OR
char n,k; unsigned int w; if (n<>k || w<=10) whatever();
;if(n<>k||w<=10) mov ah,n cmp ah,k jne then_ cmp w,10 ja end_if then_: call whatever end_if:

Lnh LOOP
LOOP nhan
Gim CX i 1 Nu (CX) <> 0 th JMP nhan. Nu khng th tip tc thc hin lnh theo trt t bnh thng mov cx,9 nhan: lnh 1 lnh 2 lnh 3 loop nhan

LOOPZ/E v LOOPNZ/E
Cc bin th ca LOOP Gi tr ca c ZF c th lm kt thc sm vng lp Loop while ZF/equal && CX!=0 Loop while (NZ/ not equal) && CX!=0 Lu : LOOP gim CX nhng khng nh hung n cc c LOOPZ == LOOPE LOOPNZ==LOOPNE Cc lnh trong vng lp c th tc ng n c ZF (CMP ?)

Chng trnh con

Chng trnh con trong ngn ng Assembly c gi l Th tc (Procedure) Mt th tc c th c thc hin nhiu ln C lin quan n stack: - lu gi a ch quay v - lu gi gi tr ca cc thanh ghi ca vi x l

Stack ?
Cu trc d liu LIFO RWM
- PUSH : ghi d liu vo stack, - POP: c d liu t stack

(SS:SP) tr n nh ca stack (SS:BP) truy cp stack ngu nhin (khng theo LIFO)

Stack Initialization
The .stack directive hides an array allocation statement that looks like this
The_Stack DB Stack_Size dup (?)

On program load
SS is set to a segment address containing this array (usually The_Stack starts at offset 0) SP is set to the offset of The_Stack+Stack_Size which is one byte past the end of the stack array
This is the condition for an empty stack

Initial Stack Configuration

.stack 12 ;Reserve space for the stack Loader determines actual segment address for the start of the stack
This is an empty stack
Stack Size: 000C

SS:0340 SS:0340

SP:000C SP:000C

How Does The Stack Work?

The stack grows backwards through memory towards the start of the stack segment
Stack Size: 000C

SS:0340 SS:0340

SP:0008 SP:0008

Push decrements stack pointer Pop increments stack pointer

PUSH
PUSH ngun
Push ngun vo stack

PUSHF
Push thanh ghi c vo stack

Lnh PUSH trc ht s gim SP i 2 ri lu gi tr ca ngun vo v tr nh c tr bi (SS:SP)

V d PUSH
Stack Size: 000C
3C 09 A4 40 2C FF A2 43 07 06 4C 2A 09 46

SS:0340 SS:0340

SP:0008 SP:0008 AX: AX:0123 0123

PUSH AX

3C 09 A4 40 2C FF A2 23 01 06 4C 2A 09 46

SS:0340 SS:0340

SP:0006 SP:0006

POP
POP ch
Pop d liu t nh stack vo ich

POPF
Pop d liu t nh stack vo thanh ghi c

Lnh POP trc ht copy d liu c tr bi (SS:SP) n ch ri tng SP ln 2

V d POP
3C 09 A4 40 2C FF A2 23 01 06 4C 2A 09 46

SS:0340 SS:0340

SP:0006 SP:0006

POP ES
3C 09 A4 40 2C FF A2 23 01 06 4C 2A 09 46

SS:0340 SS:0340

ES: ES:0123 0123

SP:0008 SP:0008

Trn stack!
Stack Size: 000C

SS:0340 SS:0340

SP:FFFE SP:FFFE

Stack Overflow Stack Underflow

Stack Size: 000C

SS:0340 SS:0340

SP:000D SP:000D

Th tc
Tn_Th_tc PROC kiu ;thn ca th tc RET ;quay v chung trnh gi Tn_Th_tc ENDP

kiu l NEAR hoc FAR

ngm nh l NEAR

Mt th tc c th c nhiu lnh RET

Lnh CALL v RET

Gi mt th tc (NEAR) CALL Tn_Th_tc
push IP vo stack copy a ch ca Tn_Th_tc vo IP

Tr v t mt th tc (NEAR) RET
pop gi tr nh stack vo IP

Th tc Far
Gi th tc (FAR) CALL Tn_th_tc
ln lt push CS v IP vo stack copy a ch ca Tn_th_tc vo CS v IP

Tr v t th tc (FAR) RET
pop gi tr t nh stack ln lt vo IP v CS

Gi ngt
Gi ngt l mt li gi th tc c bit
FAR Thanh ghi c phi c bo ton

INT S ngt
Thanh ghi c c push, TF v IF b xo CS v rI IP c push a ch ca mt chng trnh con phc v ngt (Vector ngt) tng ng vi S ngt c copy vo CS v IP

Tr v t ngt
IRET Tc dng ca lnh:
Gi tr nh ca stack c pop vo IP Gi tr nh ca stack c pop vo CS Gi tr nh ca stack c pop vo thanh ghi c

Chng trnh b ngt tip tc thc hin dng nh khng c chuyn g xy ra

Xut k t ra mn hnh PC
Ngt 21h
Ngt ny h tr rt nhiu dch v trn PC Nhn dng dch v bng s dch v (s hm). S dch v cn c np vo thanh ghi AH Tu theo tng dch v, c th cn thm mt s i s khc c np vo cc thanh ghi xc nh

AH = 2, DL = M ASCII ca k t cn xut
K t c hin th ti v tr hin thI ca con tr

Xut xu k t ra mn hnh PC
Dch v 09h ca ngt 21h
DX = a ch Offset ca xu (trong on d liu) DS = a ch segment ca xu Xu k t phi kt thc bng k t '$'

np a ch offset ca xu vo DX, c th:

LEA MOV DX, Tnxu DX, OFFSET Tn xu

Nhp 1 k t t bn phm PC
Dch v 01h ca ngt 21h Khi NSD g mt k t t bn phm:
K t s hin trn mn hnh AL s cha m ASCII ca k t
AL=0 nu k t c nhp l k t iu khin

Nhm lnh thao tc string

Chng ta hiu: string l mt mng byte hoc t nm trong b nh Cc thao tc string:
Sao chp Tm kim Lu tr So snh

Cc c im
Ngun: (DS:SI), ch: (ES:DI)
DS, ES cha a ch Segment ca string SI, DI cha a ch Offset ca string

C hng DF (0 = Up, 1 = Down)

DF = 0 - Tng a ch (tri qua phi) DF = 1 - Gim a ch (phI qua tri)

Chuyn (Sao chp)

MOVSB, MOVSW
Chuyn 1 byte hoc 1 word t v tr nh ny sang v tr nh khc Tc dng ca lnh:
Sao chp byte/word t (DS:SI) n (ES:DI) Tng/Gim SI v DI 1 hoc 2 gi tr

Nu CX cha mt gi tr khc khng:

REP MOVSB hoc REP MOVSW s t ng sao chp (CX) ln v CX s v khng

V d:Sao chp mng

; Sao chp 10 byte t mng a sang mng b, gi s (DS) = (ES)

mov mov mov cld rep

cx, 10 di, offset b si, offset a ;xo c DF movsb

V d: Tnh tin cc nh
mov mov mov std rep
a

cx, 7 di, offset a+9 si, offset a+6 ;lp c DF movsb SI

DI

V d
pattern mov mov mov cld rep
SI

db "!@#*" db 96 dup (?) cx,96 si, offset pattern di, offset pattern+4 movsb
DI

! @ # * a

Lu tr string
STOSB, STOSW Copy AL hoc AX vo mt mng byte hoc word
ch (ES:DI)

Thng c s dng c tin t REP v s ln lp trong CX

Tng hoc Gim DI

ph thuc DF

V d:
arr dw 200 dup (?) mov ax,50A0h mov di,offset arr mov cx,200 cld AX 50 A0 rep stosw

DI

A0 50 A0 50 arr

Np String
LODSB, LODSW
Byte hoc word ti (DS:SI) c copy vo AL hoc AX SI tng hoc gim 1 hoc 2 gi tr ph thuc DF

Thng c dng vi STOSx trong mt vng lp x l tng phn t trong mt mng

V d:
mov di, offset b mov si, offset a mov cx,30 cld lp: lodsb and al,0DFh stosb loop lp

Qut String
SCASB, SCASW So snh AL hoc AX vI byte hoc word tI (ES:DI) v t ng tng hoc gim DI Lnh ny nh hng n cc c trng thi
Tu theo kt qu so snh Dng trong mt vng lp REPs
REPZ, REPE, REPNZ, REPNE

V d
arr db 'abcdefghijklmnopqrstuvwxyz' mov di, offset arr mov cx,26 cld mov al,target repne scasb jne nomatch

So snh String
CMPSB, CMPSW So snh byte hoc word ti (DS:SI) vi byte hoc word tI (ES:DI), tc ng n cc c v tng hoc gim SI v DI Thng dng so snh hai mng vi nhau

V d
mov si, offset str1 mov di, offset str2 cld mov cx, 12 repe cmpsb jl str1smaller jg str2smaller ;the strings are equal - so far ;if sizes different, shorter string is less

Nhm lnh hn hp
- Cc lnh Lp/Xo trc tip cc c: STC, CLC STD, CLD STI, CLI - Lnh NOP (No Operation): Khng lm g!!! - Lnh NOP thng c dng trong cc vng lp to tr (delay)bng phn mm - Cc lnh Nhp/Xut d liu i vi cc cng I/O IN OUT

Lnh IN
- Nu a ch ca cng Nh hn hoc bng FFh: IN Acc, a ch cng - Trong : Acc c th l AL hoc AX - Nhp d liu t cng vo Acc - Nu a ch ca cng Ln hn FFh: MOV DX, a ch cng IN Acc, DX - Trong : Acc c th l AL hoc AX - Nhp d liu t cng vo Acc

Lnh OUT
- Nu a ch ca cng Nh hn hoc bng FFh: OUT a ch cng, Acc - Trong : Acc c th l AL hoc AX - Xut d liu t Acc ra cng - Nu a ch ca cng Ln hn FFh: MOV DX, a ch cng OUT DX, Acc - Trong : Acc c th l AL hoc AX - Xut d liu t Acc ra cng

Tm tt chng
- Tnh tng thch v Cu trc thanh ghi ca cc vi x l h x86 - Tnh tng thch v Tp lnh ca cc vi x l h x86