Professional Documents
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Disclaimer
• A proper introduction alone would take weeks,
let alone a whole semester
• Need to omit lots of nitty-gritty yet important process
details
• Hopefully, we’ll still learn lots of cool device physics
59nm
Qdep
p-substrate depletion
charge
Loke, Wee & Pfiester
Agilent Technologies Slide 5
More MOS Fundamentals (Energy Band Diagram)
Formation of Inversion Layer
VT = gate voltage required to reverse doping of silicon surface, i.e., move φs by 2φb
flatband onset of inversion onset of strong inversion
(no field in silicon) (surface is undoped) (VT condition)
M O S M O S M O S
silicon inversion
surface layer
EC
EF φs φb φb φb
Ei
EF φs φs
EV VT φs
φs = φb φs = 0
φs = -φb
kBT NA Qdep
φb = ln VT = VFB + 2φb +
q ni
Cox
offset bulk oxide
Loke, Wee & Pfiester drop drop
Agilent Technologies Slide 6
Reintroducing (…drum roll…) the MOSFET
VGS = 0
VDS = 0 (no net current flow)
Large source barrier
(back-to-back diodes)
VGS ≈ VT
VDS = 0 (no net current flow)
Source barrier is lowered
Surface is inverted
electron
current VGS > VT
VDS > 0 (net source-to-drain current flow)
Carriers easily overcome source barrier
Surface is strongly inverted
Ideal Reality
IDS IDS
VGS
VGS
VDS VDS
2 n-well p-well 5
3 6
pFET nFET
Gate Oxidation & Salicidation
Poly Definition
Loke, Wee & Pfiester
Agilent Technologies Slide 10
Step-and-Scan Projection Lithography
Rayleigh’s Equation: Resolution ∝ λ / NA
Deep-UV Slit Source
• Previous generations used G-line (436nm) & I-line
(365nm) steppers (refractive 4X-projection optics) Excimer Laser
• Technology trends KrF (248nm) or ArF (193nm)
• More aggressive CD’s shorter λ
• Higher NA lenses $$$
• Larger reticle field sizes $$$
• Step-and-scan enabled resolution & CD control for
critical layers beyond 0.35µm node
• Slide reticle & wafer across narrow slit of light
• Aberration-free high-NA optics only required
along 1-D but now requires high-precision
constant-velocity stages
• Still much cheaper than optics optimized in 2-D
• Rectangular reticle size shorter edge limited
by slit width
• Relatively weak intensity of deep-UV source
required development of very sensitive
chemically-amplified resists for throughput Source: Nikon
Resist
Pattern Intensity
at Wafer
Source: Socha, ASML (2004) Source: Plummer, Stanford (2004)
• Industry played lots of tricks to reduce width of bird’s beak & make field oxide
coplanar with active areas
2
4
5
etched away in
subsequent
oxide cleans
Strip Si3N4 polish stop
oxide CMP
Core
n-well
Core Core
n-well p-well
free lunch!!!
Loke, Wee & Pfiester
Agilent Technologies Slide 17
Well Engineering
Shallow & steep surface channel implant
Retrograded well dopant profile • VT control
(implants before poly deposition) • Slow diffusers critical (Ga, Sb)
Substrate
Doping
STI STI
oxide p-well oxide
Implant order matters to prevent ion channeling, especially for the shallow implant
resist anti-reflection
layer (ARL)
Si substrate
1 4
poly gate poly gate
p-well halos
self-aligned high-tilt halo/pocket implant p-well
(p-type)
Resulting structure has:
2 • Smaller SCE
poly gate • Shallow junction where needed most
• Low junction capacitance
p-well Not to be confused with LDD’s in I/O FET’s
• Same process with spacers but Iightly
dielectric spacer formation doped drain (LDD) is used for minimizing
3
peak E fields that cause hot carriers &
poly gate
breakdown
• Extensions need to be heavily doped to
p-well minimize series resistance
Different halo & extension/LDD implants for
Loke, Wee & Pfiester each FET variant
Agilent Technologies Slide 21
Rapid Thermal Processing (RTP)
Wasabi vs. Curry
RTP Furnace
Temperature
Temperature
substantial
ramp times
Time Time
poly
1 diffusion 3
well
2 4
poly
field oxide diffusion
1
SiO2 deposition prior to salicide module
2
Salicide block etch
salicide
3
Salicide module
• Increasing discrepancy between electrical & physical gate oxide thicknesses since
charges are not intimately in contact with oxide interface Cox not as small
• Cox must account for gate & Si surface charge centroids as well as εSi
• Modeled in BSIM4 more accurate I-V & C-V calculations
• Motivation for high-K gate dielectrics & metal/silicided gate technology
Loke, Wee & Pfiester
Agilent Technologies Slide 26
VT Variations Across FET L & W in 90nm
• Wondered why so many transistor L & W bins in SPICE models?
• e.g., SPICE model linear VT’s for 90nm nom-VT core nFET @ 85°C
• VT↑ as L ↓
• VT↓ as W ↓ 15/0.1µm
short
• WHY?
wide
0.36
0.15/0.1µm 0.34
0.32 0.34-0.36
short 0.32-0.34
0.30
narrow 0.30-0.32
0.28
0.28-0.30
0.26
0.26-0.28
0.24 VT (V)
0.24-0.26
0.22
• Think how much gate 0.20
0.22-0.24
0.16-0.18
0.16
0.14-0.16
0.63
L (µ m) 0.12-0.14
2.51
15.00
5.97
3.98
2.38
0.95
6.31
0.38
0.15
10.00
W (µ m)
conventional SCE
p-well
Drawn Channel Length, L
VT
Thicker oxide under gate edge
• Tougher to deplete
• More gate charge needed for
inversion
Drawn Channel Width, W
nFET pFET
0.24/1.0µm
1.0/1.0µm
1.0/1.0µm
0.24/1.0µm
0.24/0.18µm
1.0/0.18µm
1.0/0.18µm
0.24/0.18µm
10.0
1.0
• “No free lunch” principle prevails again: high ION high IOFF
• VT’s not scaling as aggressively as VDD
• Technology providers offer variety of VT’s on same die to concurrently
meet high-speed vs. low-leakage needs
Loke, Wee & Pfiester
Agilent Technologies Slide 33
Leakage Current Contributions
VDD
poly gate IG
n+ ISUB n+
IGIDL
p-well
IJ
source CSi
silicon
VG drain
p-substrate depletion
VB capacitance
Loke, Wee & Pfiester
Agilent Technologies Slide 35
Basic Intuition on Body Effect
• Body or backgate effect
• Applying reverse bias between substrate (body) & source increases |VT|
• Basic equation: VT = VT0 + γ ( 2φb+VSB – 2φb )
• Tug-o-war between VG & VB to control surface potential through Cox & Csi
• Inversion layer forms when φs is lowered sufficiently with respect to source
(that’s where carriers come from)
VG
Silicon surface Cox
Potential (φs) gate gate oxide
capacitance
CSi
silicon
p-substrate depletion
VB capacitance
p-well p-well
source drain
CB reduction of electron barrier
VDD height in conduction band (CB)
at edge of source
halo n+ drain
poly gate
drain
p-well
0.1
high-V
T
-0.4
-0.5 1
0.1 1 10
L, Drawn Channel Length (µm)
-0.82mV/C
0.2 nFET
φb ↓ for constant NA
Linear V (V)
0.1
|VT| ↓
T
0.0
-0.1
pFET -1.08mV/C
-0.2 -1.04mV/C
kBT NA low-V
φb = ln -0.3
nom-V
T
-0.88mV/C
q ni -0.4
high-V
T
T
-0.5
-0.6
-40 -20 0 20 40 60 80 100 120 140 160
• VT can vary a lot with temperature Temperature (C)
source drain
CB
VD
Source: Cao et al., UC Berkeley (1999)
Idsat ∝ (VDD–VT) 2
FS SS SF FF
acceptable
pFET pFET
VT TT Idsat TT
FF SF SS FS
F = fast
nFET T = typical nFET
VT S = slow Idsat
3.5
FF
3.0 σ
3.0 SF 2.5 σ
TT Measurements
2.5 SPICE Targets
FS
2.0 SS
uncorrelated variations due
1.5
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
to uncommon processes
10/0.13µm nFET Idsat (mA) e.g., channel & well ion
implants
Prof. Simon Wong Prof. Krishna Saraswat Prof. James Plummer Prof. Bruce Wooley Prof. Tom Lee
Stanford University Stanford University Stanford University Stanford University Stanford University
Dr. Stephen Kuehne Dr. Gary Ray Dr. Jeff Wetzel Prof. Martin Wedepohl Prof. David Pulfrey
Agere Novellus Sematech University of B.C. University of B.C.
Tom Cynkar Dr. Peter George Mike Gilsdorf Dr. Chintamani Palsule Bob Barnes
Agilent Agilent Agilent Agilent Agilent
Loke, Wee & Pfiester
Agilent Technologies Slide 50