In this lecture:

Lecture 8: ROM &

Programmable Logic Devices
• Read-only memory
Dr Pete Sedcole
• Implementing logic with ROM
Department of E&E Engineering
Imperial College London
• Programmable Logic Devices
http://cas.ee.ic.ac.uk/~nps/ • Implementing logic with PLDs
• Static hazards
(Floyd 10.1, 10.3 – 10.5, 11.1 – 11.3)
(Tocci 12.1, 12.4, 12.5, 12.7, 12.8, 13.1 – 13.4)

E1.2 Digital Electronics 1 8.1 7 November 2008 E1.2 Digital Electronics 1 8.2 7 November 2008

Memory terminology

• Memory cell: circuit that stores one bit of information

• Byte: a group of 8 bits
• Word: a group of n bits (usually 8 – 64)
• Capacity:
4096 20-bit words = 81920 bits (written 4096x20 or 4k x 20)
1 kilo (k) = 1024 = 210
1 Mega (M) = 220
1 Giga (G) = 230
• Address
• Read operation
• Write operation

E1.2 Digital Electronics 1 8.3 7 November 2008 E1.2 Digital Electronics 1 8.4 7 November 2008
 A ROM device example
Read-only Memory (ROM)
64x1 bit ROM +5 Volts

• A ROM cell can store one bit of information

• Data can be read but not changed (written) row select BIN/1 of 8
0 8 16 24 32 40 48 56
– although some ROMs can be erased decoder
1 9 17 25 33 41 49 57
– unlike RAM, which can be read and written
18 26 34 42 50 58
• ROM is non-volatile
2 10
A0

– the data is kept even when the power supply to the circuit is A1
3 11 19 27 35 43 51 59

turned off A2
4 12 20 28 36 44 52 60

– the data can be read again after the power is turned back on 5 13 21 29 37 45 53 61

– unlike RAM, which is volatile 6 14 22 30 38 46 54 62

• Applications: 7 15 23 31 39 47 55 63
MUX
– permanent storage of programmes for microprocessors A3 7
OUT
.
.
– look-up tables of data A4 .
0

– implementing combinational logic A5 .} G

0 0_
2 7

E1.2 Digital Electronics 1 8.5 7 November 2008 E1.2 Digital Electronics 1 8.6 7 November 2008

A ROM cell
Row
e
• 64 x 1 bit ROM example: rag
Sto
– 6 address inputs: half are used for selecting the row, and half for 0 or 1 Column
selecting the column
– the row-select decoder energises all 8 cells in one row
– the column-select MUX chooses just one column signal to pass
through to the output • A voltage level is stored to represent a 0 or 1
– column lines are normally “pulled high” by resistors • If the “row-line” is addressed, the switch closes and the stored
– a ROM cell programmed with a 0 pulls the line low voltage appears on the “column-line”
• The switch is implemented with a transistor (typically a MOSFET)

E1.2 Digital Electronics 1 8.7 7 November 2008 E1.2 Digital Electronics 1 8.8 7 November 2008
 Programmable ROMs
Mask Programmed ROM • MROM are inflexible – the data are fixed when the chips are
fabricated
• In a Mask Programmed ROM (MROM): • Programmable ROMs (PROMs) can be programmed after
– The data to be stored in the ROM is fixed at the time of manufacture
manufacture – A fuse is used instead of a wire link
– The presence or absence of a wire determines whether a cell is – Certain types of fuses can be reset under UV light
programmed with a 0 or a 1 • Electrical Erasable PROMs (EEPROMs) use another transistor
instead of a fuse
5V data stored in a
PROM cell EEPROM cell gate capacitance
row line row line

stores column
0 0 stores 0 line 0 column 0
1 line
E1.2 Digital Electronics 1 8.9 7 November 2008 E1.2 Digital Electronics 1 8.10 7 November 2008

Implementing logic with ROM

Different ROM technologies • A 2n x m ROM has n inputs (the address) and m outputs
• E.g.: 24 x 6
Addr[3:0] 16x6 Data[5:0]
ROM

• This can be used to implement logic functions directly

– connect the input signals to the address lines
– programme the ROM data with the truth table
A B C Z Addr (hex) Data (hex)
0 0 0 0 00 00
0 0 1 0 01 00
0 1 0 0 02 00
Truth 0 1 1 1 ROM 03 01
table: 1 0 0 0 contents: 04 00
1 0 1 1 05 01
1 1 0 1 06 01
1 1 1 1 07 01
E1.2 Digital Electronics 1 8.11 7 November 2008 E1.2 Digital Electronics 1 8.12 7 November 2008
 Programmable Logic Devices (PLDs) PALs use programmable
fuses or transistors
similar to PROM
• Several different “architectures” available, but we will only look at the
PAL architecture Original devices in the
1970s used fuses which
• PAL: Programmable Array Logic could not be reset: such
– These implement SOP expressions in canonical form devices were called
– Typically, the SOP expressions can have between 7 to 16 “one-time programmable”
product terms (OTP)

– Construction: a programmable AND section and a fixed OR PALs and CPLDs

section available today usually
use reprogrammable
• CPLD: Complex Programmable Logic Device
fuses
– Larger devices containing several PALs

E1.2 Digital Electronics 1 8.13 7 November 2008 E1.2 Digital Electronics 1 8.14 7 November 2008

PAL architecture
A0 A1 A2 A3 A4 A5 A6 A7
Detail of AND gates in PALs
&
f = A 0. A1. A 3 + "
All inputs and their &
complements are
&
provided >1 &
&
To simplify the f
diagram, only one &
input line is drawn ≥1 f
&
for each AND gate
A dot indicates an & 1 1 1 1
active connection &

A0 A1 A2 A3 the other input

A0 A1 A2 A3 A4 A5 A6 A7
connections are
f = A 0. A1. A 2. A 4. A 6 + A1. A 3. A 4 not shown
E1.2 Digital Electronics 1 8.15 7 November 2008 E1.2 Digital Electronics 1 8.16 7 November 2008
 Summary of combinational logic building blocks • Arithmetic circuits
– binary adders, comparators, multipliers
• Combinational: logic output is a function of the inputs – it has no – need to cope with negative numbers using signed number
memory or storage representations
• Gates • Programmable Logic Devices (PLDs)
– seven fundamental gates from which all other circuits are made – ROMs
– NOT, AND / NAND, OR / NOR, XOR / XNOR • can implement arbitrary logic functions
• Multiplexers • efficient for large combinational logic circuits
– act as switches to connect one output to one of a number of – PLAs (and CPLDs)
input signals • implement canonical SOP Boolean expressions
– can also be used to implement logic functions – Advantages of PLDs
• Decoders • reduction in chip count
– inverted multiplexers • easy to fix bugs and upgrade by reprogramming
– a demultiplexer connects one input to one of a number of outputs – Disadvantages
– also includes circuits such as binary to 7 segment decoders • requires programming equipment

E1.2 Digital Electronics 1 8.17 7 November 2008 E1.2 Digital Electronics 1 8.18 7 November 2008

Avoiding static hazards

Timing and glitches • The case on the previous slide is an example of a static hazard
– the output of the circuit glitches when it shouldn’t change
– in some circuits static hazards can cause malfunctions
• It takes a finite amount of time for a signal to travel through a logic
gate - this is called the “propagation delay” of the gate • To avoid static hazards, use a Karnaugh map and add redundant
groups such that all groups have some overlap
• This delay can cause “glitches” in signals
• Example – consider this circuit which contains an inverter with a A \ BC 00 01 11 10
propagation delay of 2ns
There will be a 2ns window 0 0 0 1 1
f = A B + AC
where B and B are both 1 0 1 1 0
A low - causing a glitch
&
B
Groups A B and AC do not overlap, so are potential hazards
≥1
B Add the group BC so that all groups overlap
1 B
B
C & f = A B + AC + BC
2ns
E1.2 Digital Electronics 1 8.19 7 November 2008 E1.2 Digital Electronics 1 8.20 7 November 2008