In this lecture:

Lecture 13: Applications

• Delaying data
Dr Pete Sedcole • Ring counter
Department of Electrical & Electronic Engineering
Imperial College London • An FSM to detect a sequence
http://cas.ee.ic.ac.uk/~nps/ • A vending machine example
• A stopwatch example

E1.2 Digital Electronics 1 13.1 21 November 2008 E1.2 Digital Electronics 1 13.2 21 November 2008

Adding delay to data Shift register delay element

Synchronous Din Asynchronous Din

• A shift register can be used as a delay element

SRG3 Q0 is Din delayed by 1 clock cycle CLOCK

CLOCK C1
Q1 is Din delayed by 2 clock cycles Din
Din 1D Q0
Q2 is Din delayed by 3 clock cycles Q0
Q1
Q2 Q1

Q2

1 clock period delay >1 clock period delay

E1.2 Digital Electronics 1 13.3 21 November 2008 E1.2 Digital Electronics 1 13.4 21 November 2008
 Ring counter Starting a ring counter
• The ring counter needs to be initialised with data to start with
• A ring counter is constructed from a shift register, with the output of • To load the counter with 1,0,0,0:
the last bit connected back to the input – reset the counter
– then assert START for one clock cycle
SRG3
CLOCK CLOCK
C1
SRG3
RESET R
Din 1D Q0 Q0
CLOCK C1
Q1
Q1 START Din
Q2 ≥1 1D Q0
Q3 Q2 Q1
Q2
Q3 Q3

E1.2 Digital Electronics 1 13.5 21 November 2008 E1.2 Digital Electronics 1 13.6 21 November 2008

A sequence detector Sequence detector state diagram

Use the Mealy model (why?)
• Design a circuit to detect a binary sequence of 1010 in a serial because the output depends on the input and not just the state
bitstream

DATA 0/0 1/0 1/0

Y
CLK 1/0
a b 0/0 c 1/0 d
0/0
CLK
0/1
DATA

Y The state tells us what has a = start (0) b=1

been detected so far: c = 10 d = 101
E1.2 Digital Electronics 1 13.7 21 November 2008 E1.2 Digital Electronics 1 13.8 21 November 2008
 Sequence detector state transition table Sequence detector: design the hardware

CLOCK
Inputs Outputs
S1 S0 D N1 N0 Y C1
1/0 1/0 DATA combinational
0 0 0 0 0 0 0/0 N1 S1
0 0 1 0 1 0 circuit 1D
1/0 N0 S0
?
0 1 0 1 0 0 00 01 0/0 10 1/0 11
0 1 1 0 1 0 Y
0/0
1 0 0 0 0 0
1 0 1 1 1 0 0/1
1 1 0 0 0 1
1 1 1 0 1 0

E1.2 Digital Electronics 1 13.9 21 November 2008 E1.2 Digital Electronics 1 13.10 21 November 2008

Sequence detector: K-maps Sequence detector: Boolean equations

D\S1S0 00 01 11 10 D\S1S0 00 01 11 10
N1:
0 0 1 0 0 Inputs Outputs
N1:
0 0 1 0 0 N1 = D.S1.S 0 + D.S1.S 0
1 0 0 0 1 S1 S0 D N1 N0 Y 1 0 0 0 1
0 0 0 0 0 0
0 0 1 0 1 0
D\S1S0 00 01 11 10 D\S1S0 00 01 11 10
0 1 0 1 0 0
N0:
0 0 0 0 0
0 1 1 0 1 0 N0:
0 0 0 0 0 N0 = D
1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0
1 0 1 1 1 0
D\S1S0 00 01 11 10 1 1 0 0 0 1 D\S1S0 00 01 11 10
Y: 0 0 0 1 0 1 1 1 0 1 0 Y: 0 0 0 1 0 N1 = D.S1.S 0
1 0 0 0 0 1 0 0 0 0

E1.2 Digital Electronics 1 13.11 21 November 2008 E1.2 Digital Electronics 1 13.12 21 November 2008
 A vending machine Vending machine definition

• Design the digital electronics for a coffee vending machine

– The machine accepts 10p and 20p coins
– The price of a coffee is 30p • Assume that:
– As soon as sufficient money has been entered the machine – only one coin at a time
produces a coffee – when a 10p or 20p coin is inserted, it produces a pulse on the
– If two 20p coins are used, the machine returns 10p change p10 or p20 input for one clock cycle
– vend = 1 will produce a coffee
p10 vend
coins coffee – change = 1 will return 10p in change
input digital output
conditioning electronics drivers change
p20 change
clock

E1.2 Digital Electronics 1 13.13 21 November 2008 E1.2 Digital Electronics 1 13.14 21 November 2008

Vending machine state diagram State transition table

Inputs Outputs
Current state p20 p10 Next State vend change
00/00 00/00 00/00
a (0p) 0 0 a 0 0
01/00 Inputs: p10, p20 a (0p) 0 1 b 0 0
a b 01/00 c a (0p) 1 0 c 0 0
01/10 Outputs: vend, change
b (10p) 0 0 b 0 0
10/00
b (10p) 0 1 c 0 0
10/10 State “a” represents 0p credit b (10p) 1 0 a 1 0
01/11 State “b” represents 10p credit c (20p) 0 0 c 0 1
State “c” represents 20p credit c (20p) 0 1 a 1 0
c (20p) 1 0 a 1 1

E1.2 Digital Electronics 1 13.15 21 November 2008 E1.2 Digital Electronics 1 13.16 21 November 2008
 State transition table – assign states Vending machine – design hardware
Inputs Outputs
s1 s0 p20 p10 n1 n0 vend change CLOCK
00 0 0 00 0 0
00 0 1 01 0 0 p10 C1
00 1 0 10 0 0 p20 combinational n1 1D s1
01 0 0 01 0 0 circuit n0 s0
01 0 1 10 0 0 ? vend
01 1 0 00 1 0 change
10 0 0 10 0 0
10 0 1 00 1 0
10 1 0 00 1 1
11 X X 00 0 0

E1.2 Digital Electronics 1 13.17 21 November 2008 E1.2 Digital Electronics 1 13.18 21 November 2008

Vending machine – K-maps Vending machine – K-maps

• For each variable:
vend:
n1: s1s0\p20p10 00 01 11 10
s1s0\p20p10 00 01 11 10
n1 = s1.s 0. p 20 + s1.s 0. p10
00 0 0 X 0 vend = s1.s 0. p 20 + s1.s 0. p 20
00 0 0 X 1 01 0 0 X 1
01 0 1 X 0 + s1.s 0. p 20. p10 11 0 0 X 0 + s1.s 0. p10
11 0 0 X 0 10 0 1 X 1
10 1 0 X 0
change:
n0: s1s0\p20p10 00 01 11 10
s1s0\p20p10 00 01 11 10 00 0 0 X 0
00 0 1 X 0 01 0 0 X 0 change = s1.s 0. p 20
01 1 0 X 0 n0 = s1.s 0. p10 + s1.s 0. p 20. p10 11 0 0 X 0
11 0 0 X 0 10 0 0 X 1
10 0 0 X 0

E1.2 Digital Electronics 1 13.19 21 November 2008 E1.2 Digital Electronics 1 13.20 21 November 2008
 Stopwatch The stopwatch system
5V

• Design a “stop-watch”: START/STOP

– has two buttons, START/STOP and CLEAR digital
SS electronics
– when started, counts minutes and seconds up to 9 minutes 59s
then “wraps around” back to 0m 00s CLEAR

– displays the count on seven segment displays CLEAR

7 7 7
– can be paused and restarted by pressing the START/STOP M[6:0]
button clock
T[6:0]
– if CLEAR is pressed anytime, resets the display to 0m 00s (32768Hz) S[6:0]
– the clock for the system is generated from a 32.768kHz crystal

E1.2 Digital Electronics 1 13.21 21 November 2008 E1.2 Digital Electronics 1 13.22 21 November 2008

Stopwatch: display drivers

Stopwatch: 1Hz clock DEC/7SEG
a
1 b
2 c
d
M[6:0]
4
• To count seconds, it would be best to use a 1Hz clock 8 e
f
• The clock input is 32768Hz g
– How can we generate a 1Hz clock?
DEC/7SEG
– Divide by 215: use 15 divide-by-2 circuits a
1 b
2 c
4 d T[6:0]
8 e
f
clock CLOCK (1Hz)
g
(32768Hz)
DEC/7SEG
a
1 2 3 4 5 … 15 1 b
2 c
4 d S[6:0]
8 e
f
E1.2 Digital Electronics 1 13.23 21 November 2008 E1.2 Digital Electronics 1 13.24 g 21 November 2008
 Stopwatch: counters
DEC/7SEG Stopwatch: 0 – 5 counter
=9 a
EN
1 b
CTR4 2 c
R
d
M[6:0]
[0-9] 4
8 e Inputs/state Next state/output
f
g EN Q2 Q1 Q0 Q2+ Q1+ Q0+ =5
0 X X X Q2 Q1 Q0 0
DEC/7SEG 1 0 0 0 0 0 1 0
=5 a
EN
1 b 1 0 0 1 0 1 0 0
R CTR3 2 c
1 0 1 0 0 1 1 0
[0-5] 4 d T[6:0]
8 e 1 0 1 1 1 0 0 0
f 1 1 0 0 1 0 1 0
0 g
1 1 0 1 0 0 0 1
DEC/7SEG
EN =9 a
1 b
CTR4 2 c
CLEAR R S[6:0]
[0-9] 4 d
8 e
CLOCK
f
E1.2 Digital Electronics 1 13.25 g 21 November 2008 E1.2 Digital Electronics 1 13.26 21 November 2008

Stopwatch: control
DEC/7SEG Stopwatch: FSM
=9 a
EN
1 b
CTR4 2 c • One input (SS), one output (EN)
R
d
M[6:0]
[0-9] 4 – When SS is pressed, enable the counters
8 e
Control f – When SS is pressed again, disable the counters
logic g
• The START/STOP button could be held for several clock cycles
SS DEC/7SEG before being released
EN =5 a
EN
1 b • Therefore, we need a FSM:
R CTR3 2 c
[0-5] 4 d T[6:0] 0
e 1 0
8
CLK f
0 a/0 b/1
g

DEC/7SEG 1
EN =9 a 1
1 b
CTR4 2 c
CLEAR R
[0-9] S[6:0] d/0 0 c/1
4 d
CLOCK 8 e 0 1
f
E1.2 Digital Electronics 1 13.27 g 21 November 2008 E1.2 Digital Electronics 1 13.28 21 November 2008