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Digital Systems Design - Homework Report

Digital Systems Design - Homework Report

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Here is my report for the Digital Systems Design. We had to implement a VHDL design for controlling a 7-segment display with a number shifting every 2 seconds (and by pressing some buttons you have to be able to modify the time of shift).
Here is my report for the Digital Systems Design. We had to implement a VHDL design for controlling a 7-segment display with a number shifting every 2 seconds (and by pressing some buttons you have to be able to modify the time of shift).

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Categories:Types, School Work
Published by: Project Symphony Collection on Feb 21, 2008
Copyright:Attribution Non-commercial

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12/01/2010

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Digital System Design
Homework Report
Vittorio Giovara149374
02/11/2008
 
Part I
Introduction
This report will explain the implementation details of the homework assignment of the course DigitalSystem Design. It will adopt a top-down approach, from the global functionaly to the single moduleoperations.
Board
The chosen board for development of the project is a Diligent Pegasus Board, model Xilinx Spartan2xc2s50-pq208.Figure 1: The adopted board.
Integrated Development Environment
The software application used for implementing the project solution is Xilinx ISE WebPACK 9.2i.
Homework Assignment
The handous for this project are to design a synchronous sequential circuit showing on a seven-segments display the rightmost digit of the matriculation number (4 in this case). Every two secondsthe digit must shift to the left in the next display slot and start over when the last one is reached. Itis possible to duplicate or to divide in half the shift time by pressing BTN1 or BTN0 resplectively.The following assumption has been made: if a button is kept pressed, it sends its input repeat-edly every (about) 200ms, continuously updating the time shift, up to a maximum (and minimum)frequence.1
 
Part II
General Functionality
The solution was reached by implementing several small VHDL modules and then connect them witha schematic file. The next picture shows the connection of the implemented circuit.Figure 2: The schematic view of the solution.The
reset
and
clock
signals are the same for all the modules and there is no commixture of control/timing signals with data signals. The
btn0
and
btn1
inputs are connected to the respectivebuttons on the board (BTN0 and BTN1).
displayer
constantly sends the same number on the
digit
output and changes the value of 
segment
only when the input from
divisor
goes low.It’s
fdivisor
that controls the time shift. At start up it sends the control signal
tc
every twoseconds (active low) and as result
displayer
moves the digit to the next left slot of the display; whenthe last slot is reached the loop goes on from the first. It is possible to modify the time shift by actingon the
button0
and
button1
inputs of 
fdivisor
. The time shift is initialezed every time a button ispressed.When the user presses BTN1 or BTN0 to modify the shift time, the input signal is first filteredby
filterer
and then sent to
fdivsor
. This is done in order not to send additional unwanted inputsdue to bounces of the buttons and the speed of the board processor.The
reset
signal is connected to the BTN3 of the board. When this button is pressed, everymodule is re-initialized and the system correctly restarts.2

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