2010 International Conference

on Reconfigurable Computing

ReConFig 2010

Table of Contents
Message from the Chairs..............................................................................................................................xii
Organizing Committee...................................................................................................................................xiii
Program Committee ........................................................................................................................................xiv
Additional Reviewers ....................................................................................................................................xvii
Keynote Abstract 1 ........................................................................................................................................xviii
Keynote Abstract 2 ..........................................................................................................................................xix

General Sessions
A Minimalistic Architecture for Reconfigurable WFS-Based Immersive-Audio ..........................................................1
Dimitris Theodoropoulos, Georgi Kuzmanov, and Georgi Gaydadjiev
MARC: A Many-Core Approach to Reconfigurable Computing ...................................................................................7
Ilia Lebedev, Shaoyi Cheng, Austin Doupnik, James Martin, Christopher Fletcher,
Daniel Burke, Mingjie Lin, and John Wawrzynek
Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts
of Configuration Memory Space ..................................................................................................................................13
Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Mller-Glaser, and Jrgen Becker
An Efficient Non-blocking Data Cache for Soft Processors ........................................................................................19
Kaveh Aasaraai and Andreas Moshovos
Runtime Task Mapping Based on Hardware Configuration Reuse ..............................................................................25
Kamana Sigdel, Carlo Galuzzi, Koen Bertels, Mark Thompson, and Andy D. Pimentel
Modeling and Formal Control of Partial Dynamic Reconfiguration ............................................................................31
Sbastien Guillet, Florent de Lamotte, ric Rutten, Guy Gogniat, and Jean-Philippe Diguet
Fault Injection Results of Linux Operating on an FPGA Embedded Platform ............................................................37
Joshua S. Monson, Mike Wirthlin, and Brad Hutchings
gNOSIS: A Board-Level Debugging and Verification Tool ........................................................................................43
Ashfaquzzaman Khan, Richard Neil Pittman, and Alessandro Forin

Communication Architectures for Run-Time Reconfigurable Modules in a 2-D Mesh

on FPGAs .....................................................................................................................................................................49
Jochen Strunk, Johannes Hiltscher, Wolfgang Rehm, and Heiko Schick
Hardware Particle Swarm Optimization Based on the Attractive-Repulsive Scheme
for Embedded Applications ..........................................................................................................................................55
Daniel M. Muoz, Carlos H. Llanos, Leandro dos S. Coelho, and Mauricio Ayala-Rincn
FPGA-Based Platform Development for Change Detection in GTAW Welding Process ...........................................61
Ronald H. Hurtado, Sadek C.A. Alfaro, and Carlos H. Llanos
Pruning the Design Space for Just-in-Time Processor Customization .........................................................................67
Mariusz Grad and Christian Plessl
Applying Model-Checking to Post-Silicon-Verification: Bridging
the Specification-Realisation Gap ................................................................................................................................73
O. Dahmoune and R. de B. Johnston
A Dynamically Reconfigured Network Platform for High-Speed Malware Collection ..............................................79
Sascha Mhlbach and Andreas Koch
Design and Implementation of a Visual Fuzzy Control in FPGA for the Ball and Plate
System ..........................................................................................................................................................................85
Marco A. Moreno-Armendriz, Elsa Rubio, and Csar A. Prez-Olvera
Placing Streaming Applications with Similarities on Dynamically Partially
Reconfigurable Architectures .......................................................................................................................................91
J. Angermeier, S. Wildermann, E. Sibirko, and J. Teich
An Application Example of a Run-Time Reconfigurable Embedded System .............................................................97
Daniel Kriesten, Volker Pankalla, and Ulrich Heinkel
Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction
Operations ...................................................................................................................................................................103
Mingjie Lin, Shaoyi Cheng, and John Wawrzynek
UCORE: Reconfigurable Platform for Educational Purposes ....................................................................................109
Francisco J. Quiles, Manuel Ortiz, Maria Brox, Carlos D. Moreno, Javier Hormigo,
and Julio Villalba
A Two Level Architecture for High Throughput DCT-Processor and Implementing
on FPGA .....................................................................................................................................................................115
Azad Fakhari and Mahmood Fathy
Parallel FPGA-Based Implementation of Recursive Sorting Algorithms ..................................................................121
Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, and Alexander Sudnitson
Analysis and Preliminary Measurements of Radiated Emissions in an Asynchronous
Circuit versus its Synchronous Counterpart ...............................................................................................................127
Rui A.L. de Cristo, Ricardo P. Jasinski, and Volnei A. Pedroni
Reconfigurable Digital Audio Mixer for Electroacoustic Music ...............................................................................132
David Pedrosa Branco, Iouliia Skliarova, and Jos Vieira

vi

A Hardware Architecture of an XML/XPath Broker for Content-Based

Publish/Subscribe Systems .........................................................................................................................................138
Fadi El-Hassan and Dan Ionescu
A Runtime Proler: Toward Virtualization of Polymorphic Computing Platforms...................................................144
Hamid Mushtaq, Mojtaba Sabeghi, and Koen Bertels
Improving the Reliability of a FPGA Using Fault-Tolerance Mechanism Based
on Magnetic Memory (MRAM) .................................................................................................................................150
Lus Vitrio Cargnini, Yoann Guillemenet, Lionel Torres, and Gilles Sassatelli
A Novel Hardware Implementation of the Compact Genetic Algorithm ...................................................................156
Marco A. Moreno-Armendriz, Nareli Cruz-Corts, and Alejandro Lon-Javier
Hardware Pessimistic Run-Time Profiling for a Self-Reconfigurable Embedded
Processor Architecture ................................................................................................................................................162
Shady O. Agwa, Hany H. Ahmad, and Awad I. Saleh
Multi-channel Driving Systems for Therapeutic Applications Based-on Focused
Ultrasound ..................................................................................................................................................................168
J. Pindter-Medina, S. Pichardo, L. Curiel, A.D. Garcia-Garcia, and J.E. Chong-Quero
Reconfigurable Node Processing Unit for a Low-Power Wireless Sensor Network .................................................173
Luis A. Vera-Salas, Sandra V. Moreno-Tapia, Roque A. Osornio-Rios,
and Rene de J. Romero-Troncoso
Genetic Algorithms and Artificial Neural Networks to Combinational Circuit
Generation on Reconfigurable Hardware ...................................................................................................................179
Bruno A. Silva, Mauricio A. Dias, Jorge L. Silva, and Fernando S. Osorio
FPGA Implementation of OFDM Transceiver for a 60GHz Wireless Mobile Radio
System ........................................................................................................................................................................185
Khaled Sobaihi, Akram Hammoudeh, and David Scammell

High Performance Reconfigurable Computing

A New Hardware Efficient Inversion Based Random Number Generator
for Non-uniform Distributions ....................................................................................................................................190
Christian de Schryver, Daniel Schmidt, Norbert Wehn, Elke Korn, Henning Marxen,
and Ralf Korn
Performance Analysis of Hardware/Software Middleware in Network of Smart
Camera Systems .........................................................................................................................................................196
Ali Akbar Zarezadeh and Christophe Bobda
Fixed-Point Arithmetic Error Estimation in Monte-Carlo Simulations .....................................................................202
Xiang Tian and Khaled Benkrid
Accelerating 2D FFT with Non-Power-of-Two Problem Size on FPGA ...................................................................208
Wendi Wang, Bo Duan, Chunming Zhang, Peiheng Zhang, and Ninghui Sun

vii

Parallel Data Sort Using Networked FPGAs ..............................................................................................................214

Janardhan Singaraju and John A. Chandy
Issues on Building an MPI Cluster on Microblaze .....................................................................................................220
Juan-Carlos Daz-Martn, Carolina Gmez-Tostn Gutirrez, lvaro Corts Fcila,
and Juan-Antonio Rico-Gallego
Modeling and Simulation of Reconfigurable Processors in Grid Networks ..............................................................226
M. Faisal Nadeem, Mahmood Ahmadi, M. Nadeem, and Stephan Wong
Accelerating Texture Features Extraction Algorithms Using FPGA Architecture ....................................................232
Ali Reza Akoushideh and Asadollah Shahbahrami
Huffman Coding-Based Compression Unit for Embedded Systems ..........................................................................238
Marco Antonio Soto Hernndez, Oscar Alvarado-Nava,
and Francisco Javier Zaragoza Martnez
FPGA-Based Online Detection of Multiple-Combined Faults through Information
Entropy and Neural Networks ....................................................................................................................................244
Eduardo Cabal-Yepez, Ricardo Saucedo-Gallaga, Armando G. Garcia-Ramirez,
Arturo A. Fernandez-Jaramillo, Marcos Pena-Anaya, and Martin Valtierra-Rodriguez
Reconfigurable Cache Implemented on an FPGA ......................................................................................................250
A.D. Santana Gil, J.I. Benavides Benitez, M. Hernandez Calvio, and E. Herruzo Gmez
Hardware Computation of the PageRank Eigenvector ...............................................................................................256
Samas McGettrick and Dermot Geraghty

Reconfigurable Computing for Security and Cryptography

Analysis and Enhancement of Ring Oscillators Based Physical Unclonable Functions
in FPGAs ....................................................................................................................................................................262
Crina Costea, Florent Bernard, Viktor Fischer, and Robert Fouquet
Cross-Correlation Cartography ...................................................................................................................................268
Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, and Yves Mathieu
Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations
on FPGAs ...................................................................................................................................................................274
Shaunak Shah, Rajesh Velegalati, Jens-Peter Kaps, and David Hwang
HCrypt: A Novel Concept of Crypto-processor with Secured Key Management ......................................................280
Lubos Gaspar, Viktor Fischer, Florent Bernard, Lilian Bossuet, and Pascal Cotret
High-Speed FPGA-Based Pseudorandom Generators with Extremely Long Periods ...............................................286
Mieczyslaw Jessa and Michal Jaworski
Skein Tree Hashing on FPGA ....................................................................................................................................292
Aric Schorr and Marcin Lukowiak
Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable
Functions on FPGAs ...................................................................................................................................................298
Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, and Akashi Satoh

viii

Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete Results .......................................................................304

Julien Francq and Cline Thuillet
Evaluation of White-Box and Grey-Box Noekeon Implementations in FPGA .........................................................310
Zouha Cherif, Florent Flament, Jean-Luc Danger, Shivam Bhasin, Sylvain Guilley,
and Herv Chabanne
On FPGA-Based Implementations of the SHA-3 Candidate Grstl ..........................................................................316
Bernhard Jungk and Steffen Reith
An Improved GF(2) Matrix Inverter with Linear Time Complexity ..........................................................................322
Ricardo P. Jasinski, Volnei A. Pedroni, Antonio Gortan, and Walter Godoy Jr.

Multiprocessor Systems and Networks on Chip

Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface ..............................................328
Christoforos Kachris, George Nikiforos, Stamatis Kavadias, Vassilis Papaefstathiou,
and Manolis Katevenis
Merging Programming Models and On-chip Networks to Meet the Programmable
and Performance Needs of Multi-core Systems on a Programmable Chip ................................................................334
Andrew G. Schmidt, William V. Kritikos, Erik K. Anderson, Ron Sass, and Matthew French
A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching
for On-chip Networks .................................................................................................................................................340
Angelo Kuti Lusala and Jean-Didier Legat
A Cost-Effective Solution to Increase System Reliability and Maintain Global
Performance under Unreliable Silicon in MPSoC ......................................................................................................346
Nicolas Hbert, Gabriel Marchesan Almeida, Pascal Benoit, Gilles Sassatelli,
and Lionel Torres
Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis ........................................................352
Cristinel Ababei
Operating System Structures for Multiprocessor Systems on Programmable Chip ...................................................358
Miaoqing Huang, David Andrews, and Jason Agron
Low Power Dual Core Microcontroller ......................................................................................................................364
Rajesh Kannan Megalingam, Ashwin Mohan, Shekhil Hassan Thavalengal,
Tanmay Muralidhar Rao, and Vivek Periye
A Process-Oriented Streaming System Design Paradigm for FPGAs ........................................................................370
Ling Liu and Oleksii Morozov
R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip ........................................................376
Ludovic Devaux, Sebastien Pillement, Daniel Chillet, and Didier Demigny
Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means
of Using a Control-Loop Feedback Mechanism .........................................................................................................382
Gabriel Marchesan Almeida, Sameer Varyani, Rmi Busseuil, Nicolas Hebert,
Gilles Sassatelli, Pascal Benoit, Lionel Torres, and Michel Robert

ix

Power Consumption Calculation of AP-DCD Algorithm Using FPGA Platform .....................................................388

Sasmita Deo

Reconfigurable Computing for DSP and Communications

Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA
Platform ......................................................................................................................................................................394
Mohamed El-Hadedy, Martin Margala, Danilo Gligoroski, and Svein J. Knapskog
Singular Value Decomposition Hardware for MIMO: State of the Art and Custom
Design .........................................................................................................................................................................400
Yue Wang, Kevin Cunningham, Prawat Nagvajara, and Jeremy Johnson
FPGA Implementation of Adjustable Wideband Fractional Delay FIR Filters .........................................................406
G. Ramirez-Conejo, J. Diaz-Carmona, A. Ramirez-Agundis, A. Padilla-Medina,
and J. Delgado-Frias
A Hardware-Efficient Frequency Domain Correlator Architecture for Acquisition
Stage in GPS ...............................................................................................................................................................412
E. Romero-Aguirre, R. Parra-Michel, O. Longoria-Gandara, and M. Aguirre-Hernndez

Reconfiguration Techniques
Using Partial Reconfiguration in an Embedded Message-Passing System ................................................................418
Manuel Saldaa, Arun Patel, Hao Jun Liu, and Paul Chow
Run-Time Reconfiguration for Automatic Hardware/Software Partitioning .............................................................424
Tom Davidson, Karel Bruneel, and Dirk Stroobandt
Configuration Sharing Optimized Placment and Routing ..........................................................................................430
Piotr Stepien and John Cobb
Synthesis and Implementation of Hierarchical Finite State Machines with Implicit
Modules ......................................................................................................................................................................436
Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, and Alexander Sudnitson

Cyber Physical Systems and Image Processing

An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based
on Marching Pixels .....................................................................................................................................................442
Michael Schmidt and Dietmar Fey
Open Source Precision Timed Soft Processor for Cyber Physical System Applications ...........................................448
Stephen Craven, Daniel Long, and Jason Smith
Mapping of a Real-Time Object Detection Application onto a Configurable
RISC/Coprocessor Architecture at Full HD Resolution .............................................................................................452
Holger Flatt, Holger Blume, and Peter Pirsch

Flex-SURF: A Flexible Architecture for FPGA-Based Robust Feature Extraction

for Optical Tracking Systems .....................................................................................................................................458
Michael Schaeferling and Gundolf Kiefer

Author Index .......................................................................................................................................................464

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