(IJCSIS) International Journal of Computer Science and Information Security, Vol. 12, No. 2, February 2014
AN OPTIMIZED MULTIPLIER ARCHITECTURE FOR A DUAL FIELD PROCESSOR FOR ECC
Research Scholar, Department of E & C Engineering VTU, PESCE, Mandya Karnataka, India
Department of E & C Engineering. VTU, PESCE, Mandya Karnataka, India
—This paper presents an optimized multiplier architecture for a Dual field Elliptic curve cryptographic (DF-ECC) processor for both Galois prime field GF(p) and binary field GF(2
), by the selection of proper type of coordinates in the Elliptic curve cryptographic (ECC) arithmetic unit. In this unit, multiplication plays important role to perform scalar multiplication (kP) .We present two multiplier architectures, using FPGA Virtex-5 as the target device. These are, multiplier using carry save adder (CSA) and vedic multiplier. The proposed Dual field ECC processor using Vedic multiplier can reach a speed up to 151MHz.
Keywords- Dual Field ECC; Galois Field; Elliptic curve scalar multiplication;Elliptic curve point addition;Elliptic curve point doubling; Dual field multiplier; Dual field adder;Vedic multiplier;FPGA.
Security plays a vital role in Industrial applications. Normally data will be transmitted or shared through insecure channels. In order to protect the confidential data, cryptography has become very important and striving issue. Accordingly cryptography is mainly used for confidentiality, authentication, data integrity, and non-repudiation. Cryptography can be divided into two types: secret-key cryptography and public-key cryptography. Secret-key cryptography -, which usually has a relatively compact architecture and smaller key size than public-key cryptography, is often used to encrypt/decrypt sensitive information or documents. Elliptic curve cryptography (ECC) is one of the public key crypto-system. Elliptic curve cryptography (ECC) was proposed by Koblitz  and Miller in 1985 . Its attractive feature is smaller key size with the same level of security compared to other cryptographic algorithms like RSA. For example, the security level of 160 and 224 bits ECC is analogous to the 1024 and 2048 bits RSA respectively . Point addition and doubling are key operations of ECC which decide the Performance of ECC. In Refs. ,, architectures are proposed using parallelism and pipelining in both addition and doubling by using the projective coordinates. Scalar multiplication based on Montgomery method is proposed which reduces delay by merging addition and doubling. Multiplication in finite fields takes more time than addition and squaring. Reductions are defined within a multiplier unit to achieve high throughput. A high performance ECC processor based on the Lopez–dahab EC point multiplication was proposed . A dual field ECC processor with projective coordinates adaptive to both binary and prime fields, implemented with carry save adder(CSA) as multiplier was proposed . In  the unified multiplier architecture was proposed, which operates in both fields that is GF(p) and GF(2
).This work proposes a unified architecture for a public key cryptographic processor, that can support both RSA and ECC. In , the theoretical model is used to approximate the delay of critical paths in the elliptic curve scalar multiplier architecture (ECSMA) implemented on k input lookup table (LUT)-based field-programmable gate arrays. In  the implementations of different software algorithms to compute the scalar multiplication based on Elliptic Curve Cryptography (ECC) using five different methods are studied. These are defined for both prime and binary fields. Several improved ECC architectures have been proposed [17-26]. Among them ,&[21-24] are implemented on FPGA platform. Compared to ASIC, FPGA has the advantage that any cryptographic processor can be re-configured or re-programmed based on the security and application requirements. Therefore, Field Programmable Gate Array (FPGA) implementation is well suited platform for cryptographic processors. In ECC, normally two finite fields are used. Those are Binary field known as Galois field GF(2
) and Prime field known as Galois field GF(p). In prime field GF(p) the hardware complexity will be slightly higher than the Binary field GF(2
). Since binary field is suitable for hardware application, as on literature date, only a few hardware implementations are done in prime field GF(p). The organization of this paper is as follows: Mathematical background is defined in Section II. Sections III and IV discuss about CSA and Vedic mathematics. The proposed multiplier architecture is structured in Section V. Section VI presents the Dual field ECC processor. The Experimental results and comparisons are given in Section VII. Finally Section VIII concludes the work. II.
As described in the Specifications for public key cryptography mentioned by IEEE 1363 standard  and recommended by NIST , the standard elliptic curve over GF(2
) is given by, y
+xy = x
+b, where x, y GF(2
) , and b 0. Similarly the standard elliptic curve over GF(p) is
18http://sites.google.com/site/ijcsis/ ISSN 1947-5500