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Ec1461 Vlsi Design

Ec1461 Vlsi Design

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Published by Arunkumar
contains 2 marks and 16 marks dears
it il be very useful
contains 2 marks and 16 marks dears
it il be very useful

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Published by: Arunkumar on Oct 30, 2009
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04/20/2013

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Unit I1. Define Threshold voltage
The threshold voltage V
T
for a MOS transistor can be defined as thevoltage between the gate and the source terminals below which the drainto source current effectively drops to zero.
Define body effect or substrate bias effect.
The threshold voltage V
T
is not a constant with respect to the voltagedifference between the substrate and the source of the MOS transistor.This effect is called the body effect or substrate bias effect.
2. Give the different modes of operation of MOS transistor
Cut off modeLinear modeSaturation mode
3. What are the different regions of operation of a MOS transistor?
a. Cut off regionHere the current flow is essentially zero (accumulation mode)b. Linear regionIt is also called weak inversion region where the drain current isdependent on the gate and the drain voltage w. r. to the substrate.c. Saturation regionChannel is strongly inverted and the drain current flow is ideallyindependent of the drain-source voltage (strong-inversion region).
4. Give the expressions for drain current for different modes of operation of MOS transistor.
a. Cut off regionI
D
=0b. Linear regionI
D
= k 
n
[(V
GS
 
– V
T
) V
DS
– V
DS2
 /2]c. Saturation regionI
D
= (k 
n
 /2) (V
GS
– V
T
)
2
 
 
 
5. Plot the current-voltage characteristics of a nMOS transistor.6. Define accumulation mode.The initial distribution of mobile positive holes in a p type silicon substrate of amos transistor for a voltage much less than the threshold voltage7. What are the secondary effects of MOS transistor?
a. Threshold voltage variationsb. Source to drain resistancec. Variation in I-V characteristicsd. Subthreshold conductione. CMOS latchup
8. What is CMOS latchup? How it can be prevented?
The MOS technology contains a number of intrinsic bipolar transistors.These are especially troublesome in CMOS processes, where thecombination of wells and subtrates results in the formation of p-n-p-nstructures. Triggering these thyristor like devices leads to a shorting of V
DD
& V
SS
lines, usually resulting in a destruction of the chip.The remedies for the latch-up problem include:(i) an increase in substrate doping levels with a consequent drop in the value of R
psubs
.
 
(ii) reducing R
nwell
by control of fabrication parameters and ensuring a lowcontact resistance to V
DD
.(iii) by introducing guard rings.
9. What are the different fabrication processes available to CMOS technology?
a. p-well processb. n-well processc. Twin-tub processd. Silicon On Insulator (SOI) / Silicon On Sapphire (SOS) process

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