Optimization of Spanning Tree Adders

Overview
Compare designs of spanning tree adders in terms of
delay complexity power consumption

Spanning tree adders is an existing category of adders, this paper does not focus on inventing new spanning tree adders but performing experiments on several possible configuration of spanning tree adders.

Introduction to several adders Why spanning tree adders are needed? Experimental result Conclusion future wor!

Agenda
Introduction to "dders #roblem Statement Spanning $ree "dders %esult Conclusion

Introduction to "dders #roblem Statement Spanning $ree "dders %esult Conclusion

Introduction to Adders & Problem Statement

source: http://en.wikipedia.org/ wiki/Adder_(electronics )

&ery brief introduction on several existing adders'

ripple carry adders carry s!ip adders carry loo! ahead adders tree structured adders

(rent)*ung Spanning $ree +ing ,an)Carlson *ogge)Stone

&ery brief introduction on several existing adders'

ripple carry adders carry s!ip adders carry loo! ahead adders tree structured adders

(rent)*ung Spanning $ree +ing ,an)Carlson *ogge)Stone

Propagation Delay
(asically, the performance of adders are evaluated with propagation delay -in this paper.

$ropagation %ela : also called gate dela & the ti#e di''erence between the change o' input and output signals.

source: http://www.seas.upenn. edu/~ese201/lab/Carr ! ookAhead/Carr !ookA head"01.ht#l

%ipple Carry "dders

/oal'

the adder should be able to compute the sum of more than 0 bits Idea' 1ust chain several adders together

source: http://en.wikipedia.org/ wiki/Adder_(electronics )

Pros & Cons

#ros'
straight

forward, easy to implement low power consumption, low resource

source: %.(.)inni#ent& (.%.*arside& +.*ao& A comparison of

Power Consumption in Some CMOS Adder Circuits . ,n: $roceedings o' the "i'th ,nternational -orkshop $A./012345& 0ldenburg& *er#an & ,1+6 7281922 052:2;& pp. 10:2118.

Cons'
slow
a

-high propagation delay.

23)bits adder re4uires 20 carry computations

source: http://en.wikipedia.org/ wiki/Adder_(electronics )

Carry loo! ahead adders

proposed

by Weinberger and Smith in 0567

source: http://en.wikipedia.org/ wiki/Carr _look2 ahead_adder

 carry

loo! ahead adders wor! by creating 8#ropagate9 and 8/enerate9 signals for each bit
#ropagate'

controls whether a carry is propagated from lower bits to higher bits /enerate' controls whether a carry is generated

:)bits carry loo! ahead adder

source: http://www.seas.upen n.edu/~ese201/lab/Ca rr !ookAhead/Carr !ookAhead"01.ht#l

Pros & Cons

#ros'
faster

than ripple)carry adders, since some computation can be done in advance

'or e<a#ple& part o' C9 can be pre2co#puted a'ter C0& $0& *0 are known

Cons'
much

more complicated when ; : bits http'<<www.seas.upenn.edu<=ese3>0<lab<Carry+oo . the carry loo! ahead bloc! re4uires gates with more than 3 input, which may cause efficiency problems -according to @egha +adhaA Earl E. SwartBlander, Cr .

Alternatives
"lternatives'
improved

carry loo! ahead adders' +ing

adders tree)style adders to decrease input numbers for each level'

*ogge)Stone

"dder (rent)*ung "dder ,an)Carlson "dder Spanning $ree "dder

)ogge21tone Adder

+rent2)ung Adder source: http://www.acsel2 lab.co#/$ro=ects/'ast_adder/a dder_designs.ht#

Introduction to "dders #roblem Statement Spanning $ree "dders %esult Conclusion

Spanning Tree Adder STA!

Spanning tree adder
use minimum number of multi)input gates ,ybrid adder

@anchester Carry Chain -@CC.

use ripple carries #ropagate rapidly SiBe of @CC is a trade of D of inputs D of levels

MCC

32-bit STA

STA based on "CC

/i'1E@CC3-/i'!)0, /!'1, #i'!)0, #!'1. /i'1E@CC2-/i'!)0, /!'m)0, /m'1, #i'!)0, #!'m)0, #!'1. CiE/>'i)0

Carry Select Adder CSA!

$wo sum outputs'
"ssumed carry input as > "ssumed carry input as 0

D of @CC level is decided by the siBe of final stage CS"

m)bits wide CS" %e4uire C , C , C F m 3m 2m

carry select adder

?inal stage adder'

if m is large carry select adder ta!es more time if m is mall need more @CC levels

7)bits wide carry select adder : sum outputs

Introduction to "dders #roblem Statement Spanning $ree "dders %esult Conclusion

"ain Comparion
0G)bit vs. 23)bit adders C+" vs. Spanning tree adders :)bit, 7)bit, 0G)bit %C" vs. CS" @easure' Helay, complexity, power consumption
Helay

and power consumption are performed with Synopsys and Cadence

#$%bit vs& '(%bit Adders

1:2bit spanning tree

722bit spanning tree 1i>e o' C1A ?: %ela o' /CC @& C1A ?

)%bit* +%bit* #$%bit ,CA vs& CSA % Delay

1: and 722bit spanning tree with C1A and ACA in 'inal stage

%ela : B<cept 92bit #odule& C1A is better

)%bit* +%bit* #$%bit ,CA vs& CSA % Comple-ity

1: and 722bit spanning tree with C1A and ACA in 'inal stage

Co#ple<it : Al#ost the sa#e

)%bit* +%bit* #$%bit ,CA vs& CSA % Power Consumption

1: and 722bit spanning tree with C1A and ACA in 'inal stage

1i>e o' "inal Adders ?: $ower Consu#ption @

C.A vs& Spanning tree adders % Delay

1: and 722bit C!A and 0pti#u# 1panning .ree(01.) Aatio o' %ela : 72bit decreases #ore

C.A vs& Spanning tree adders % Comple-ity

1: and 722bit C!A and 0pti#u# 1panning .ree(01.) Aatio o' Co#ple<it : 72bit increases less

C.A vs& Spanning tree adders % Power Consumption

1: and 722bit C!A and 0pti#u# 1panning .ree(01.) Aatio o' $ower Consu#ption: Al#ost the sa#e

Conclusion
#erformance'
In

0G)bit Spanning tree adder, :)bit, %C" and CS" are the same In 23)bit Spanning tree adder, 7)bit above, %C" is better Spanning tree is more ideal for larger siBe.

/uture 0or1
Ise transistor to design final adders and @CC bloc!s SiBed for optimum performance Ise transistor multiplexer instead of gate level multiplexer

Some Ot2ers 3 IC Design

+anguage level' +i!e C language /ate level' "ssembly language $ransistor level' @achine code